From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 31314 invoked by alias); 3 Feb 2016 16:45:41 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 31300 invoked by uid 89); 3 Feb 2016 16:45:40 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD,SPF_HELO_PASS autolearn=ham version=3.3.2 spammy=cie, Hx-languages-length:1545 X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Wed, 03 Feb 2016 16:45:39 +0000 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (Postfix) with ESMTPS id 4F3FAE1B77 for ; Wed, 3 Feb 2016 16:45:38 +0000 (UTC) Received: from pinnacle.lan (ovpn-113-155.phx2.redhat.com [10.3.113.155]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u13Gjbtg015124 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA256 bits=256 verify=NO) for ; Wed, 3 Feb 2016 11:45:38 -0500 Date: Wed, 03 Feb 2016 16:45:00 -0000 From: Kevin Buettner To: gdb-patches@sourceware.org Subject: Re: [patch] [v2] Enable dwarf unwind for AVR target Message-ID: <20160203094534.0ec066aa@pinnacle.lan> In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2016-02/txt/msg00075.txt.bz2 On Fri, 8 Jan 2016 08:52:33 +0000 "Sivanupandi, Pitchumani" wrote: > Dwarf debug info generated by avr-gcc denotes the return address by register > 36 which is not an actual register. > e.g. .debug_frame > (--snip--) > 00000000 00000010 ffffffff CIE > Version: 1 > Augmentation: "" > Code alignment factor: 2 > Data alignment factor: -1 > Return address column: 36 > > DW_CFA_def_cfa: r32 ofs 3 > DW_CFA_offset: r36 at cfa-2 > (--snip--) > > The fix is to add a pseudo register (36 - AVR_DWARF2_PC_REGNUM/LR) to gdb to > map return address register. Register name is "LR" (link register). When dwarf > frame unwind asks for PC, target function will read return address value from > AVR_DWARF2_PC_REGNUM's CFA address. The usual way to handle this problem is to define a dwarf2_reg_to_regnum method which maps the index of DWARF's return address column to GDB's PC register. So, for the AVR, you'd map 36 to 35. If you do this, I think you can dispense with all of the stuff which adds and manipulates the pseudo-register. Here's an example (from rx-tdep.c) where this is done: static int rx_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) { if (0 <= reg && reg <= 15) return reg; else if (reg == 16) return RX_PSW_REGNUM; else if (reg == 17) return RX_PC_REGNUM; else return -1; } Then, in rx_gdbarch_init, this function is registered as follows: set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rx_dwarf_reg_to_regnum); Hope this helps... Kevin