From: Kamil Rytarowski <n54@gmx.com>
To: jhb@FreeBSD.org
Cc: gdb-patches@sourceware.org, Kamil Rytarowski <n54@gmx.com>
Subject: [PATCH] Rename __BIT() to __ONEBIT() in the nds32 target
Date: Tue, 05 Sep 2017 22:52:00 -0000 [thread overview]
Message-ID: <20170905224019.18860-1-n54@gmx.com> (raw)
The __BIT() macro used by the nds32 code conflicts with the NetBSD
header <sys/cdefs.h> with a different __BIT() implementation,
althought used for the same purpose.
Remove the conflict with renaming __BIT() to __ONEBIT().
include/ChangeLog
2017-09-05 Kamil Rytarowski <n54@gmx.com>
* opcode/nds32.h: Rename __BIT() to __ONEBIT().
opcodes/ChangeLog
2017-09-05 Kamil Rytarowski <n54@gmx.com>
* nds32-asm.c: Rename __BIT() to __ONEBIT().
* nds32-asm.h: Likewise.
* nds32-dis.c: Likewise.
---
bfd/elf32-nds32.c | 26 +++++++++---------
include/ChangeLog | 4 +++
include/opcode/nds32.h | 4 +--
opcodes/ChangeLog | 6 +++++
opcodes/nds32-asm.c | 72 +++++++++++++++++++++++++-------------------------
opcodes/nds32-asm.h | 2 +-
opcodes/nds32-dis.c | 6 ++---
7 files changed, 65 insertions(+), 55 deletions(-)
diff --git a/bfd/elf32-nds32.c b/bfd/elf32-nds32.c
index b5f59e7646..39fed5af08 100644
--- a/bfd/elf32-nds32.c
+++ b/bfd/elf32-nds32.c
@@ -7343,7 +7343,7 @@ nds32_convert_32_to_16 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
if (!IS_WITHIN_S (N32_IMM14S (insn), 8))
goto done;
- if ((insn & __BIT (14)) == 0)
+ if ((insn & __ONEBIT (14)) == 0)
{
/* N32_BR1_BEQ */
if (N32_IS_RT3 (insn) && N32_RA5 (insn) == REG_R5
@@ -7411,7 +7411,7 @@ nds32_convert_32_to_16 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
break;
case N32_OP6_JI:
- if ((insn & __BIT (24)) == 0)
+ if ((insn & __ONEBIT (24)) == 0)
{
/* N32_JI_J */
if (IS_WITHIN_S (N32_IMM24S (insn), 8))
@@ -7647,7 +7647,7 @@ nds32_convert_16_to_32 (bfd *abfd, uint16_t insn16, uint32_t *pinsn)
insn = N32_TYPE2 (SLTI, REG_TA, N16_RT4 (insn16), N16_IMM5U (insn16));
goto done;
case 0x34: /* beqzs8, bnezs8 */
- if (insn16 & __BIT (8))
+ if (insn16 & __ONEBIT (8))
insn = N32_BR2 (BNEZ, REG_TA, N16_IMM8S (insn16));
else
insn = N32_BR2 (BEQZ, REG_TA, N16_IMM8S (insn16));
@@ -7747,7 +7747,7 @@ nds32_convert_16_to_32 (bfd *abfd, uint16_t insn16, uint32_t *pinsn)
switch (__GF (insn16, 11, 4))
{
case 0x7: /* lwi37.fp/swi37.fp */
- if (insn16 & __BIT (7)) /* swi37.fp */
+ if (insn16 & __ONEBIT (7)) /* swi37.fp */
insn = N32_TYPE2 (SWI, N16_RT38 (insn16), REG_FP, N16_IMM7U (insn16));
else /* lwi37.fp */
insn = N32_TYPE2 (LWI, N16_RT38 (insn16), REG_FP, N16_IMM7U (insn16));
@@ -7850,7 +7850,7 @@ turn_insn_to_sda_access (uint32_t insn, bfd_signed_vma type, uint32_t *pinsn)
break;
case N32_OP6_LBSI:
/* lbsi.gp */
- oinsn = N32_TYPE1 (LBGP, N32_RT5 (insn), __BIT (19));
+ oinsn = N32_TYPE1 (LBGP, N32_RT5 (insn), __ONEBIT (19));
break;
case N32_OP6_SBI:
/* sbi.gp */
@@ -7858,7 +7858,7 @@ turn_insn_to_sda_access (uint32_t insn, bfd_signed_vma type, uint32_t *pinsn)
break;
case N32_OP6_ORI:
/* addi.gp */
- oinsn = N32_TYPE1 (SBGP, N32_RT5 (insn), __BIT (19));
+ oinsn = N32_TYPE1 (SBGP, N32_RT5 (insn), __ONEBIT (19));
break;
}
break;
@@ -7872,11 +7872,11 @@ turn_insn_to_sda_access (uint32_t insn, bfd_signed_vma type, uint32_t *pinsn)
break;
case N32_OP6_LHSI:
/* lhsi.gp */
- oinsn = N32_TYPE1 (HWGP, N32_RT5 (insn), __BIT (18));
+ oinsn = N32_TYPE1 (HWGP, N32_RT5 (insn), __ONEBIT (18));
break;
case N32_OP6_SHI:
/* shi.gp */
- oinsn = N32_TYPE1 (HWGP, N32_RT5 (insn), __BIT (19));
+ oinsn = N32_TYPE1 (HWGP, N32_RT5 (insn), __ONEBIT (19));
break;
}
break;
@@ -11319,7 +11319,7 @@ nds32_elf_relax_pltgot_suff (struct bfd_link_info *link_info, bfd *abfd,
irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
R_NDS32_PLT_GOTREL_LO19);
/* addi.gp */
- insn = N32_TYPE1 (SBGP, N32_RT5 (insn), __BIT (19));
+ insn = N32_TYPE1 (SBGP, N32_RT5 (insn), __ONEBIT (19));
}
else if (N32_OP6 (insn) == N32_OP6_JREG
&& N32_SUB5 (insn) == N32_JREG_JRAL)
@@ -11452,12 +11452,12 @@ nds32_elf_relax_gotoff_suff (struct bfd_link_info *link_info, bfd *abfd,
ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_NDS32_SDA18S1_RELA);
break;
case (N32_OP6_MEM << 8) | N32_MEM_LHS:
- insn = N32_TYPE1 (HWGP, N32_RT5 (insn), __BIT (18));
+ insn = N32_TYPE1 (HWGP, N32_RT5 (insn), __ONEBIT (18));
irel->r_info =
ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_NDS32_SDA18S1_RELA);
break;
case (N32_OP6_MEM << 8) | N32_MEM_SH:
- insn = N32_TYPE1 (HWGP, N32_RT5 (insn), __BIT (19));
+ insn = N32_TYPE1 (HWGP, N32_RT5 (insn), __ONEBIT (19));
irel->r_info =
ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_NDS32_SDA18S1_RELA);
break;
@@ -11468,7 +11468,7 @@ nds32_elf_relax_gotoff_suff (struct bfd_link_info *link_info, bfd *abfd,
ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_NDS32_SDA19S0_RELA);
break;
case (N32_OP6_MEM << 8) | N32_MEM_LBS:
- insn = N32_TYPE1 (LBGP, N32_RT5 (insn), __BIT (19));
+ insn = N32_TYPE1 (LBGP, N32_RT5 (insn), __ONEBIT (19));
irel->r_info =
ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_NDS32_SDA19S0_RELA);
break;
@@ -11478,7 +11478,7 @@ nds32_elf_relax_gotoff_suff (struct bfd_link_info *link_info, bfd *abfd,
ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_NDS32_SDA19S0_RELA);
break;
case (N32_OP6_ALU1 << 8) | N32_ALU1_ADD:
- insn = N32_TYPE1 (SBGP, N32_RT5 (insn), __BIT (19));
+ insn = N32_TYPE1 (SBGP, N32_RT5 (insn), __ONEBIT (19));
irel->r_info =
ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_NDS32_SDA19S0_RELA);
break;
diff --git a/include/ChangeLog b/include/ChangeLog
index 2845f8574c..67bed3bdc8 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2017-09-05 Kamil Rytarowski <n54@gmx.com>
+
+ * opcode/nds32.h: Rename __BIT() to __ONEBIT().
+
2017-09-05 Alexander Fedotov <alexander.fedotov@nxp.com>
Edmar Wienskoski <edmar.wienskoski@nxp.com
diff --git a/include/opcode/nds32.h b/include/opcode/nds32.h
index 95e5f8ce3c..bcbfe8a0ce 100644
--- a/include/opcode/nds32.h
+++ b/include/opcode/nds32.h
@@ -50,8 +50,8 @@ static const int nds32_r54map[] ATTRIBUTE_UNUSED =
-1, -1, -1, -1, -1, -1, -1, -1
};
-#define __BIT(n) (1 << (n))
-#define __MASK(n) (__BIT (n) - 1)
+#define __ONEBIT(n) (1 << (n))
+#define __MASK(n) (__ONEBIT (n) - 1)
#define __MF(v, off, bs) (((v) & __MASK (bs)) << (off))
#define __GF(v, off, bs) (((v) >> off) & __MASK (bs))
#define __SEXT(v, bs) ((((v) & ((1 << (bs)) - 1)) ^ (1 << ((bs) - 1))) - (1 << ((bs) - 1)))
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b8c1586ae4..37a354c049 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2017-09-05 Kamil Rytarowski <n54@gmx.com>
+
+ * nds32-asm.c: Rename __BIT() to __ONEBIT().
+ * nds32-asm.h: Likewise.
+ * nds32-dis.c: Likewise.
+
2017-08-31 Nick Clifton <nickc@redhat.com>
* po/fr.po: Updated French translation.
diff --git a/opcodes/nds32-asm.c b/opcodes/nds32-asm.c
index 90e25975e8..c0f5b49bbd 100644
--- a/opcodes/nds32-asm.c
+++ b/opcodes/nds32-asm.c
@@ -212,8 +212,8 @@ const field_t operand_fields[] =
{NULL, 0, 0, 0, 0, NULL}
};
-#define DEF_REG(r) (__BIT (r))
-#define USE_REG(r) (__BIT (r))
+#define DEF_REG(r) (__ONEBIT (r))
+#define USE_REG(r) (__ONEBIT (r))
#define RT(r) (r << 20)
#define RA(r) (r << 15)
#define RB(r) (r << 10)
@@ -252,29 +252,29 @@ struct nds32_opcode nds32_opcodes[] =
/* seg-DPREFI. */
{"dprefi.w", "%dpref_st,[%ra{+%i15s2}]", OP6 (DPREFI), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
- {"dprefi.d", "%dpref_st,[%ra{+%i15s3}]", OP6 (DPREFI) | __BIT (24), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+ {"dprefi.d", "%dpref_st,[%ra{+%i15s3}]", OP6 (DPREFI) | __ONEBIT (24), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
/* seg-LBGP. */
{"lbi.gp", "=rt,[+%i19s]", OP6 (LBGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
- {"lbsi.gp", "=rt,[+%i19s]", OP6 (LBGP) | __BIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
+ {"lbsi.gp", "=rt,[+%i19s]", OP6 (LBGP) | __ONEBIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
/* seg-LWC/0. */
{"cplwi", "%cp,=cprt,[%ra{+%i12s2}]", OP6 (LWC), 4, 0, 0, NULL, 0, NULL},
- {"cplwi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (LWC) | __BIT (12), 4, 0, 0, NULL, 0, NULL},
+ {"cplwi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (LWC) | __ONEBIT (12), 4, 0, 0, NULL, 0, NULL},
/* seg-SWC/0. */
{"cpswi", "%cp,=cprt,[%ra{+%i12s2}]", OP6 (SWC), 4, 0, 0, NULL, 0, NULL},
- {"cpswi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (SWC) | __BIT (12), 4, 0, 0, NULL, 0, NULL},
+ {"cpswi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (SWC) | __ONEBIT (12), 4, 0, 0, NULL, 0, NULL},
/* seg-LDC/0. */
{"cpldi", "%cp,%cprt,[%ra{+%i12s2}]", OP6 (LDC), 4, 0, 0, NULL, 0, NULL},
- {"cpldi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (LDC) | __BIT (12), 4, 0, 0, NULL, 0, NULL},
+ {"cpldi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (LDC) | __ONEBIT (12), 4, 0, 0, NULL, 0, NULL},
/* seg-SDC/0. */
{"cpsdi", "%cp,%cprt,[%ra{+%i12s2}]", OP6 (SDC), 4, 0, 0, NULL, 0, NULL},
- {"cpsdi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (SDC) | __BIT (12), 4, 0, 0, NULL, 0, NULL},
+ {"cpsdi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (SDC) | __ONEBIT (12), 4, 0, 0, NULL, 0, NULL},
/* seg-LSMW. */
{"lmw", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMW), 4, ATTR_ALL, 0, NULL, 0, NULL},
{"lmwa", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMWA), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
{"lmwzb", "%abm %rt,[%ra],%re{,%enb4}", LSMW (LSMWZB), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
- {"smw", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMW) | __BIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL},
- {"smwa", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMWA) | __BIT (5), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
- {"smwzb", "%abm %rt,[%ra],%re{,%enb4}", LSMW (LSMWZB) | __BIT (5), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
+ {"smw", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMW) | __ONEBIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL},
+ {"smwa", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMWA) | __ONEBIT (5), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
+ {"smwzb", "%abm %rt,[%ra],%re{,%enb4}", LSMW (LSMWZB) | __ONEBIT (5), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
/* seg-HWGP. */
{"lhi.gp", "=rt,[+%i18s1]", OP6 (HWGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
{"lhsi.gp", "=rt,[+%i18s1]", OP6 (HWGP) | (2 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
@@ -284,10 +284,10 @@ struct nds32_opcode nds32_opcodes[] =
/* seg-SBGP. */
{"sbi.gp", "%rt,[+%i19s]", OP6 (SBGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
- {"addi.gp", "=rt,%i19s", OP6 (SBGP) | __BIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
+ {"addi.gp", "=rt,%i19s", OP6 (SBGP) | __ONEBIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
/* seg-JI. */
{"j", "%i24s1", OP6 (JI), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
- {"jal", "%i24s1", OP6 (JI) | __BIT (24), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
+ {"jal", "%i24s1", OP6 (JI) | __ONEBIT (24), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
/* seg-JREG. */
{"jr", "%rb", JREG (JR), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
{"jral", "%rt,%rb", JREG (JRAL), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
@@ -304,7 +304,7 @@ struct nds32_opcode nds32_opcodes[] =
{"jral", "%dtiton %rb", JREG (JRAL) | RT (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
/* seg-BR1. */
{"beq", "%rt,%ra,%i14s1", OP6 (BR1), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
- {"bne", "%rt,%ra,%i14s1", OP6 (BR1) | __BIT (14), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
+ {"bne", "%rt,%ra,%i14s1", OP6 (BR1) | __ONEBIT (14), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
/* seg-BR2. */
#define BR2(sub) (OP6 (BR2) | (N32_BR2_ ## sub << 16))
{"ifcall", "%i16s1", BR2 (IFCALL), 4, ATTR (IFC_EXT), 0, NULL, 0, NULL},
@@ -318,7 +318,7 @@ struct nds32_opcode nds32_opcodes[] =
{"bltzal", "%rt,%i16s1", BR2 (BLTZAL), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
/* seg-BR3. */
{"beqc", "%rt,%i11br3,%i8s1", OP6 (BR3), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL},
- {"bnec", "%rt,%i11br3,%i8s1", OP6 (BR3) | __BIT (19), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL},
+ {"bnec", "%rt,%i11br3,%i8s1", OP6 (BR3) | __ONEBIT (19), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL},
/* seg-SIMD. */
{"pbsad", "%rt,%ra,%rb", SIMD (PBSAD), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL},
{"pbsada", "%rt,%ra,%rb", SIMD (PBSADA), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL},
@@ -392,22 +392,22 @@ struct nds32_opcode nds32_opcodes[] =
/* seg-ALU2_FFBI. */
{"ffb", "=rt,%ra,%rb", ALU2 (FFB), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
- {"ffbi", "=rt,%ra,%ib8u", ALU2 (FFBI) | __BIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
+ {"ffbi", "=rt,%ra,%ib8u", ALU2 (FFBI) | __ONEBIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
/* seg-ALU2_FLMISM. */
{"ffmism", "=rt,%ra,%rb", ALU2 (FFMISM), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
- {"flmism", "=rt,%ra,%rb", ALU2 (FLMISM) | __BIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
+ {"flmism", "=rt,%ra,%rb", ALU2 (FLMISM) | __ONEBIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
/* seg-ALU2_MULSR64. */
{"mults64", "=dt,%ra,%rb", ALU2 (MULTS64), 4, ATTR_ALL, 0, NULL, 0, NULL},
- {"mulsr64", "=rt,%ra,%rb", ALU2 (MULSR64)| __BIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
+ {"mulsr64", "=rt,%ra,%rb", ALU2 (MULSR64)| __ONEBIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
/* seg-ALU2_MULR64. */
{"mult64", "=dt,%ra,%rb", ALU2 (MULT64), 4, ATTR_ALL, 0, NULL, 0, NULL},
- {"mulr64", "=rt,%ra,%rb", ALU2 (MULR64) | __BIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
+ {"mulr64", "=rt,%ra,%rb", ALU2 (MULR64) | __ONEBIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
/* seg-ALU2_MADDR32. */
{"madd32", "=dt,%ra,%rb", ALU2 (MADD32), 4, ATTR (MAC) | ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL},
- {"maddr32", "=rt,%ra,%rb", ALU2 (MADDR32) | __BIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL},
+ {"maddr32", "=rt,%ra,%rb", ALU2 (MADDR32) | __ONEBIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL},
/* seg-ALU2_MSUBR32. */
{"msub32", "=dt,%ra,%rb", ALU2 (MSUB32), 4, ATTR (MAC) | ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL},
- {"msubr32", "=rt,%ra,%rb", ALU2 (MSUBR32) | __BIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL},
+ {"msubr32", "=rt,%ra,%rb", ALU2 (MSUBR32) | __ONEBIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL},
/* seg-MISC. */
{"standby", "%stdby_st", MISC (STANDBY), 4, ATTR_ALL, 0, NULL, 0, NULL},
@@ -425,11 +425,11 @@ struct nds32_opcode nds32_opcodes[] =
/* seg-MISC_MTSR. */
{"mtsr", "%rt,%sr", MISC (MTSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
/* seg-MISC_SETEND. */
- {"setend.l", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __BIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL},
- {"setend.b", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __BIT (5) | __BIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL},
+ {"setend.l", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __ONEBIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL},
+ {"setend.b", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __ONEBIT (5) | __ONEBIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL},
/* seg-MISC_SETGIE. */
- {"setgie.d", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __BIT (6), 4, ATTR_ALL, 0, NULL, 0, NULL},
- {"setgie.e", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __BIT (6) | __BIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL},
+ {"setgie.d", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __ONEBIT (6), 4, ATTR_ALL, 0, NULL, 0, NULL},
+ {"setgie.e", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __ONEBIT (6) | __ONEBIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL},
{"mfsr", "=rt,%ridx", MISC (MFSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
{"mtsr", "%rt,%ridx", MISC (MTSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
{"trap", "", MISC (TRAP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
@@ -764,19 +764,19 @@ struct nds32_opcode nds32_opcodes[] =
/* Saturation ext ISA. */
{"kaddw", "=rt,%ra,%rb", ALU2 (KADD), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
{"ksubw", "=rt,%ra,%rb", ALU2 (KSUB), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"kaddh", "=rt,%ra,%rb", ALU2 (KADD) | __BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"ksubh", "=rt,%ra,%rb", ALU2 (KSUB) | __BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
+ {"kaddh", "=rt,%ra,%rb", ALU2 (KADD) | __ONEBIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
+ {"ksubh", "=rt,%ra,%rb", ALU2 (KSUB) | __ONEBIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
{"kdmbb", "=rt,%ra,%rb", ALU2 (KMxy), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"kdmbt", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"kdmtb", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"kdmtt", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (6) | __BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"khmbb", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (8), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"khmbt", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (8) | __BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"khmtb", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (8) | __BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"khmtt", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (8) | __BIT (6) | __BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
+ {"kdmbt", "=rt,%ra,%rb", ALU2 (KMxy) | __ONEBIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
+ {"kdmtb", "=rt,%ra,%rb", ALU2 (KMxy) | __ONEBIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
+ {"kdmtt", "=rt,%ra,%rb", ALU2 (KMxy) | __ONEBIT (6) | __ONEBIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
+ {"khmbb", "=rt,%ra,%rb", ALU2 (KMxy) | __ONEBIT (8), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
+ {"khmbt", "=rt,%ra,%rb", ALU2 (KMxy) | __ONEBIT (8) | __ONEBIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
+ {"khmtb", "=rt,%ra,%rb", ALU2 (KMxy) | __ONEBIT (8) | __ONEBIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
+ {"khmtt", "=rt,%ra,%rb", ALU2 (KMxy) | __ONEBIT (8) | __ONEBIT (6) | __ONEBIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
{"kslraw", "=rt,%ra,%rb", ALU2 (KSLRA), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"rdov", "=rt", ALU2 (MFUSR) | __BIT (6) | ( 0x1e << 15), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"clrov", "", ALU2 (MTUSR) | __BIT (6) | ( 0x1e << 15), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
+ {"rdov", "=rt", ALU2 (MFUSR) | __ONEBIT (6) | ( 0x1e << 15), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
+ {"clrov", "", ALU2 (MTUSR) | __ONEBIT (6) | ( 0x1e << 15), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
/* Audio ext. instructions. */
diff --git a/opcodes/nds32-asm.h b/opcodes/nds32-asm.h
index e5d5554955..9a32c91402 100644
--- a/opcodes/nds32-asm.h
+++ b/opcodes/nds32-asm.h
@@ -279,7 +279,7 @@ extern void nds32_asm_init (nds32_asm_desc_t *, int);
#define ALU2(sub) (OP6 (ALU2) | N32_ALU2_ ## sub)
#define MISC(sub) (OP6 (MISC) | N32_MISC_ ## sub)
#define MEM(sub) (OP6 (MEM) | N32_MEM_ ## sub)
-#define FPU_RA_IMMBI(sub) (OP6 (sub) | __BIT (12))
+#define FPU_RA_IMMBI(sub) (OP6 (sub) | __ONEBIT (12))
#define FS1(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_ ## sub << 6))
#define FS1_F2OP(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_F2OP << 6) \
| (N32_FPU_FS1_F2OP_ ## sub << 10))
diff --git a/opcodes/nds32-dis.c b/opcodes/nds32-dis.c
index 4ee3bb5cb4..2bd57f3676 100644
--- a/opcodes/nds32-dis.c
+++ b/opcodes/nds32-dis.c
@@ -759,10 +759,10 @@ nds32_mask_opcode (uint32_t insn)
return MASK_OP (insn, 0);
case N32_OP6_ALU2:
/* FFBI */
- if (__GF (insn, 0, 7) == (N32_ALU2_FFBI | __BIT (6)))
+ if (__GF (insn, 0, 7) == (N32_ALU2_FFBI | __ONEBIT (6)))
return MASK_OP (insn, 0x7f);
- else if (__GF (insn, 0, 7) == (N32_ALU2_MFUSR | __BIT (6))
- || __GF (insn, 0, 7) == (N32_ALU2_MTUSR | __BIT (6)))
+ else if (__GF (insn, 0, 7) == (N32_ALU2_MFUSR | __ONEBIT (6))
+ || __GF (insn, 0, 7) == (N32_ALU2_MTUSR | __ONEBIT (6)))
/* RDOV CLROV */
return MASK_OP (insn, 0xf81ff);
return MASK_OP (insn, 0x1ff);
--
2.14.1
next reply other threads:[~2017-09-05 22:52 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-05 22:52 Kamil Rytarowski [this message]
2017-09-06 0:02 ` Pedro Alves
2017-09-06 15:23 ` [PATCH v2] Rename __BIT() to N32_BIT() " Kamil Rytarowski
2017-09-06 17:11 ` Pedro Alves
2017-09-09 2:00 ` Kamil Rytarowski
2017-09-11 6:45 ` Kuan-Lin Chen
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