[PATCH v2 0/3] Support large registers in regcache transfer_regset

[Alan Hayward <alan.hayward@arm.com>]

Support core file reading/writing where the register size is either greater
or smaller than the space allocated to it in the core file.

This will prevent assert failures on Aarch64 SVE.

Whilst writing this patch I spotted potential issue for aarch64. The 32bit
CPSR register has a 64bit slot in the core file. The existing transfer_regset
did not ensure the extra 32bits were null padded.

This version addresses all the review comments for V1, and splits up into
smaller chunks.

Patch 1 will enble patch 3 to use unsigned ints.
Patch 2 is a cleanup of exisiting code.
Patch 3 fixes the two issues.

I did not update read_part/write_part to use unsigned ints as that would
have required spiralled out to quite a few target file changes.

Tested by generating cores on aarch64 and aarch64 sve, both via gdb and the
kernel, then ensuring the cores load back on the both systems.
Checked cores on x86 still look ok.
Ran make check on x86 and aarch64.


Alan Hayward (3):
  Use unsigned ints in regcache_map_entry All current uses of
    regcache_map_entry use static hard coded values.
  Avoid memcpys in regcache read_part/write_part for full registers.
  Use partial register read/writes in transfer_regset

 gdb/regcache.c | 189 ++++++++++++++++++++++++++++++++++++++++-----------------
 gdb/regcache.h |  26 ++++++--
 2 files changed, 154 insertions(+), 61 deletions(-)

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