From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15284 invoked by alias); 21 Jun 2018 09:39:02 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 15163 invoked by uid 89); 21 Jun 2018 09:39:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-8.0 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_2,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 spammy=greater X-HELO: EUR01-HE1-obe.outbound.protection.outlook.com Received: from mail-he1eur01on0064.outbound.protection.outlook.com (HELO EUR01-HE1-obe.outbound.protection.outlook.com) (104.47.0.64) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 21 Jun 2018 09:38:59 +0000 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Alan.Hayward@arm.com; Received: from C02TF0U7HF1T.manchester.arm.com (217.140.96.140) by AM4PR0802MB2131.eurprd08.prod.outlook.com (2603:10a6:200:5c::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.863.16; Thu, 21 Jun 2018 09:38:52 +0000 From: Alan Hayward To: gdb-patches@sourceware.org Cc: nd@arm.com, Alan Hayward Subject: [PATCH v2 0/3] Support large registers in regcache transfer_regset Date: Thu, 21 Jun 2018 09:39:00 -0000 Message-Id: <20180621093802.79342-1-alan.hayward@arm.com> MIME-Version: 1.0 Content-Type: text/plain X-ClientProxiedBy: CWLP265CA0232.GBRP265.PROD.OUTLOOK.COM (2603:10a6:401:4f::28) To AM4PR0802MB2131.eurprd08.prod.outlook.com (2603:10a6:200:5c::22) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: bedd4746-4b3f-4ba2-46c4-08d5d75acca6 X-MS-TrafficTypeDiagnostic: AM4PR0802MB2131: NoDisclaimer: True X-Exchange-Antispam-Report-Test: UriScan:; X-MS-Exchange-SenderADCheck: 1 X-Forefront-PRVS: 07106EF9B9 Received-SPF: None (protection.outlook.com: arm.com does not designate permitted sender hosts) SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2018 09:38:52.1539 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bedd4746-4b3f-4ba2-46c4-08d5d75acca6 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR0802MB2131 X-IsSubscribed: yes X-SW-Source: 2018-06/txt/msg00512.txt.bz2 Support core file reading/writing where the register size is either greater or smaller than the space allocated to it in the core file. This will prevent assert failures on Aarch64 SVE. Whilst writing this patch I spotted potential issue for aarch64. The 32bit CPSR register has a 64bit slot in the core file. The existing transfer_regset did not ensure the extra 32bits were null padded. This version addresses all the review comments for V1, and splits up into smaller chunks. Patch 1 will enble patch 3 to use unsigned ints. Patch 2 is a cleanup of exisiting code. Patch 3 fixes the two issues. I did not update read_part/write_part to use unsigned ints as that would have required spiralled out to quite a few target file changes. Tested by generating cores on aarch64 and aarch64 sve, both via gdb and the kernel, then ensuring the cores load back on the both systems. Checked cores on x86 still look ok. Ran make check on x86 and aarch64. Alan Hayward (3): Use unsigned ints in regcache_map_entry All current uses of regcache_map_entry use static hard coded values. Avoid memcpys in regcache read_part/write_part for full registers. Use partial register read/writes in transfer_regset gdb/regcache.c | 189 ++++++++++++++++++++++++++++++++++++++++----------------- gdb/regcache.h | 26 ++++++-- 2 files changed, 154 insertions(+), 61 deletions(-) -- 2.15.2 (Apple Git-101.1)