* [PATCH 16/17] [PowerPC] Add support for EBB and PMU registers
2018-07-13 13:53 [PATCH 00/17] GDB support for more powerpc registers on linux Pedro Franco de Carvalho
@ 2018-07-13 13:53 ` Pedro Franco de Carvalho
2018-07-13 16:38 ` Ulrich Weigand
2018-07-13 13:53 ` [PATCH 05/17] [PowerPC] Add support for PPR and DSCR Pedro Franco de Carvalho
` (15 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 13:53 UTC (permalink / raw)
To: gdb-patches; +Cc: uweigand, edjunior
From: Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
This patch adds support for registers of the Event Based Branching and
Performance Monitoring Units for the powerpc linux native and core
file targets.
All three EBB registers are accessible. Only a subset of the PMU
registers can be accessed through ptrace. Because of this, the PMU
registers are enumerated indivitually in gdbarch_tdep, as opposed to
having a single "have_pmu" flag. This is intended to make it easier to
add additional PMU registers in the future, since checking a
"have_pmu" flag elsewhere in the code would no longer be correct.
It's unclear if it makes sense to save and restore these registers
across function calls, since some of them can be modified
asynchronously. They are also not tracked in record-replay mode.
Currently, the kernel can return ENODATA when ptrace is used to get
the EBB registers, unless a linux performance event that uses EBB is
open in the inferior. However, EBB registers are always saved and
restored by the kernel, but not the PMU registers, so the ENODATA
might have been meant for the PMU registers. For this reason GDB
handles ENODATA for both regsets.
Like for the previous patches, configure.srv is updated here to avoid
breaking the build at this patch.
gdb/ChangeLog:
YYYY-MM-DD Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* arch/ppc-linux-common.h (PPC_LINUX_SIZEOF_EBBREGSET)
(PPC_LINUX_SIZEOF_PMUREGSET): Declare.
* nat/ppc-linux.h (PPC_FEATURE2_EBB, NT_PPC_EBB, NT_PPC_PMU):
Define if not already defined.
* features/rs6000/power-ebb.xml: New file.
* features/rs6000/power-pmu.xml: New file.
* features/rs6000/powerpc-isa207-vsx32l.xml: Include ebb and pmu
features.
* features/rs6000/powerpc-isa207-vsx64l.xml: Likewise.
* features/rs6000/powerpc-isa207-htm-vsx32l.xml: Likewise.
* features/rs6000/powerpc-isa207-htm-vsx64l.xml: Likewise.
* features/rs6000/powerpc-isa207-vsx32l.c: Re-generate.
* features/rs6000/powerpc-isa207-vsx64l.c: Re-generate.
* features/rs6000/powerpc-isa207-htm-vsx32l.c: Re-generate.
* features/rs6000/powerpc-isa207-htm-vsx64l.c: Re-generate.
* regformats/rs6000/powerpc-isa207-vsx32l.dat: Re-generate.
* regformats/rs6000/powerpc-isa207-vsx64l.dat: Re-generate.
* regformats/rs6000/powerpc-isa207-htm-vsx32l.dat: Re-generate.
* regformats/rs6000/powerpc-isa207-htm-vsx64l.dat: Re-generate.
* ppc-linux-nat.c (fetch_register, fetch_ppc_registers): Call
fetch_regset with ebb and pmu regsets.
(store_register, store_ppc_registers): Call store_regset with ebb
and pmu regsets.
(ppc_linux_nat_target::read_description): Set isa207 field in the
features struct if ebb and pmu are avaiable.
* ppc-linux-tdep.c (ppc32_regmap_ebb, ppc32_regmap_pmu)
(ppc32_linux_ebbregset, ppc32_linux_pmuregset): New globals.
(ppc_linux_iterate_over_regset_sections): Call back with the ebb
and pmu regsets.
(ppc_linux_core_read_description): Add comment.
* ppc-linux-tdep.h (ppc32_linux_ebbregset, ppc32_linux_pmuregset):
Declare.
* ppc-tdep.h (struct gdbarch_tdep) <ppc_mmcr0_regnum>: New field.
<ppc_mmcr2_regnum, ppc_siar_regnum, ppc_sdar_regnum>: New fields.
<ppc_sier_regnum>: New field.
(enum): <PPC_BESCR_REGNUM, PPC_EBBHR_REGNUM, PPC_EBBRR_REGNUM>:
New enum values.
<PPC_MMCR0_REGNUM, PPC_MMCR2_REGNUM, PPC_SIAR_REGNUM>: New enum
values.
<PPC_SDAR_REGNUM, PPC_SIER_REGNUM>: New enum values.
(PPC_IS_EBB_REGNUM, PPC_IS_PMU_REGNUM): Define.
* rs6000-tdep.c (rs6000_gdbarch_init): Look for and validate the
ebb and pmu features.
gdb/gdbserver/ChangeLog:
YYYY-MM-DD Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* configure.srv (powerpc*-*-linux*): Add rs6000/power-ebb.xml and
rs6000/power-pmu.xml to srv_xmlfiles.
---
gdb/arch/ppc-linux-common.h | 2 +
gdb/features/rs6000/power-ebb.xml | 14 +
gdb/features/rs6000/power-pmu.xml | 16 ++
gdb/features/rs6000/powerpc-isa207-htm-vsx32l.c | 294 +++++++++++----------
gdb/features/rs6000/powerpc-isa207-htm-vsx32l.xml | 2 +
gdb/features/rs6000/powerpc-isa207-htm-vsx64l.c | 294 +++++++++++----------
gdb/features/rs6000/powerpc-isa207-htm-vsx64l.xml | 2 +
gdb/features/rs6000/powerpc-isa207-vsx32l.c | 12 +
gdb/features/rs6000/powerpc-isa207-vsx32l.xml | 2 +
gdb/features/rs6000/powerpc-isa207-vsx64l.c | 12 +
gdb/features/rs6000/powerpc-isa207-vsx64l.xml | 2 +
gdb/gdbserver/configure.srv | 2 +
gdb/nat/ppc-linux.h | 13 +
gdb/ppc-linux-nat.c | 64 ++++-
gdb/ppc-linux-tdep.c | 52 ++++
gdb/ppc-linux-tdep.h | 2 +
gdb/ppc-tdep.h | 59 +++--
.../rs6000/powerpc-isa207-htm-vsx32l.dat | 8 +
.../rs6000/powerpc-isa207-htm-vsx64l.dat | 8 +
gdb/regformats/rs6000/powerpc-isa207-vsx32l.dat | 8 +
gdb/regformats/rs6000/powerpc-isa207-vsx64l.dat | 8 +
gdb/rs6000-tdep.c | 65 ++++-
22 files changed, 640 insertions(+), 301 deletions(-)
create mode 100644 gdb/features/rs6000/power-ebb.xml
create mode 100644 gdb/features/rs6000/power-pmu.xml
diff --git a/gdb/arch/ppc-linux-common.h b/gdb/arch/ppc-linux-common.h
index 71e2d5d173..9ecb02bcf6 100644
--- a/gdb/arch/ppc-linux-common.h
+++ b/gdb/arch/ppc-linux-common.h
@@ -33,6 +33,8 @@ struct target_desc;
#define PPC_LINUX_SIZEOF_PPRREGSET 8
#define PPC_LINUX_SIZEOF_DSCRREGSET 8
#define PPC_LINUX_SIZEOF_TARREGSET 8
+#define PPC_LINUX_SIZEOF_EBBREGSET (3*8)
+#define PPC_LINUX_SIZEOF_PMUREGSET (5*8)
#define PPC_LINUX_SIZEOF_TM_SPRREGSET (3*8)
#define PPC32_LINUX_SIZEOF_CGPRREGSET (48*4)
#define PPC64_LINUX_SIZEOF_CGPRREGSET (48*8)
diff --git a/gdb/features/rs6000/power-ebb.xml b/gdb/features/rs6000/power-ebb.xml
new file mode 100644
index 0000000000..7bec21f916
--- /dev/null
+++ b/gdb/features/rs6000/power-ebb.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- POWER8 Event-based Branching Registers. -->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.power.ebb">
+ <reg name="bescr" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="ebbhr" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="ebbrr" bitsize="64" type="uint64" save-restore="no"/>
+</feature>
diff --git a/gdb/features/rs6000/power-pmu.xml b/gdb/features/rs6000/power-pmu.xml
new file mode 100644
index 0000000000..8f20c5df07
--- /dev/null
+++ b/gdb/features/rs6000/power-pmu.xml
@@ -0,0 +1,16 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- POWER8 Performance Monitor Registers. -->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.power.pmu">
+ <reg name="mmcr0" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="mmcr2" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="siar" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="sdar" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="sier" bitsize="64" type="uint64" save-restore="no"/>
+</feature>
diff --git a/gdb/features/rs6000/powerpc-isa207-htm-vsx32l.c b/gdb/features/rs6000/powerpc-isa207-htm-vsx32l.c
index 99c6a7feb7..4c3b977d82 100644
--- a/gdb/features/rs6000/powerpc-isa207-htm-vsx32l.c
+++ b/gdb/features/rs6000/powerpc-isa207-htm-vsx32l.c
@@ -199,6 +199,18 @@ initialize_tdesc_powerpc_isa207_htm_vsx32l (void)
feature = tdesc_create_feature (result, "org.gnu.gdb.power.tar");
tdesc_create_reg (feature, "tar", 141, 1, NULL, 64, "uint64");
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.ebb");
+ tdesc_create_reg (feature, "bescr", 142, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "ebbhr", 143, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "ebbrr", 144, 0, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.pmu");
+ tdesc_create_reg (feature, "mmcr0", 145, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "mmcr2", 146, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "siar", 147, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "sdar", 148, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "sier", 149, 0, NULL, 64, "uint64");
+
feature = tdesc_create_feature (result, "org.gnu.gdb.power.htm");
element_type = tdesc_named_type (feature, "ieee_single");
tdesc_create_vector (feature, "v4f", element_type, 4);
@@ -224,147 +236,147 @@ initialize_tdesc_powerpc_isa207_htm_vsx32l (void)
field_type = tdesc_named_type (feature, "v16i8");
tdesc_add_field (type_with_fields, "v16_int8", field_type);
- tdesc_create_reg (feature, "tfhar", 142, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "texasr", 143, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "tfiar", 144, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr0", 145, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr1", 146, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr2", 147, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr3", 148, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr4", 149, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr5", 150, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr6", 151, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr7", 152, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr8", 153, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr9", 154, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr10", 155, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr11", 156, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr12", 157, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr13", 158, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr14", 159, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr15", 160, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr16", 161, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr17", 162, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr18", 163, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr19", 164, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr20", 165, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr21", 166, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr22", 167, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr23", 168, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr24", 169, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr25", 170, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr26", 171, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr27", 172, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr28", 173, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr29", 174, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr30", 175, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cr31", 176, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "ccr", 177, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cxer", 178, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "clr", 179, 0, NULL, 32, "code_ptr");
- tdesc_create_reg (feature, "cctr", 180, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cf0", 181, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf1", 182, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf2", 183, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf3", 184, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf4", 185, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf5", 186, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf6", 187, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf7", 188, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf8", 189, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf9", 190, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf10", 191, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf11", 192, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf12", 193, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf13", 194, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf14", 195, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf15", 196, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf16", 197, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf17", 198, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf18", 199, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf19", 200, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf20", 201, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf21", 202, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf22", 203, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf23", 204, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf24", 205, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf25", 206, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf26", 207, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf27", 208, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf28", 209, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf29", 210, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf30", 211, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf31", 212, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cfpscr", 213, 0, "float", 64, "uint64");
- tdesc_create_reg (feature, "cvr0", 214, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr1", 215, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr2", 216, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr3", 217, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr4", 218, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr5", 219, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr6", 220, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr7", 221, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr8", 222, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr9", 223, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr10", 224, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr11", 225, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr12", 226, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr13", 227, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr14", 228, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr15", 229, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr16", 230, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr17", 231, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr18", 232, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr19", 233, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr20", 234, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr21", 235, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr22", 236, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr23", 237, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr24", 238, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr25", 239, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr26", 240, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr27", 241, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr28", 242, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr29", 243, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr30", 244, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr31", 245, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvscr", 246, 0, NULL, 32, "int");
- tdesc_create_reg (feature, "cvrsave", 247, 0, NULL, 32, "int");
- tdesc_create_reg (feature, "cvs0h", 248, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs1h", 249, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs2h", 250, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs3h", 251, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs4h", 252, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs5h", 253, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs6h", 254, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs7h", 255, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs8h", 256, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs9h", 257, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs10h", 258, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs11h", 259, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs12h", 260, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs13h", 261, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs14h", 262, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs15h", 263, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs16h", 264, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs17h", 265, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs18h", 266, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs19h", 267, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs20h", 268, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs21h", 269, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs22h", 270, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs23h", 271, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs24h", 272, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs25h", 273, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs26h", 274, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs27h", 275, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs28h", 276, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs29h", 277, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs30h", 278, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs31h", 279, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cppr", 280, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cdscr", 281, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "ctar", 282, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "tfhar", 150, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "texasr", 151, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "tfiar", 152, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr0", 153, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr1", 154, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr2", 155, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr3", 156, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr4", 157, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr5", 158, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr6", 159, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr7", 160, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr8", 161, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr9", 162, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr10", 163, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr11", 164, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr12", 165, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr13", 166, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr14", 167, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr15", 168, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr16", 169, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr17", 170, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr18", 171, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr19", 172, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr20", 173, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr21", 174, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr22", 175, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr23", 176, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr24", 177, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr25", 178, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr26", 179, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr27", 180, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr28", 181, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr29", 182, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr30", 183, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr31", 184, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "ccr", 185, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cxer", 186, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "clr", 187, 0, NULL, 32, "code_ptr");
+ tdesc_create_reg (feature, "cctr", 188, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cf0", 189, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf1", 190, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf2", 191, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf3", 192, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf4", 193, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf5", 194, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf6", 195, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf7", 196, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf8", 197, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf9", 198, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf10", 199, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf11", 200, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf12", 201, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf13", 202, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf14", 203, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf15", 204, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf16", 205, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf17", 206, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf18", 207, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf19", 208, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf20", 209, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf21", 210, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf22", 211, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf23", 212, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf24", 213, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf25", 214, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf26", 215, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf27", 216, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf28", 217, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf29", 218, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf30", 219, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf31", 220, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cfpscr", 221, 0, "float", 64, "uint64");
+ tdesc_create_reg (feature, "cvr0", 222, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr1", 223, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr2", 224, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr3", 225, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr4", 226, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr5", 227, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr6", 228, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr7", 229, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr8", 230, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr9", 231, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr10", 232, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr11", 233, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr12", 234, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr13", 235, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr14", 236, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr15", 237, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr16", 238, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr17", 239, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr18", 240, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr19", 241, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr20", 242, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr21", 243, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr22", 244, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr23", 245, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr24", 246, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr25", 247, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr26", 248, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr27", 249, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr28", 250, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr29", 251, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr30", 252, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr31", 253, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvscr", 254, 0, NULL, 32, "int");
+ tdesc_create_reg (feature, "cvrsave", 255, 0, NULL, 32, "int");
+ tdesc_create_reg (feature, "cvs0h", 256, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs1h", 257, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs2h", 258, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs3h", 259, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs4h", 260, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs5h", 261, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs6h", 262, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs7h", 263, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs8h", 264, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs9h", 265, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs10h", 266, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs11h", 267, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs12h", 268, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs13h", 269, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs14h", 270, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs15h", 271, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs16h", 272, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs17h", 273, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs18h", 274, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs19h", 275, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs20h", 276, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs21h", 277, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs22h", 278, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs23h", 279, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs24h", 280, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs25h", 281, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs26h", 282, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs27h", 283, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs28h", 284, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs29h", 285, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs30h", 286, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs31h", 287, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cppr", 288, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cdscr", 289, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "ctar", 290, 0, NULL, 64, "uint64");
tdesc_powerpc_isa207_htm_vsx32l = result;
}
diff --git a/gdb/features/rs6000/powerpc-isa207-htm-vsx32l.xml b/gdb/features/rs6000/powerpc-isa207-htm-vsx32l.xml
index 84192b0c38..778372d305 100644
--- a/gdb/features/rs6000/powerpc-isa207-htm-vsx32l.xml
+++ b/gdb/features/rs6000/powerpc-isa207-htm-vsx32l.xml
@@ -16,5 +16,7 @@
<xi:include href="power-ppr.xml"/>
<xi:include href="power-dscr.xml"/>
<xi:include href="power-tar.xml"/>
+ <xi:include href="power-ebb.xml"/>
+ <xi:include href="power-pmu.xml"/>
<xi:include href="power-htm.xml"/>
</target>
diff --git a/gdb/features/rs6000/powerpc-isa207-htm-vsx64l.c b/gdb/features/rs6000/powerpc-isa207-htm-vsx64l.c
index 2647a077dd..ef0cdece20 100644
--- a/gdb/features/rs6000/powerpc-isa207-htm-vsx64l.c
+++ b/gdb/features/rs6000/powerpc-isa207-htm-vsx64l.c
@@ -199,6 +199,18 @@ initialize_tdesc_powerpc_isa207_htm_vsx64l (void)
feature = tdesc_create_feature (result, "org.gnu.gdb.power.tar");
tdesc_create_reg (feature, "tar", 141, 1, NULL, 64, "uint64");
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.ebb");
+ tdesc_create_reg (feature, "bescr", 142, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "ebbhr", 143, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "ebbrr", 144, 0, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.pmu");
+ tdesc_create_reg (feature, "mmcr0", 145, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "mmcr2", 146, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "siar", 147, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "sdar", 148, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "sier", 149, 0, NULL, 64, "uint64");
+
feature = tdesc_create_feature (result, "org.gnu.gdb.power.htm");
element_type = tdesc_named_type (feature, "ieee_single");
tdesc_create_vector (feature, "v4f", element_type, 4);
@@ -224,147 +236,147 @@ initialize_tdesc_powerpc_isa207_htm_vsx64l (void)
field_type = tdesc_named_type (feature, "v16i8");
tdesc_add_field (type_with_fields, "v16_int8", field_type);
- tdesc_create_reg (feature, "tfhar", 142, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "texasr", 143, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "tfiar", 144, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr0", 145, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr1", 146, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr2", 147, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr3", 148, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr4", 149, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr5", 150, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr6", 151, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr7", 152, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr8", 153, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr9", 154, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr10", 155, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr11", 156, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr12", 157, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr13", 158, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr14", 159, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr15", 160, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr16", 161, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr17", 162, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr18", 163, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr19", 164, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr20", 165, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr21", 166, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr22", 167, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr23", 168, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr24", 169, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr25", 170, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr26", 171, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr27", 172, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr28", 173, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr29", 174, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr30", 175, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cr31", 176, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "ccr", 177, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "cxer", 178, 0, NULL, 32, "uint32");
- tdesc_create_reg (feature, "clr", 179, 0, NULL, 64, "code_ptr");
- tdesc_create_reg (feature, "cctr", 180, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cf0", 181, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf1", 182, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf2", 183, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf3", 184, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf4", 185, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf5", 186, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf6", 187, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf7", 188, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf8", 189, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf9", 190, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf10", 191, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf11", 192, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf12", 193, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf13", 194, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf14", 195, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf15", 196, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf16", 197, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf17", 198, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf18", 199, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf19", 200, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf20", 201, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf21", 202, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf22", 203, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf23", 204, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf24", 205, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf25", 206, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf26", 207, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf27", 208, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf28", 209, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf29", 210, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf30", 211, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cf31", 212, 0, NULL, 64, "ieee_double");
- tdesc_create_reg (feature, "cfpscr", 213, 0, "float", 64, "uint64");
- tdesc_create_reg (feature, "cvr0", 214, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr1", 215, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr2", 216, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr3", 217, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr4", 218, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr5", 219, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr6", 220, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr7", 221, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr8", 222, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr9", 223, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr10", 224, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr11", 225, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr12", 226, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr13", 227, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr14", 228, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr15", 229, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr16", 230, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr17", 231, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr18", 232, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr19", 233, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr20", 234, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr21", 235, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr22", 236, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr23", 237, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr24", 238, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr25", 239, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr26", 240, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr27", 241, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr28", 242, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr29", 243, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr30", 244, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvr31", 245, 0, NULL, 128, "vec128");
- tdesc_create_reg (feature, "cvscr", 246, 0, NULL, 32, "int");
- tdesc_create_reg (feature, "cvrsave", 247, 0, NULL, 32, "int");
- tdesc_create_reg (feature, "cvs0h", 248, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs1h", 249, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs2h", 250, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs3h", 251, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs4h", 252, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs5h", 253, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs6h", 254, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs7h", 255, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs8h", 256, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs9h", 257, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs10h", 258, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs11h", 259, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs12h", 260, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs13h", 261, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs14h", 262, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs15h", 263, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs16h", 264, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs17h", 265, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs18h", 266, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs19h", 267, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs20h", 268, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs21h", 269, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs22h", 270, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs23h", 271, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs24h", 272, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs25h", 273, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs26h", 274, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs27h", 275, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs28h", 276, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs29h", 277, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs30h", 278, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cvs31h", 279, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cppr", 280, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "cdscr", 281, 0, NULL, 64, "uint64");
- tdesc_create_reg (feature, "ctar", 282, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "tfhar", 150, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "texasr", 151, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "tfiar", 152, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr0", 153, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr1", 154, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr2", 155, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr3", 156, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr4", 157, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr5", 158, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr6", 159, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr7", 160, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr8", 161, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr9", 162, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr10", 163, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr11", 164, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr12", 165, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr13", 166, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr14", 167, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr15", 168, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr16", 169, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr17", 170, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr18", 171, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr19", 172, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr20", 173, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr21", 174, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr22", 175, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr23", 176, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr24", 177, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr25", 178, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr26", 179, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr27", 180, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr28", 181, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr29", 182, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr30", 183, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr31", 184, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "ccr", 185, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cxer", 186, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "clr", 187, 0, NULL, 64, "code_ptr");
+ tdesc_create_reg (feature, "cctr", 188, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cf0", 189, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf1", 190, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf2", 191, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf3", 192, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf4", 193, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf5", 194, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf6", 195, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf7", 196, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf8", 197, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf9", 198, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf10", 199, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf11", 200, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf12", 201, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf13", 202, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf14", 203, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf15", 204, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf16", 205, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf17", 206, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf18", 207, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf19", 208, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf20", 209, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf21", 210, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf22", 211, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf23", 212, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf24", 213, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf25", 214, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf26", 215, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf27", 216, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf28", 217, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf29", 218, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf30", 219, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf31", 220, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cfpscr", 221, 0, "float", 64, "uint64");
+ tdesc_create_reg (feature, "cvr0", 222, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr1", 223, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr2", 224, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr3", 225, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr4", 226, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr5", 227, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr6", 228, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr7", 229, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr8", 230, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr9", 231, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr10", 232, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr11", 233, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr12", 234, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr13", 235, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr14", 236, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr15", 237, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr16", 238, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr17", 239, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr18", 240, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr19", 241, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr20", 242, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr21", 243, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr22", 244, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr23", 245, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr24", 246, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr25", 247, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr26", 248, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr27", 249, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr28", 250, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr29", 251, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr30", 252, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr31", 253, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvscr", 254, 0, NULL, 32, "int");
+ tdesc_create_reg (feature, "cvrsave", 255, 0, NULL, 32, "int");
+ tdesc_create_reg (feature, "cvs0h", 256, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs1h", 257, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs2h", 258, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs3h", 259, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs4h", 260, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs5h", 261, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs6h", 262, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs7h", 263, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs8h", 264, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs9h", 265, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs10h", 266, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs11h", 267, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs12h", 268, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs13h", 269, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs14h", 270, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs15h", 271, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs16h", 272, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs17h", 273, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs18h", 274, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs19h", 275, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs20h", 276, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs21h", 277, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs22h", 278, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs23h", 279, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs24h", 280, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs25h", 281, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs26h", 282, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs27h", 283, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs28h", 284, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs29h", 285, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs30h", 286, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs31h", 287, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cppr", 288, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cdscr", 289, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "ctar", 290, 0, NULL, 64, "uint64");
tdesc_powerpc_isa207_htm_vsx64l = result;
}
diff --git a/gdb/features/rs6000/powerpc-isa207-htm-vsx64l.xml b/gdb/features/rs6000/powerpc-isa207-htm-vsx64l.xml
index e1649d0d9e..2ee2675abd 100644
--- a/gdb/features/rs6000/powerpc-isa207-htm-vsx64l.xml
+++ b/gdb/features/rs6000/powerpc-isa207-htm-vsx64l.xml
@@ -16,5 +16,7 @@
<xi:include href="power-ppr.xml"/>
<xi:include href="power-dscr.xml"/>
<xi:include href="power-tar.xml"/>
+ <xi:include href="power-ebb.xml"/>
+ <xi:include href="power-pmu.xml"/>
<xi:include href="power64-htm.xml"/>
</target>
diff --git a/gdb/features/rs6000/powerpc-isa207-vsx32l.c b/gdb/features/rs6000/powerpc-isa207-vsx32l.c
index 73c7a01077..e9853829e6 100644
--- a/gdb/features/rs6000/powerpc-isa207-vsx32l.c
+++ b/gdb/features/rs6000/powerpc-isa207-vsx32l.c
@@ -199,5 +199,17 @@ initialize_tdesc_powerpc_isa207_vsx32l (void)
feature = tdesc_create_feature (result, "org.gnu.gdb.power.tar");
tdesc_create_reg (feature, "tar", 141, 1, NULL, 64, "uint64");
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.ebb");
+ tdesc_create_reg (feature, "bescr", 142, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "ebbhr", 143, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "ebbrr", 144, 0, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.pmu");
+ tdesc_create_reg (feature, "mmcr0", 145, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "mmcr2", 146, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "siar", 147, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "sdar", 148, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "sier", 149, 0, NULL, 64, "uint64");
+
tdesc_powerpc_isa207_vsx32l = result;
}
diff --git a/gdb/features/rs6000/powerpc-isa207-vsx32l.xml b/gdb/features/rs6000/powerpc-isa207-vsx32l.xml
index 599e6a24a2..a3a2454929 100644
--- a/gdb/features/rs6000/powerpc-isa207-vsx32l.xml
+++ b/gdb/features/rs6000/powerpc-isa207-vsx32l.xml
@@ -16,4 +16,6 @@
<xi:include href="power-ppr.xml"/>
<xi:include href="power-dscr.xml"/>
<xi:include href="power-tar.xml"/>
+ <xi:include href="power-ebb.xml"/>
+ <xi:include href="power-pmu.xml"/>
</target>
diff --git a/gdb/features/rs6000/powerpc-isa207-vsx64l.c b/gdb/features/rs6000/powerpc-isa207-vsx64l.c
index 9c735522d2..0e94d9c243 100644
--- a/gdb/features/rs6000/powerpc-isa207-vsx64l.c
+++ b/gdb/features/rs6000/powerpc-isa207-vsx64l.c
@@ -199,5 +199,17 @@ initialize_tdesc_powerpc_isa207_vsx64l (void)
feature = tdesc_create_feature (result, "org.gnu.gdb.power.tar");
tdesc_create_reg (feature, "tar", 141, 1, NULL, 64, "uint64");
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.ebb");
+ tdesc_create_reg (feature, "bescr", 142, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "ebbhr", 143, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "ebbrr", 144, 0, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.pmu");
+ tdesc_create_reg (feature, "mmcr0", 145, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "mmcr2", 146, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "siar", 147, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "sdar", 148, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "sier", 149, 0, NULL, 64, "uint64");
+
tdesc_powerpc_isa207_vsx64l = result;
}
diff --git a/gdb/features/rs6000/powerpc-isa207-vsx64l.xml b/gdb/features/rs6000/powerpc-isa207-vsx64l.xml
index 42a23cc001..d91ce5e9cf 100644
--- a/gdb/features/rs6000/powerpc-isa207-vsx64l.xml
+++ b/gdb/features/rs6000/powerpc-isa207-vsx64l.xml
@@ -16,4 +16,6 @@
<xi:include href="power-ppr.xml"/>
<xi:include href="power-dscr.xml"/>
<xi:include href="power-tar.xml"/>
+ <xi:include href="power-ebb.xml"/>
+ <xi:include href="power-pmu.xml"/>
</target>
diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
index 6559ab1643..570fc0762f 100644
--- a/gdb/gdbserver/configure.srv
+++ b/gdb/gdbserver/configure.srv
@@ -252,6 +252,8 @@ case "${target}" in
srv_xmlfiles="${srv_xmlfiles} rs6000/power-dscr.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-ppr.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-tar.xml"
+ srv_xmlfiles="${srv_xmlfiles} rs6000/power-ebb.xml"
+ srv_xmlfiles="${srv_xmlfiles} rs6000/power-pmu.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-htm.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-e500l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-spe.xml"
diff --git a/gdb/nat/ppc-linux.h b/gdb/nat/ppc-linux.h
index 44b76e2891..65c60cb158 100644
--- a/gdb/nat/ppc-linux.h
+++ b/gdb/nat/ppc-linux.h
@@ -60,6 +60,9 @@
#ifndef PPC_FEATURE2_TAR
#define PPC_FEATURE2_TAR 0x04000000
#endif
+#ifndef PPC_FEATURE2_EBB
+#define PPC_FEATURE2_EBB 0x10000000
+#endif
#ifndef PPC_FEATURE2_HTM
#define PPC_FEATURE2_HTM 0x40000000
#endif
@@ -109,6 +112,16 @@
#define NT_PPC_DSCR 0x105
#endif
+/* Event Based Branch Registers. */
+#ifndef NT_PPC_EBB
+#define NT_PPC_EBB 0x106
+#endif
+
+/* Performance Monitor Registers. */
+#ifndef NT_PPC_PMU
+#define NT_PPC_PMU 0x107
+#endif
+
/* TM checkpointed GPR Registers. */
#ifndef NT_PPC_TM_CGPR
#define NT_PPC_TM_CGPR 0x108
diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c
index b084934b22..32ace7219d 100644
--- a/gdb/ppc-linux-nat.c
+++ b/gdb/ppc-linux-nat.c
@@ -667,6 +667,24 @@ fetch_register (struct regcache *regcache, int tid, int regno)
&ppc32_linux_tarregset);
return;
}
+ else if (PPC_IS_EBB_REGNUM (regno))
+ {
+ gdb_assert (tdep->have_ebb);
+
+ fetch_regset (regcache, tid, NT_PPC_EBB,
+ PPC_LINUX_SIZEOF_EBBREGSET,
+ &ppc32_linux_ebbregset);
+ return;
+ }
+ else if (PPC_IS_PMU_REGNUM (regno))
+ {
+ gdb_assert (tdep->ppc_mmcr0_regnum != -1);
+
+ fetch_regset (regcache, tid, NT_PPC_PMU,
+ PPC_LINUX_SIZEOF_PMUREGSET,
+ &ppc32_linux_pmuregset);
+ return;
+ }
else if (PPC_IS_TMSPR_REGNUM (regno))
{
gdb_assert (tdep->have_htm);
@@ -953,6 +971,15 @@ fetch_ppc_registers (struct regcache *regcache, int tid)
PPC_LINUX_SIZEOF_TARREGSET,
&ppc32_linux_tarregset);
+ if (tdep->have_ebb)
+ fetch_regset (regcache, tid, NT_PPC_EBB,
+ PPC_LINUX_SIZEOF_EBBREGSET,
+ &ppc32_linux_ebbregset);
+ if (tdep->ppc_mmcr0_regnum != -1)
+ fetch_regset (regcache, tid, NT_PPC_PMU,
+ PPC_LINUX_SIZEOF_PMUREGSET,
+ &ppc32_linux_pmuregset);
+
if (tdep->have_htm)
{
fetch_regset (regcache, tid, NT_PPC_TM_SPR,
@@ -1196,6 +1223,24 @@ store_register (const struct regcache *regcache, int tid, int regno)
&ppc32_linux_tarregset);
return;
}
+ else if (PPC_IS_EBB_REGNUM (regno))
+ {
+ gdb_assert (tdep->have_ebb);
+
+ store_regset (regcache, tid, regno, NT_PPC_EBB,
+ PPC_LINUX_SIZEOF_EBBREGSET,
+ &ppc32_linux_ebbregset);
+ return;
+ }
+ else if (PPC_IS_PMU_REGNUM (regno))
+ {
+ gdb_assert (tdep->ppc_mmcr0_regnum != -1);
+
+ store_regset (regcache, tid, regno, NT_PPC_PMU,
+ PPC_LINUX_SIZEOF_PMUREGSET,
+ &ppc32_linux_pmuregset);
+ return;
+ }
else if (PPC_IS_TMSPR_REGNUM (regno))
{
gdb_assert (tdep->have_htm);
@@ -1544,6 +1589,19 @@ store_ppc_registers (const struct regcache *regcache, int tid)
PPC_LINUX_SIZEOF_TARREGSET,
&ppc32_linux_tarregset);
+ /* EBB/PMU registers can be unavailable. */
+ if (tdep->have_ebb
+ && ppc_linux_regset_available_p (regcache, &ppc32_linux_ebbregset))
+ store_regset (regcache, tid, -1, NT_PPC_EBB,
+ PPC_LINUX_SIZEOF_EBBREGSET,
+ &ppc32_linux_ebbregset);
+
+ if (tdep->ppc_mmcr0_regnum != -1
+ && ppc_linux_regset_available_p (regcache, &ppc32_linux_pmuregset))
+ store_regset (regcache, tid, -1, NT_PPC_PMU,
+ PPC_LINUX_SIZEOF_PMUREGSET,
+ &ppc32_linux_pmuregset);
+
if (tdep->have_htm)
{
store_regset (regcache, tid, -1, NT_PPC_TM_SPR,
@@ -2734,7 +2792,11 @@ ppc_linux_nat_target::read_description ()
features.ppr_dscr = true;
if ((hwcap2 & PPC_FEATURE2_ARCH_2_07)
&& (hwcap2 & PPC_FEATURE2_TAR)
- && check_regset (tid, NT_PPC_TAR, PPC_LINUX_SIZEOF_TARREGSET))
+ && (hwcap2 & PPC_FEATURE2_EBB)
+ && check_regset (tid, NT_PPC_TAR, PPC_LINUX_SIZEOF_TARREGSET)
+ && check_regset (tid, NT_PPC_EBB, PPC_LINUX_SIZEOF_EBBREGSET)
+ && check_regset (tid, NT_PPC_PMU, PPC_LINUX_SIZEOF_PMUREGSET))
+
{
features.isa207 = true;
if ((hwcap2 & PPC_FEATURE2_HTM)
diff --git a/gdb/ppc-linux-tdep.c b/gdb/ppc-linux-tdep.c
index 74e4eec413..e9e710ac6b 100644
--- a/gdb/ppc-linux-tdep.c
+++ b/gdb/ppc-linux-tdep.c
@@ -541,6 +541,24 @@ static const struct regcache_map_entry ppc32_regmap_tar[] =
{ 0 }
};
+static const struct regcache_map_entry ppc32_regmap_ebb[] =
+ {
+ { 1, PPC_EBBRR_REGNUM, 8 },
+ { 1, PPC_EBBHR_REGNUM, 8 },
+ { 1, PPC_BESCR_REGNUM, 8 },
+ { 0 }
+ };
+
+static const struct regcache_map_entry ppc32_regmap_pmu[] =
+ {
+ { 1, PPC_SIAR_REGNUM, 8 },
+ { 1, PPC_SDAR_REGNUM, 8 },
+ { 1, PPC_SIER_REGNUM, 8 },
+ { 1, PPC_MMCR2_REGNUM, 8 },
+ { 1, PPC_MMCR0_REGNUM, 8 },
+ { 0 }
+ };
+
static const struct regcache_map_entry ppc32_regmap_tm_spr[] =
{
{ 1, PPC_TFHAR_REGNUM, 8 },
@@ -731,6 +749,18 @@ const struct regset ppc32_linux_tarregset = {
regcache_collect_regset
};
+const struct regset ppc32_linux_ebbregset = {
+ ppc32_regmap_ebb,
+ regcache_supply_regset,
+ regcache_collect_regset
+};
+
+const struct regset ppc32_linux_pmuregset = {
+ ppc32_regmap_pmu,
+ regcache_supply_regset,
+ regcache_collect_regset
+};
+
const struct regset ppc32_linux_tm_sprregset = {
ppc32_regmap_tm_spr,
regcache_supply_regset,
@@ -892,6 +922,23 @@ ppc_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
cb (".reg-ppc-tar", PPC_LINUX_SIZEOF_TARREGSET,
&ppc32_linux_tarregset, "Target Address Register", cb_data);
+ /* EBB/PMU registers are unavailable when ptrace returns ENODATA.
+ Check availability when generating a core file (regcache !=
+ NULL). */
+ if (tdep->have_ebb)
+ if (regcache == NULL
+ || REG_VALID == regcache->get_register_status (PPC_BESCR_REGNUM))
+ cb (".reg-ppc-ebb", PPC_LINUX_SIZEOF_EBBREGSET,
+ &ppc32_linux_ebbregset, "Event-based Branching Registers",
+ cb_data);
+
+ if (tdep->ppc_mmcr0_regnum != -1)
+ if (regcache == NULL
+ || REG_VALID == regcache->get_register_status (PPC_MMCR0_REGNUM))
+ cb (".reg-ppc-pmu", PPC_LINUX_SIZEOF_PMUREGSET,
+ &ppc32_linux_pmuregset, "Performance Monitor Registers",
+ cb_data);
+
if (tdep->have_htm)
{
cb (".reg-ppc-tm-spr", PPC_LINUX_SIZEOF_TM_SPRREGSET,
@@ -1407,6 +1454,11 @@ ppc_linux_core_read_description (struct gdbarch *gdbarch,
if (ppr && dscr)
{
features.ppr_dscr = true;
+
+ /* We don't require the EBB or PMU note sections to be present
+ in the core file to select isa207 because these registers
+ could have been unavailable when the core file was created.
+ They will be in the tdep but will show as unavailable. */
if (tar)
{
features.isa207 = true;
diff --git a/gdb/ppc-linux-tdep.h b/gdb/ppc-linux-tdep.h
index a68eca6d42..4c19d4a39a 100644
--- a/gdb/ppc-linux-tdep.h
+++ b/gdb/ppc-linux-tdep.h
@@ -59,6 +59,8 @@ int ppc_linux_trap_reg_p (struct gdbarch *gdbarch);
extern const struct regset ppc32_linux_pprregset;
extern const struct regset ppc32_linux_dscrregset;
extern const struct regset ppc32_linux_tarregset;
+extern const struct regset ppc32_linux_ebbregset;
+extern const struct regset ppc32_linux_pmuregset;
extern const struct regset ppc32_linux_tm_sprregset;
extern const struct regset ppc32_linux_cfprregset;
extern const struct regset ppc32_linux_cvsxregset;
diff --git a/gdb/ppc-tdep.h b/gdb/ppc-tdep.h
index ddb1c5e84b..f1ba4b6246 100644
--- a/gdb/ppc-tdep.h
+++ b/gdb/ppc-tdep.h
@@ -262,6 +262,15 @@ struct gdbarch_tdep
/* Target Address Register. */
int ppc_tar_regnum;
+ int have_ebb;
+
+ /* PMU registers. */
+ int ppc_mmcr0_regnum;
+ int ppc_mmcr2_regnum;
+ int ppc_siar_regnum;
+ int ppc_sdar_regnum;
+ int ppc_sier_regnum;
+
int have_htm;
/* HTM pseudo registers. */
@@ -326,36 +335,52 @@ enum {
PPC_PPR_REGNUM = 172,
PPC_DSCR_REGNUM = 173,
PPC_TAR_REGNUM = 174,
+ /* EBB registers. */
+ PPC_BESCR_REGNUM = 175,
+ PPC_EBBHR_REGNUM = 176,
+ PPC_EBBRR_REGNUM = 177,
+ /* PMU registers. */
+ PPC_MMCR0_REGNUM = 178,
+ PPC_MMCR2_REGNUM = 179,
+ PPC_SIAR_REGNUM = 180,
+ PPC_SDAR_REGNUM = 181,
+ PPC_SIER_REGNUM = 182,
/* Hardware transactional memory registers. */
- PPC_TFHAR_REGNUM = 175,
- PPC_TEXASR_REGNUM = 176,
- PPC_TFIAR_REGNUM = 177,
+ PPC_TFHAR_REGNUM = 183,
+ PPC_TEXASR_REGNUM = 184,
+ PPC_TFIAR_REGNUM = 185,
- PPC_CR0_REGNUM = 178,
- PPC_CCR_REGNUM = 210,
- PPC_CXER_REGNUM = 211,
- PPC_CLR_REGNUM = 212,
- PPC_CCTR_REGNUM = 213,
+ PPC_CR0_REGNUM = 186,
+ PPC_CCR_REGNUM = 218,
+ PPC_CXER_REGNUM = 219,
+ PPC_CLR_REGNUM = 220,
+ PPC_CCTR_REGNUM = 221,
- PPC_CF0_REGNUM = 214,
- PPC_CFPSCR_REGNUM = 246,
+ PPC_CF0_REGNUM = 222,
+ PPC_CFPSCR_REGNUM = 254,
- PPC_CVR0_REGNUM = 247,
- PPC_CVSCR_REGNUM = 279,
- PPC_CVRSAVE_REGNUM = 280,
+ PPC_CVR0_REGNUM = 255,
+ PPC_CVSCR_REGNUM = 287,
+ PPC_CVRSAVE_REGNUM = 288,
- PPC_CVS0H_REGNUM = 281,
+ PPC_CVS0H_REGNUM = 289,
- PPC_CPPR_REGNUM = 313,
- PPC_CDSCR_REGNUM = 314,
- PPC_CTAR_REGNUM = 315,
+ PPC_CPPR_REGNUM = 321,
+ PPC_CDSCR_REGNUM = 322,
+ PPC_CTAR_REGNUM = 323,
PPC_NUM_REGS
};
/* Big enough to hold the size of the largest register in bytes. */
#define PPC_MAX_REGISTER_SIZE 64
+#define PPC_IS_EBB_REGNUM(i) \
+ ((i) >= PPC_BESCR_REGNUM && (i) <= PPC_EBBRR_REGNUM)
+
+#define PPC_IS_PMU_REGNUM(i) \
+ ((i) >= PPC_MMCR0_REGNUM && (i) <= PPC_SIER_REGNUM)
+
#define PPC_IS_TMSPR_REGNUM(i) \
((i) >= PPC_TFHAR_REGNUM && (i) <= PPC_TFIAR_REGNUM)
diff --git a/gdb/regformats/rs6000/powerpc-isa207-htm-vsx32l.dat b/gdb/regformats/rs6000/powerpc-isa207-htm-vsx32l.dat
index 6f5bbad28f..c19416db86 100644
--- a/gdb/regformats/rs6000/powerpc-isa207-htm-vsx32l.dat
+++ b/gdb/regformats/rs6000/powerpc-isa207-htm-vsx32l.dat
@@ -145,6 +145,14 @@ expedite:r1,pc
64:ppr
64:dscr
64:tar
+64:bescr
+64:ebbhr
+64:ebbrr
+64:mmcr0
+64:mmcr2
+64:siar
+64:sdar
+64:sier
64:tfhar
64:texasr
64:tfiar
diff --git a/gdb/regformats/rs6000/powerpc-isa207-htm-vsx64l.dat b/gdb/regformats/rs6000/powerpc-isa207-htm-vsx64l.dat
index 2f3d21c4c6..38359959fd 100644
--- a/gdb/regformats/rs6000/powerpc-isa207-htm-vsx64l.dat
+++ b/gdb/regformats/rs6000/powerpc-isa207-htm-vsx64l.dat
@@ -145,6 +145,14 @@ expedite:r1,pc
64:ppr
64:dscr
64:tar
+64:bescr
+64:ebbhr
+64:ebbrr
+64:mmcr0
+64:mmcr2
+64:siar
+64:sdar
+64:sier
64:tfhar
64:texasr
64:tfiar
diff --git a/gdb/regformats/rs6000/powerpc-isa207-vsx32l.dat b/gdb/regformats/rs6000/powerpc-isa207-vsx32l.dat
index 2b6e0a9c8d..0718d72d93 100644
--- a/gdb/regformats/rs6000/powerpc-isa207-vsx32l.dat
+++ b/gdb/regformats/rs6000/powerpc-isa207-vsx32l.dat
@@ -145,3 +145,11 @@ expedite:r1,pc
64:ppr
64:dscr
64:tar
+64:bescr
+64:ebbhr
+64:ebbrr
+64:mmcr0
+64:mmcr2
+64:siar
+64:sdar
+64:sier
diff --git a/gdb/regformats/rs6000/powerpc-isa207-vsx64l.dat b/gdb/regformats/rs6000/powerpc-isa207-vsx64l.dat
index 095bd7f2d3..510c6c87da 100644
--- a/gdb/regformats/rs6000/powerpc-isa207-vsx64l.dat
+++ b/gdb/regformats/rs6000/powerpc-isa207-vsx64l.dat
@@ -145,3 +145,11 @@ expedite:r1,pc
64:ppr
64:dscr
64:tar
+64:bescr
+64:ebbhr
+64:ebbrr
+64:mmcr0
+64:mmcr2
+64:siar
+64:sdar
+64:sier
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index 6687e20d2b..0c19a4c557 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -5954,7 +5954,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
enum powerpc_elf_abi elf_abi = POWERPC_ELF_AUTO;
int have_fpu = 0, have_spe = 0, have_mq = 0, have_altivec = 0;
int have_dfp = 0, have_vsx = 0, have_ppr = 0, have_dscr = 0;
- int have_tar = 0, have_htm = 0;
+ int have_tar = 0, have_ebb = 0, have_pmu = 0, have_htm = 0;
int tdesc_wordsize = -1;
const struct target_desc *tdesc = info.target_desc;
struct tdesc_arch_data *tdesc_data = NULL;
@@ -6295,6 +6295,54 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
else
have_tar = 0;
+ /* Event-based Branching Registers. */
+ feature = tdesc_find_feature (tdesc,
+ "org.gnu.gdb.power.ebb");
+ if (feature != NULL)
+ {
+ static const char *const ebb_regs[] = {
+ "bescr", "ebbhr", "ebbrr"
+ };
+
+ valid_p = 1;
+ for (i = 0; i < ARRAY_SIZE (ebb_regs); i++)
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ PPC_BESCR_REGNUM + i,
+ ebb_regs[i]);
+ if (!valid_p)
+ {
+ tdesc_data_cleanup (tdesc_data);
+ return NULL;
+ }
+ have_ebb = 1;
+ }
+ else
+ have_ebb = 0;
+
+ /* Performance Monitor Registers. */
+ feature = tdesc_find_feature (tdesc,
+ "org.gnu.gdb.power.pmu");
+ if (feature != NULL)
+ {
+ static const char *const pmu_regs[] = {
+ "mmcr0", "mmcr2", "siar", "sdar", "sier"
+ };
+
+ valid_p = 1;
+ for (i = 0; i < ARRAY_SIZE (pmu_regs); i++)
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ PPC_MMCR0_REGNUM + i,
+ pmu_regs[i]);
+ if (!valid_p)
+ {
+ tdesc_data_cleanup (tdesc_data);
+ return NULL;
+ }
+ have_pmu = 1;
+ }
+ else
+ have_pmu = 0;
+
/* Hardware Transactional Memory Registers. */
feature = tdesc_find_feature (tdesc,
"org.gnu.gdb.power.htm");
@@ -6582,6 +6630,21 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
tdep->ppc_ppr_regnum = have_ppr ? PPC_PPR_REGNUM : -1;
tdep->ppc_dscr_regnum = have_dscr ? PPC_DSCR_REGNUM : -1;
tdep->ppc_tar_regnum = have_tar ? PPC_TAR_REGNUM : -1;
+ tdep->have_ebb = have_ebb;
+
+ /* If additional pmu registers are added, care must be taken when
+ setting new fields in the tdep below, to maintain compatibility
+ with features that only provide some of the registers. Currently
+ gdb access to the pmu registers is only supported in linux, and
+ linux only provides a subset of the pmu registers defined in the
+ architecture. */
+
+ tdep->ppc_mmcr0_regnum = have_pmu ? PPC_MMCR0_REGNUM : -1;
+ tdep->ppc_mmcr2_regnum = have_pmu ? PPC_MMCR2_REGNUM : -1;
+ tdep->ppc_siar_regnum = have_pmu ? PPC_SIAR_REGNUM : -1;
+ tdep->ppc_sdar_regnum = have_pmu ? PPC_SDAR_REGNUM : -1;
+ tdep->ppc_sier_regnum = have_pmu ? PPC_SIER_REGNUM : -1;
+
tdep->have_htm = have_htm;
set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
--
2.13.6
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 16/17] [PowerPC] Add support for EBB and PMU registers
2018-07-13 13:53 ` [PATCH 16/17] [PowerPC] Add support for EBB and PMU registers Pedro Franco de Carvalho
@ 2018-07-13 16:38 ` Ulrich Weigand
2018-07-13 18:23 ` Pedro Franco de Carvalho
0 siblings, 1 reply; 38+ messages in thread
From: Ulrich Weigand @ 2018-07-13 16:38 UTC (permalink / raw)
To: Pedro Franco de Carvalho; +Cc: gdb-patches, edjunior
Pedro Franco de Carvalho wrote:
> All three EBB registers are accessible. Only a subset of the PMU
> registers can be accessed through ptrace. Because of this, the PMU
> registers are enumerated indivitually in gdbarch_tdep, as opposed to
> having a single "have_pmu" flag. This is intended to make it easier to
> add additional PMU registers in the future, since checking a
> "have_pmu" flag elsewhere in the code would no longer be correct.
>
> It's unclear if it makes sense to save and restore these registers
> across function calls, since some of them can be modified
> asynchronously. They are also not tracked in record-replay mode.
Agreed, they should not be saved and restored.
> Currently, the kernel can return ENODATA when ptrace is used to get
> the EBB registers, unless a linux performance event that uses EBB is
> open in the inferior. However, EBB registers are always saved and
> restored by the kernel, but not the PMU registers, so the ENODATA
> might have been meant for the PMU registers. For this reason GDB
> handles ENODATA for both regsets.
It would be good to clarify this with kernel people.
> Like for the previous patches, configure.srv is updated here to avoid
> breaking the build at this patch.
Same comment as before.
> <xi:include href="power-ppr.xml"/>
> <xi:include href="power-dscr.xml"/>
> <xi:include href="power-tar.xml"/>
> + <xi:include href="power-ebb.xml"/>
> + <xi:include href="power-pmu.xml"/>
> <xi:include href="power-htm.xml"/>
Adding these in the middle causes a bit of churn in the generated files.
(It re-shuffles the gdbserver protocol register buffer instead of just
adding to the end.) Now this *should* still all be compatible, but I
guess it would be better to avoid the churn; either add this patch
before the HTM patch, or else change the sequence in the XML file.
> /* Hardware transactional memory registers. */
> - PPC_TFHAR_REGNUM = 175,
> - PPC_TEXASR_REGNUM = 176,
> - PPC_TFIAR_REGNUM = 177,
> + PPC_TFHAR_REGNUM = 183,
> + PPC_TEXASR_REGNUM = 184,
> + PPC_TFIAR_REGNUM = 185,
Similar comment to above, can we not avoid this renumbering churn?
Also, I see you haven't got any test cases for this? Would these
be difficult to add?
Bye,
Ulrich
--
Dr. Ulrich Weigand
GNU/Linux compilers and toolchain
Ulrich.Weigand@de.ibm.com
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH 16/17] [PowerPC] Add support for EBB and PMU registers
2018-07-13 16:38 ` Ulrich Weigand
@ 2018-07-13 18:23 ` Pedro Franco de Carvalho
0 siblings, 0 replies; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 18:23 UTC (permalink / raw)
To: Ulrich Weigand; +Cc: gdb-patches, edjunior
Ulrich Weigand <uweigand@de.ibm.com> writes:
> Pedro Franco de Carvalho wrote:
> Similar comment to above, can we not avoid this renumbering churn?
Yes, I will change this.
> Also, I see you haven't got any test cases for this? Would these
> be difficult to add?
It's a bit harder, because it's not so straightforward to open the
performance events to put the inferior in a state where the ebb/pmu
registers are meaningful. I have a kludgy test I used, I'll try to make
it better for submission.
Thanks!
--
Pedro Franco de Carvalho
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 05/17] [PowerPC] Add support for PPR and DSCR
2018-07-13 13:53 [PATCH 00/17] GDB support for more powerpc registers on linux Pedro Franco de Carvalho
2018-07-13 13:53 ` [PATCH 16/17] [PowerPC] Add support for EBB and PMU registers Pedro Franco de Carvalho
@ 2018-07-13 13:53 ` Pedro Franco de Carvalho
2018-07-13 15:23 ` Ulrich Weigand
2018-07-13 13:53 ` [PATCH 09/17] [PowerPC] Add support for TAR Pedro Franco de Carvalho
` (14 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 13:53 UTC (permalink / raw)
To: gdb-patches; +Cc: uweigand, edjunior
From: Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
This patch adds gdb support for the Program Priorty Register and the
Data Stream Control Register, for the powerpc linux native and core
file targets.
The gdbserver implementation comes in the next patch. However, because
powerpc target description declarations are common to gdb and
gdbserver, the .dat files and gdbserver/configure.srv are altered
here, in order to avoid breaking the build at the commit corresponding
to this patch.
gdb/ChangeLog:
YYYY-MM-DD Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* arch/ppc-linux-tdesc.h (tdesc_powerpc_isa205_ppr_dscr_vsx32l)
(tdesc_powerpc_isa205_ppr_dscr_vsx64l): Declare.
* arch/ppc-linux-common.h (PPC_LINUX_SIZEOF_PPRREGSET)
(PPC_LINUX_SIZEOF_DSCRREGSET): Define.
(struct ppc_linux_features) <ppr_dscr>: New field.
(ppc_linux_no_features): Add initializer for ppr_dscr field.
* arch/ppc-linux-common.c (ppc_linux_match_description): Return
new tdescs.
* nat/ppc-linux.h (PPC_FEATURE2_DSCR, NT_PPC_PPR, NT_PPC_DSCR):
Define if not already defined.
* features/Makefile (WHICH): Add
rs6000/powerpc-isa205-ppr-dscr-vsx32l and
rs6000/powerpc-isa205-ppr-dscr-vsx64l.
(XMLTOC): Add rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml and
rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml.
* features/rs6000/power-dscr.xml: New file.
* features/rs6000/power-ppr.xml: New file.
* features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml: New file.
* features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml: New file.
* features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c: Generate.
* features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c: Generate.
* regformats/rs6000/powerpc-isa205-ppr-dscr-vsx32l.dat: Generate.
* regformats/rs6000/powerpc-isa205-ppr-dscr-vsx64l.dat: Generate.
* ppc-linux-nat.c: Include <sys/uio.h>.
(fetch_regset, store_regset, check_regset): New functions.
(fetch_register, fetch_ppc_registers): Call fetch_regset with DSCR
and PPR regsets.
(store_register, store_ppc_registers): Call store_regset with DSCR
and PPR regsets..
(ppc_linux_get_hwcap2): New function.
(ppc_linux_nat_target::read_description): Call
ppc_linux_get_hwcap2 and check_regset, set ppr_dscr field in the
features struct if needed.
* ppc-linux-tdep.c: Include
features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c and
features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c.
(ppc32_regmap_ppr, ppc32_regmap_dscr, ppc32_linux_pprregset)
(ppc32_linux_dscrregset): New globals.
(ppc_linux_iterate_over_regset_sections): Call back with the ppr
and dscr regsets.
(ppc_linux_core_read_description): Check if the ppr and dscr
sections are present and set ppr_dscr in the features struct.
(_initialize_ppc_linux_tdep): Call
initialize_tdesc_powerpc_isa205_ppr_dscr_vsx32l and
initialize_tdesc_powerpc_isa205_ppr_dscr_vsx64l.
* ppc-linux-tdep.h (ppc32_linux_pprregset)
(ppc32_linux_dscrregset): Declare.
* ppc-tdep.h (struct gdbarch_tdep) <ppc_ppr_regnum>: New field.
<ppc_dscr_regnum>: New field.
(enum) <PPC_PPR_REGNUM, PPC_DSCR_REGNUM>: New enum values.
* rs6000-tdep.c (rs6000_gdbarch_init): Look for and validate ppr
and dscr features.
gdb/gdbserver/ChangeLog:
YYYY-MM-DD Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* configure.srv (ipa_ppc_linux_regobj): Add
powerpc-isa205-ppr-dscr-vsx32l-ipa.o and
powerpc-isa205-ppr-dscr-vsx64l-ipa.o.
(powerpc*-*-linux*): Add powerpc-isa205-ppr-dscr-vsx32l.o and
powerpc-isa205-ppr-dscr-vsx64l.o to srv_regobj, add
rs6000/power-dscr.xml, rs6000/power-ppr.xml,
rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml and
rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml to srv_xmlfiles.
---
gdb/arch/ppc-linux-common.c | 6 +-
gdb/arch/ppc-linux-common.h | 4 +
gdb/arch/ppc-linux-tdesc.h | 2 +
gdb/features/Makefile | 4 +
gdb/features/rs6000/power-dscr.xml | 12 ++
gdb/features/rs6000/power-ppr.xml | 12 ++
.../rs6000/powerpc-isa205-ppr-dscr-vsx32l.c | 200 +++++++++++++++++++++
.../rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml | 18 ++
.../rs6000/powerpc-isa205-ppr-dscr-vsx64l.c | 200 +++++++++++++++++++++
.../rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml | 18 ++
gdb/gdbserver/configure.srv | 8 +-
gdb/nat/ppc-linux.h | 13 ++
gdb/ppc-linux-nat.c | 144 +++++++++++++++
gdb/ppc-linux-tdep.c | 44 +++++
gdb/ppc-linux-tdep.h | 4 +
gdb/ppc-tdep.h | 8 +
.../rs6000/powerpc-isa205-ppr-dscr-vsx32l.dat | 146 +++++++++++++++
.../rs6000/powerpc-isa205-ppr-dscr-vsx64l.dat | 146 +++++++++++++++
gdb/rs6000-tdep.c | 42 ++++-
19 files changed, 1027 insertions(+), 4 deletions(-)
create mode 100644 gdb/features/rs6000/power-dscr.xml
create mode 100644 gdb/features/rs6000/power-ppr.xml
create mode 100644 gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c
create mode 100644 gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml
create mode 100644 gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c
create mode 100644 gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml
create mode 100644 gdb/regformats/rs6000/powerpc-isa205-ppr-dscr-vsx32l.dat
create mode 100644 gdb/regformats/rs6000/powerpc-isa205-ppr-dscr-vsx64l.dat
diff --git a/gdb/arch/ppc-linux-common.c b/gdb/arch/ppc-linux-common.c
index eb7de40af0..7cf08eb7da 100644
--- a/gdb/arch/ppc-linux-common.c
+++ b/gdb/arch/ppc-linux-common.c
@@ -53,7 +53,8 @@ ppc_linux_match_description (struct ppc_linux_features features)
if (features.cell)
tdesc = tdesc_powerpc_cell64l;
else if (features.vsx)
- tdesc = (features.isa205? tdesc_powerpc_isa205_vsx64l
+ tdesc = (features.ppr_dscr? tdesc_powerpc_isa205_ppr_dscr_vsx64l
+ : features.isa205? tdesc_powerpc_isa205_vsx64l
: tdesc_powerpc_vsx64l);
else if (features.altivec)
tdesc = (features.isa205? tdesc_powerpc_isa205_altivec64l
@@ -69,7 +70,8 @@ ppc_linux_match_description (struct ppc_linux_features features)
if (features.cell)
tdesc = tdesc_powerpc_cell32l;
else if (features.vsx)
- tdesc = (features.isa205? tdesc_powerpc_isa205_vsx32l
+ tdesc = (features.ppr_dscr? tdesc_powerpc_isa205_ppr_dscr_vsx32l
+ : features.isa205? tdesc_powerpc_isa205_vsx32l
: tdesc_powerpc_vsx32l);
else if (features.altivec)
tdesc = (features.isa205? tdesc_powerpc_isa205_altivec32l
diff --git a/gdb/arch/ppc-linux-common.h b/gdb/arch/ppc-linux-common.h
index 2f535e801d..666954e765 100644
--- a/gdb/arch/ppc-linux-common.h
+++ b/gdb/arch/ppc-linux-common.h
@@ -30,6 +30,8 @@ struct target_desc;
#define PPC_LINUX_SIZEOF_VRREGSET 544
#define PPC_LINUX_SIZEOF_VSXREGSET 256
+#define PPC_LINUX_SIZEOF_PPRREGSET 8
+#define PPC_LINUX_SIZEOF_DSCRREGSET 8
/* Check if the hwcap auxv entry indicates that isa205 is supported. */
bool ppc_linux_has_isa205 (CORE_ADDR hwcap);
@@ -41,6 +43,7 @@ struct ppc_linux_features
bool altivec;
bool vsx;
bool isa205;
+ bool ppr_dscr;
bool cell;
};
@@ -51,6 +54,7 @@ const struct ppc_linux_features ppc_linux_no_features = {
false,
false,
false,
+ false,
};
/* Return a target description that matches FEATURES. */
diff --git a/gdb/arch/ppc-linux-tdesc.h b/gdb/arch/ppc-linux-tdesc.h
index 594c7c7c7c..3b5a2286e0 100644
--- a/gdb/arch/ppc-linux-tdesc.h
+++ b/gdb/arch/ppc-linux-tdesc.h
@@ -29,6 +29,7 @@ extern struct target_desc *tdesc_powerpc_vsx32l;
extern struct target_desc *tdesc_powerpc_isa205_32l;
extern struct target_desc *tdesc_powerpc_isa205_altivec32l;
extern struct target_desc *tdesc_powerpc_isa205_vsx32l;
+extern struct target_desc *tdesc_powerpc_isa205_ppr_dscr_vsx32l;
extern struct target_desc *tdesc_powerpc_e500l;
extern struct target_desc *tdesc_powerpc_64l;
@@ -38,5 +39,6 @@ extern struct target_desc *tdesc_powerpc_vsx64l;
extern struct target_desc *tdesc_powerpc_isa205_64l;
extern struct target_desc *tdesc_powerpc_isa205_altivec64l;
extern struct target_desc *tdesc_powerpc_isa205_vsx64l;
+extern struct target_desc *tdesc_powerpc_isa205_ppr_dscr_vsx64l;
#endif /* ARCH_PPC_LINUX_TDESC_H */
diff --git a/gdb/features/Makefile b/gdb/features/Makefile
index 168c46e003..9755646e2e 100644
--- a/gdb/features/Makefile
+++ b/gdb/features/Makefile
@@ -73,6 +73,8 @@ WHICH = aarch64 \
rs6000/powerpc-isa205-32l rs6000/powerpc-isa205-64l \
rs6000/powerpc-isa205-altivec32l rs6000/powerpc-isa205-altivec64l \
rs6000/powerpc-isa205-vsx32l rs6000/powerpc-isa205-vsx64l \
+ rs6000/powerpc-isa205-ppr-dscr-vsx32l \
+ rs6000/powerpc-isa205-ppr-dscr-vsx64l \
s390-linux32 s390-linux64 s390x-linux64 \
s390-linux32v1 s390-linux64v1 s390x-linux64v1 \
s390-linux32v2 s390-linux64v2 s390x-linux64v2 \
@@ -167,6 +169,8 @@ XMLTOC = \
rs6000/powerpc-isa205-altivec64l.xml \
rs6000/powerpc-isa205-vsx32l.xml \
rs6000/powerpc-isa205-vsx64l.xml \
+ rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml \
+ rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml \
rs6000/powerpc-vsx32.xml \
rs6000/powerpc-vsx32l.xml \
rs6000/powerpc-vsx64.xml \
diff --git a/gdb/features/rs6000/power-dscr.xml b/gdb/features/rs6000/power-dscr.xml
new file mode 100644
index 0000000000..98a0bcacb9
--- /dev/null
+++ b/gdb/features/rs6000/power-dscr.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- POWER Data Stream Control Register. -->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.power.dscr">
+ <reg name="dscr" bitsize="64" type="uint64"/>
+</feature>
diff --git a/gdb/features/rs6000/power-ppr.xml b/gdb/features/rs6000/power-ppr.xml
new file mode 100644
index 0000000000..bf76544a49
--- /dev/null
+++ b/gdb/features/rs6000/power-ppr.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- POWER Program Priority Register. -->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.power.ppr">
+ <reg name="ppr" bitsize="64" type="uint64"/>
+</feature>
diff --git a/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c b/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c
new file mode 100644
index 0000000000..c8f56ea029
--- /dev/null
+++ b/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c
@@ -0,0 +1,200 @@
+/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
+ Original: powerpc-isa205-ppr-dscr-vsx32l.xml */
+
+#include "defs.h"
+#include "osabi.h"
+#include "target-descriptions.h"
+
+struct target_desc *tdesc_powerpc_isa205_ppr_dscr_vsx32l;
+static void
+initialize_tdesc_powerpc_isa205_ppr_dscr_vsx32l (void)
+{
+ struct target_desc *result = allocate_target_description ();
+ set_tdesc_architecture (result, bfd_scan_arch ("powerpc:common"));
+
+ struct tdesc_feature *feature;
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.core");
+ tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r13", 13, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r14", 14, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r15", 15, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r16", 16, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r17", 17, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r18", 18, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r19", 19, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r20", 20, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r21", 21, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r22", 22, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r23", 23, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r24", 24, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r25", 25, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r26", 26, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r27", 27, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r28", 28, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "pc", 64, 1, NULL, 32, "code_ptr");
+ tdesc_create_reg (feature, "msr", 65, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr", 66, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "lr", 67, 1, NULL, 32, "code_ptr");
+ tdesc_create_reg (feature, "ctr", 68, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "xer", 69, 1, NULL, 32, "uint32");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.fpu");
+ tdesc_create_reg (feature, "f0", 32, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f1", 33, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f2", 34, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f3", 35, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f4", 36, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f5", 37, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f6", 38, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f7", 39, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f8", 40, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f9", 41, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f10", 42, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f11", 43, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f12", 44, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f13", 45, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f14", 46, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f15", 47, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f16", 48, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f17", 49, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f18", 50, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f19", 51, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f20", 52, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f21", 53, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f22", 54, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f23", 55, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f24", 56, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f25", 57, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f26", 58, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f27", 59, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f28", 60, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f29", 61, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f30", 62, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f31", 63, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "fpscr", 70, 1, "float", 64, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.linux");
+ tdesc_create_reg (feature, "orig_r3", 71, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "trap", 72, 1, NULL, 32, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.altivec");
+ tdesc_type *element_type;
+ element_type = tdesc_named_type (feature, "ieee_single");
+ tdesc_create_vector (feature, "v4f", element_type, 4);
+
+ element_type = tdesc_named_type (feature, "int32");
+ tdesc_create_vector (feature, "v4i32", element_type, 4);
+
+ element_type = tdesc_named_type (feature, "int16");
+ tdesc_create_vector (feature, "v8i16", element_type, 8);
+
+ element_type = tdesc_named_type (feature, "int8");
+ tdesc_create_vector (feature, "v16i8", element_type, 16);
+
+ tdesc_type_with_fields *type_with_fields;
+ type_with_fields = tdesc_create_union (feature, "vec128");
+ tdesc_type *field_type;
+ field_type = tdesc_named_type (feature, "uint128");
+ tdesc_add_field (type_with_fields, "uint128", field_type);
+ field_type = tdesc_named_type (feature, "v4f");
+ tdesc_add_field (type_with_fields, "v4_float", field_type);
+ field_type = tdesc_named_type (feature, "v4i32");
+ tdesc_add_field (type_with_fields, "v4_int32", field_type);
+ field_type = tdesc_named_type (feature, "v8i16");
+ tdesc_add_field (type_with_fields, "v8_int16", field_type);
+ field_type = tdesc_named_type (feature, "v16i8");
+ tdesc_add_field (type_with_fields, "v16_int8", field_type);
+
+ tdesc_create_reg (feature, "vr0", 73, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr1", 74, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr2", 75, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr3", 76, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr4", 77, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr5", 78, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr6", 79, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr7", 80, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr8", 81, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr9", 82, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr10", 83, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr11", 84, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr12", 85, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr13", 86, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr14", 87, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr15", 88, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr16", 89, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr17", 90, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr18", 91, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr19", 92, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr20", 93, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr21", 94, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr22", 95, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr23", 96, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr24", 97, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr25", 98, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr26", 99, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr27", 100, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr28", 101, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr29", 102, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr30", 103, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr31", 104, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vscr", 105, 1, "vector", 32, "int");
+ tdesc_create_reg (feature, "vrsave", 106, 1, "vector", 32, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.vsx");
+ tdesc_create_reg (feature, "vs0h", 107, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs1h", 108, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs2h", 109, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs3h", 110, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs4h", 111, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs5h", 112, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs6h", 113, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs7h", 114, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs8h", 115, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs9h", 116, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs10h", 117, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs11h", 118, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs12h", 119, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs13h", 120, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs14h", 121, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs15h", 122, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs16h", 123, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs17h", 124, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs18h", 125, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs19h", 126, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs20h", 127, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs21h", 128, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs22h", 129, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs23h", 130, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs24h", 131, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs25h", 132, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs26h", 133, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs27h", 134, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs28h", 135, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs29h", 136, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs30h", 137, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs31h", 138, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.ppr");
+ tdesc_create_reg (feature, "ppr", 139, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.dscr");
+ tdesc_create_reg (feature, "dscr", 140, 1, NULL, 64, "uint64");
+
+ tdesc_powerpc_isa205_ppr_dscr_vsx32l = result;
+}
diff --git a/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml b/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml
new file mode 100644
index 0000000000..6f46f8908a
--- /dev/null
+++ b/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>powerpc:common</architecture>
+ <xi:include href="power-core.xml"/>
+ <xi:include href="power-fpu-isa205.xml"/>
+ <xi:include href="power-linux.xml"/>
+ <xi:include href="power-altivec.xml"/>
+ <xi:include href="power-vsx.xml"/>
+ <xi:include href="power-ppr.xml"/>
+ <xi:include href="power-dscr.xml"/>
+</target>
diff --git a/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c b/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c
new file mode 100644
index 0000000000..76e32f3b1b
--- /dev/null
+++ b/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c
@@ -0,0 +1,200 @@
+/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
+ Original: powerpc-isa205-ppr-dscr-vsx64l.xml */
+
+#include "defs.h"
+#include "osabi.h"
+#include "target-descriptions.h"
+
+struct target_desc *tdesc_powerpc_isa205_ppr_dscr_vsx64l;
+static void
+initialize_tdesc_powerpc_isa205_ppr_dscr_vsx64l (void)
+{
+ struct target_desc *result = allocate_target_description ();
+ set_tdesc_architecture (result, bfd_scan_arch ("powerpc:common64"));
+
+ struct tdesc_feature *feature;
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.core");
+ tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "pc", 64, 1, NULL, 64, "code_ptr");
+ tdesc_create_reg (feature, "msr", 65, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr", 66, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "lr", 67, 1, NULL, 64, "code_ptr");
+ tdesc_create_reg (feature, "ctr", 68, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "xer", 69, 1, NULL, 32, "uint32");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.fpu");
+ tdesc_create_reg (feature, "f0", 32, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f1", 33, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f2", 34, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f3", 35, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f4", 36, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f5", 37, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f6", 38, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f7", 39, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f8", 40, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f9", 41, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f10", 42, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f11", 43, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f12", 44, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f13", 45, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f14", 46, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f15", 47, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f16", 48, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f17", 49, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f18", 50, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f19", 51, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f20", 52, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f21", 53, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f22", 54, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f23", 55, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f24", 56, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f25", 57, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f26", 58, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f27", 59, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f28", 60, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f29", 61, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f30", 62, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f31", 63, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "fpscr", 70, 1, "float", 64, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.linux");
+ tdesc_create_reg (feature, "orig_r3", 71, 1, NULL, 64, "int");
+ tdesc_create_reg (feature, "trap", 72, 1, NULL, 64, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.altivec");
+ tdesc_type *element_type;
+ element_type = tdesc_named_type (feature, "ieee_single");
+ tdesc_create_vector (feature, "v4f", element_type, 4);
+
+ element_type = tdesc_named_type (feature, "int32");
+ tdesc_create_vector (feature, "v4i32", element_type, 4);
+
+ element_type = tdesc_named_type (feature, "int16");
+ tdesc_create_vector (feature, "v8i16", element_type, 8);
+
+ element_type = tdesc_named_type (feature, "int8");
+ tdesc_create_vector (feature, "v16i8", element_type, 16);
+
+ tdesc_type_with_fields *type_with_fields;
+ type_with_fields = tdesc_create_union (feature, "vec128");
+ tdesc_type *field_type;
+ field_type = tdesc_named_type (feature, "uint128");
+ tdesc_add_field (type_with_fields, "uint128", field_type);
+ field_type = tdesc_named_type (feature, "v4f");
+ tdesc_add_field (type_with_fields, "v4_float", field_type);
+ field_type = tdesc_named_type (feature, "v4i32");
+ tdesc_add_field (type_with_fields, "v4_int32", field_type);
+ field_type = tdesc_named_type (feature, "v8i16");
+ tdesc_add_field (type_with_fields, "v8_int16", field_type);
+ field_type = tdesc_named_type (feature, "v16i8");
+ tdesc_add_field (type_with_fields, "v16_int8", field_type);
+
+ tdesc_create_reg (feature, "vr0", 73, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr1", 74, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr2", 75, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr3", 76, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr4", 77, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr5", 78, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr6", 79, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr7", 80, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr8", 81, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr9", 82, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr10", 83, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr11", 84, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr12", 85, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr13", 86, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr14", 87, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr15", 88, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr16", 89, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr17", 90, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr18", 91, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr19", 92, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr20", 93, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr21", 94, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr22", 95, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr23", 96, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr24", 97, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr25", 98, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr26", 99, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr27", 100, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr28", 101, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr29", 102, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr30", 103, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr31", 104, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vscr", 105, 1, "vector", 32, "int");
+ tdesc_create_reg (feature, "vrsave", 106, 1, "vector", 32, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.vsx");
+ tdesc_create_reg (feature, "vs0h", 107, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs1h", 108, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs2h", 109, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs3h", 110, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs4h", 111, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs5h", 112, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs6h", 113, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs7h", 114, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs8h", 115, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs9h", 116, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs10h", 117, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs11h", 118, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs12h", 119, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs13h", 120, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs14h", 121, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs15h", 122, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs16h", 123, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs17h", 124, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs18h", 125, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs19h", 126, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs20h", 127, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs21h", 128, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs22h", 129, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs23h", 130, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs24h", 131, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs25h", 132, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs26h", 133, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs27h", 134, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs28h", 135, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs29h", 136, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs30h", 137, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs31h", 138, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.ppr");
+ tdesc_create_reg (feature, "ppr", 139, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.dscr");
+ tdesc_create_reg (feature, "dscr", 140, 1, NULL, 64, "uint64");
+
+ tdesc_powerpc_isa205_ppr_dscr_vsx64l = result;
+}
diff --git a/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml b/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml
new file mode 100644
index 0000000000..8cfd7ac1e5
--- /dev/null
+++ b/gdb/features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>powerpc:common64</architecture>
+ <xi:include href="power64-core.xml"/>
+ <xi:include href="power-fpu-isa205.xml"/>
+ <xi:include href="power64-linux.xml"/>
+ <xi:include href="power-altivec.xml"/>
+ <xi:include href="power-vsx.xml"/>
+ <xi:include href="power-ppr.xml"/>
+ <xi:include href="power-dscr.xml"/>
+</target>
diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
index 72e6a0d87f..eef13966f1 100644
--- a/gdb/gdbserver/configure.srv
+++ b/gdb/gdbserver/configure.srv
@@ -32,7 +32,7 @@ else
srv_amd64_linux_regobj=""
fi
-ipa_ppc_linux_regobj="powerpc-32l-ipa.o powerpc-altivec32l-ipa.o powerpc-cell32l-ipa.o powerpc-vsx32l-ipa.o powerpc-isa205-32l-ipa.o powerpc-isa205-altivec32l-ipa.o powerpc-isa205-vsx32l-ipa.o powerpc-e500l-ipa.o powerpc-64l-ipa.o powerpc-altivec64l-ipa.o powerpc-cell64l-ipa.o powerpc-vsx64l-ipa.o powerpc-isa205-64l-ipa.o powerpc-isa205-altivec64l-ipa.o powerpc-isa205-vsx64l-ipa.o"
+ipa_ppc_linux_regobj="powerpc-32l-ipa.o powerpc-altivec32l-ipa.o powerpc-cell32l-ipa.o powerpc-vsx32l-ipa.o powerpc-isa205-32l-ipa.o powerpc-isa205-altivec32l-ipa.o powerpc-isa205-vsx32l-ipa.o powerpc-isa205-ppr-dscr-vsx32l-ipa.o powerpc-e500l-ipa.o powerpc-64l-ipa.o powerpc-altivec64l-ipa.o powerpc-cell64l-ipa.o powerpc-vsx64l-ipa.o powerpc-isa205-64l-ipa.o powerpc-isa205-altivec64l-ipa.o powerpc-isa205-vsx64l-ipa.o powerpc-isa205-ppr-dscr-vsx64l-ipa.o"
# Linux object files. This is so we don't have to repeat
# these files over and over again.
@@ -217,6 +217,7 @@ case "${target}" in
srv_regobj="${srv_regobj} powerpc-isa205-32l.o"
srv_regobj="${srv_regobj} powerpc-isa205-altivec32l.o"
srv_regobj="${srv_regobj} powerpc-isa205-vsx32l.o"
+ srv_regobj="${srv_regobj} powerpc-isa205-ppr-dscr-vsx32l.o"
srv_regobj="${srv_regobj} powerpc-e500l.o"
srv_regobj="${srv_regobj} powerpc-64l.o"
srv_regobj="${srv_regobj} powerpc-altivec64l.o"
@@ -225,6 +226,7 @@ case "${target}" in
srv_regobj="${srv_regobj} powerpc-isa205-64l.o"
srv_regobj="${srv_regobj} powerpc-isa205-altivec64l.o"
srv_regobj="${srv_regobj} powerpc-isa205-vsx64l.o"
+ srv_regobj="${srv_regobj} powerpc-isa205-ppr-dscr-vsx64l.o"
srv_tgtobj="$srv_linux_obj linux-ppc-low.o ppc-linux.o"
srv_tgtobj="${srv_tgtobj} arch/ppc-linux-common.o"
srv_xmlfiles="rs6000/powerpc-32l.xml"
@@ -234,12 +236,15 @@ case "${target}" in
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-32l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-altivec32l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-vsx32l.xml"
+ srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-altivec.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-vsx.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-core.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-linux.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-fpu.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-fpu-isa205.xml"
+ srv_xmlfiles="${srv_xmlfiles} rs6000/power-dscr.xml"
+ srv_xmlfiles="${srv_xmlfiles} rs6000/power-ppr.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-e500l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-spe.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-64l.xml"
@@ -249,6 +254,7 @@ case "${target}" in
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-64l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-altivec64l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-vsx64l.xml"
+ srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power64-core.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power64-linux.xml"
srv_linux_usrregs=yes
diff --git a/gdb/nat/ppc-linux.h b/gdb/nat/ppc-linux.h
index 3d4d4fdc56..c2b8b0e80c 100644
--- a/gdb/nat/ppc-linux.h
+++ b/gdb/nat/ppc-linux.h
@@ -51,6 +51,9 @@
#ifndef PPC_FEATURE_HAS_SPE
#define PPC_FEATURE_HAS_SPE 0x00800000
#endif
+#ifndef PPC_FEATURE2_DSCR
+#define PPC_FEATURE2_DSCR 0x20000000
+#endif
/* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
configure time check. Some older glibc's (for instance 2.2.1)
@@ -82,6 +85,16 @@
#define PTRACE_SETEVRREGS 21
#endif
+/* Program Priority Register. */
+#ifndef NT_PPC_PPR
+#define NT_PPC_PPR 0x104
+#endif
+
+/* Data Stream Control Register. */
+#ifndef NT_PPC_DSCR
+#define NT_PPC_DSCR 0x105
+#endif
+
/* Return the wordsize of the target, either 4 or 8 bytes. */
int ppc_linux_target_wordsize (int tid);
diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c
index 47028b8688..c560f88c7d 100644
--- a/gdb/ppc-linux-nat.c
+++ b/gdb/ppc-linux-nat.c
@@ -31,6 +31,7 @@
#include <signal.h>
#include <sys/user.h>
#include <sys/ioctl.h>
+#include <sys/uio.h>
#include "gdb_wait.h"
#include <fcntl.h>
#include <sys/procfs.h>
@@ -528,6 +529,78 @@ fetch_spe_register (struct regcache *regcache, int tid, int regno)
regcache->raw_supply (tdep->ppc_spefscr_regnum, &evrregs.spefscr);
}
+/* Use ptrace to fetch all registers from the register set with note
+ type REGSET_ID, size REGSIZE, and layout described by REGSET, from
+ process/thread TID and supply their values to REGCACHE. If ptrace
+ returns ENODATA to indicate the regset is unavailable, mark the
+ registers as unavailable in REGCACHE. */
+
+static void
+fetch_regset (struct regcache *regcache, int tid,
+ int regset_id, int regsetsize, const struct regset *regset)
+{
+ void *buf = alloca (regsetsize);
+ struct iovec iov;
+
+ iov.iov_base = buf;
+ iov.iov_len = regsetsize;
+
+ if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) < 0)
+ {
+ if (errno == ENODATA)
+ regcache_supply_regset (regset, regcache, -1, NULL, regsetsize);
+ else
+ perror_with_name (_("Couldn't get register set"));
+ }
+ else
+ regcache_supply_regset (regset, regcache, -1, buf, regsetsize);
+}
+
+/* Use ptrace to store register REGNUM of the regset with note type
+ REGSET_ID, size REGSETSIZE, and layout described by REGSET, from
+ REGCACHE back to process/thread TID. If REGNUM is -1 all registers
+ in the set are collected and stored. */
+
+static void
+store_regset (const struct regcache *regcache, int tid, int regnum,
+ int regset_id, int regsetsize, const struct regset *regset)
+{
+ void *buf = alloca (regsetsize);
+ struct iovec iov;
+
+ iov.iov_base = buf;
+ iov.iov_len = regsetsize;
+
+ /* Make sure that the buffer that will be stored has up to date values
+ for the registers that won't be collected. */
+ if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) < 0)
+ perror_with_name (_("Couldn't get register set"));
+
+ regcache_collect_regset (regset, regcache, regnum, buf, regsetsize);
+
+ if (ptrace (PTRACE_SETREGSET, tid, regset_id, &iov) < 0)
+ perror_with_name (_("Couldn't set register set"));
+}
+
+/* Check whether the kernel provides a register set with number
+ REGSET_ID of size REGSETSIZE for process/thread TID. */
+
+static bool
+check_regset (int tid, int regset_id, int regsetsize)
+{
+ void *buf = alloca (regsetsize);
+ struct iovec iov;
+
+ iov.iov_base = buf;
+ iov.iov_len = regsetsize;
+
+ if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0
+ || errno == ENODATA)
+ return true;
+ else
+ return false;
+}
+
static void
fetch_register (struct regcache *regcache, int tid, int regno)
{
@@ -567,6 +640,24 @@ fetch_register (struct regcache *regcache, int tid, int regno)
fetch_spe_register (regcache, tid, regno);
return;
}
+ else if (regno == PPC_DSCR_REGNUM)
+ {
+ gdb_assert (tdep->ppc_dscr_regnum != -1);
+
+ fetch_regset (regcache, tid, NT_PPC_DSCR,
+ PPC_LINUX_SIZEOF_DSCRREGSET,
+ &ppc32_linux_dscrregset);
+ return;
+ }
+ else if (regno == PPC_PPR_REGNUM)
+ {
+ gdb_assert (tdep->ppc_ppr_regnum != -1);
+
+ fetch_regset (regcache, tid, NT_PPC_PPR,
+ PPC_LINUX_SIZEOF_PPRREGSET,
+ &ppc32_linux_pprregset);
+ return;
+ }
if (regaddr == -1)
{
@@ -763,6 +854,14 @@ fetch_ppc_registers (struct regcache *regcache, int tid)
fetch_vsx_registers (regcache, tid, -1);
if (tdep->ppc_ev0_upper_regnum >= 0)
fetch_spe_register (regcache, tid, -1);
+ if (tdep->ppc_ppr_regnum != -1)
+ fetch_regset (regcache, tid, NT_PPC_PPR,
+ PPC_LINUX_SIZEOF_PPRREGSET,
+ &ppc32_linux_pprregset);
+ if (tdep->ppc_dscr_regnum != -1)
+ fetch_regset (regcache, tid, NT_PPC_DSCR,
+ PPC_LINUX_SIZEOF_DSCRREGSET,
+ &ppc32_linux_dscrregset);
}
/* Fetch registers from the child process. Fetch all registers if
@@ -943,6 +1042,24 @@ store_register (const struct regcache *regcache, int tid, int regno)
store_spe_register (regcache, tid, regno);
return;
}
+ else if (regno == PPC_DSCR_REGNUM)
+ {
+ gdb_assert (tdep->ppc_dscr_regnum != -1);
+
+ store_regset (regcache, tid, regno, NT_PPC_DSCR,
+ PPC_LINUX_SIZEOF_DSCRREGSET,
+ &ppc32_linux_dscrregset);
+ return;
+ }
+ else if (regno == PPC_PPR_REGNUM)
+ {
+ gdb_assert (tdep->ppc_ppr_regnum != -1);
+
+ store_regset (regcache, tid, regno, NT_PPC_PPR,
+ PPC_LINUX_SIZEOF_PPRREGSET,
+ &ppc32_linux_pprregset);
+ return;
+ }
if (regaddr == -1)
return;
@@ -1157,6 +1274,14 @@ store_ppc_registers (const struct regcache *regcache, int tid)
store_vsx_registers (regcache, tid, -1);
if (tdep->ppc_ev0_upper_regnum >= 0)
store_spe_register (regcache, tid, -1);
+ if (tdep->ppc_ppr_regnum != -1)
+ store_regset (regcache, tid, -1, NT_PPC_PPR,
+ PPC_LINUX_SIZEOF_PPRREGSET,
+ &ppc32_linux_pprregset);
+ if (tdep->ppc_dscr_regnum != -1)
+ store_regset (regcache, tid, -1, NT_PPC_DSCR,
+ PPC_LINUX_SIZEOF_DSCRREGSET,
+ &ppc32_linux_dscrregset);
}
/* Fetch the AT_HWCAP entry from the aux vector. */
@@ -1171,6 +1296,19 @@ ppc_linux_get_hwcap (void)
return field;
}
+/* Fetch the AT_HWCAP2 entry from the aux vector. */
+
+static CORE_ADDR
+ppc_linux_get_hwcap2 (void)
+{
+ CORE_ADDR field;
+
+ if (target_auxv_search (current_top_target (), AT_HWCAP2, &field) != 1)
+ return 0;
+
+ return field;
+}
+
/* The cached DABR value, to install in new threads.
This variable is used when the PowerPC HWDEBUG ptrace
interface is not available. */
@@ -2232,6 +2370,7 @@ ppc_linux_nat_target::read_description ()
features.wordsize = ppc_linux_target_wordsize (tid);
CORE_ADDR hwcap = ppc_linux_get_hwcap ();
+ CORE_ADDR hwcap2 = ppc_linux_get_hwcap2 ();
if (have_ptrace_getsetvsxregs
&& (hwcap & PPC_FEATURE_HAS_VSX))
@@ -2266,6 +2405,11 @@ ppc_linux_nat_target::read_description ()
features.isa205 = ppc_linux_has_isa205 (hwcap);
+ if ((hwcap2 & PPC_FEATURE2_DSCR)
+ && check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET)
+ && check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET))
+ features.ppr_dscr = true;
+
return ppc_linux_match_description (features);
}
diff --git a/gdb/ppc-linux-tdep.c b/gdb/ppc-linux-tdep.c
index 33a0b5a83b..7dac5d22b9 100644
--- a/gdb/ppc-linux-tdep.c
+++ b/gdb/ppc-linux-tdep.c
@@ -71,6 +71,7 @@
#include "features/rs6000/powerpc-isa205-32l.c"
#include "features/rs6000/powerpc-isa205-altivec32l.c"
#include "features/rs6000/powerpc-isa205-vsx32l.c"
+#include "features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c"
#include "features/rs6000/powerpc-64l.c"
#include "features/rs6000/powerpc-altivec64l.c"
#include "features/rs6000/powerpc-cell64l.c"
@@ -78,6 +79,7 @@
#include "features/rs6000/powerpc-isa205-64l.c"
#include "features/rs6000/powerpc-isa205-altivec64l.c"
#include "features/rs6000/powerpc-isa205-vsx64l.c"
+#include "features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c"
#include "features/rs6000/powerpc-e500l.c"
/* Shared library operations for PowerPC-Linux. */
@@ -503,6 +505,18 @@ static const struct ppc_reg_offsets ppc64_linux_reg_offsets =
/* .fpscr_size = */ 8
};
+static const struct regcache_map_entry ppc32_regmap_ppr[] =
+ {
+ { 1, PPC_PPR_REGNUM, 8 },
+ { 0 }
+ };
+
+static const struct regcache_map_entry ppc32_regmap_dscr[] =
+ {
+ { 1, PPC_DSCR_REGNUM, 8 },
+ { 0 }
+ };
+
static const struct regset ppc32_linux_gregset = {
&ppc32_linux_reg_offsets,
ppc_linux_supply_gregset,
@@ -565,6 +579,18 @@ static const struct regset ppc32_linux_vsxregset = {
regcache_collect_regset
};
+const struct regset ppc32_linux_pprregset = {
+ ppc32_regmap_ppr,
+ regcache_supply_regset,
+ regcache_collect_regset
+};
+
+const struct regset ppc32_linux_dscrregset = {
+ ppc32_regmap_dscr,
+ regcache_supply_regset,
+ regcache_collect_regset
+};
+
const struct regset *
ppc_linux_gregset (int wordsize)
{
@@ -603,6 +629,8 @@ ppc_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
int have_altivec = tdep->ppc_vr0_regnum != -1;
int have_vsx = tdep->ppc_vsr0_upper_regnum != -1;
+ int have_ppr = tdep->ppc_ppr_regnum != -1;
+ int have_dscr = tdep->ppc_dscr_regnum != -1;
if (tdep->wordsize == 4)
cb (".reg", 48 * 4, &ppc32_linux_gregset, NULL, cb_data);
@@ -621,6 +649,15 @@ ppc_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
if (have_vsx)
cb (".reg-ppc-vsx", PPC_LINUX_SIZEOF_VSXREGSET,
&ppc32_linux_vsxregset, "POWER7 VSX", cb_data);
+
+ if (have_ppr)
+ cb (".reg-ppc-ppr", PPC_LINUX_SIZEOF_PPRREGSET,
+ &ppc32_linux_pprregset, "Priority Program Register", cb_data);
+
+ if (have_dscr)
+ cb (".reg-ppc-dscr", PPC_LINUX_SIZEOF_DSCRREGSET,
+ &ppc32_linux_dscrregset, "Data Stream Control Register",
+ cb_data);
}
static void
@@ -1033,6 +1070,8 @@ ppc_linux_core_read_description (struct gdbarch *gdbarch,
asection *altivec = bfd_get_section_by_name (abfd, ".reg-ppc-vmx");
asection *vsx = bfd_get_section_by_name (abfd, ".reg-ppc-vsx");
asection *section = bfd_get_section_by_name (abfd, ".reg");
+ asection *ppr = bfd_get_section_by_name (abfd, ".reg-ppc-ppr");
+ asection *dscr = bfd_get_section_by_name (abfd, ".reg-ppc-dscr");
if (! section)
return NULL;
@@ -1065,6 +1104,9 @@ ppc_linux_core_read_description (struct gdbarch *gdbarch,
features.isa205 = ppc_linux_has_isa205 (hwcap);
+ if (ppr && dscr)
+ features.ppr_dscr = true;
+
return ppc_linux_match_description (features);
}
@@ -1938,6 +1980,7 @@ _initialize_ppc_linux_tdep (void)
initialize_tdesc_powerpc_isa205_32l ();
initialize_tdesc_powerpc_isa205_altivec32l ();
initialize_tdesc_powerpc_isa205_vsx32l ();
+ initialize_tdesc_powerpc_isa205_ppr_dscr_vsx32l ();
initialize_tdesc_powerpc_64l ();
initialize_tdesc_powerpc_altivec64l ();
initialize_tdesc_powerpc_cell64l ();
@@ -1945,5 +1988,6 @@ _initialize_ppc_linux_tdep (void)
initialize_tdesc_powerpc_isa205_64l ();
initialize_tdesc_powerpc_isa205_altivec64l ();
initialize_tdesc_powerpc_isa205_vsx64l ();
+ initialize_tdesc_powerpc_isa205_ppr_dscr_vsx64l ();
initialize_tdesc_powerpc_e500l ();
}
diff --git a/gdb/ppc-linux-tdep.h b/gdb/ppc-linux-tdep.h
index 51f4b506a1..e8ae23137c 100644
--- a/gdb/ppc-linux-tdep.h
+++ b/gdb/ppc-linux-tdep.h
@@ -44,4 +44,8 @@ enum {
/* Return 1 if PPC_ORIG_R3_REGNUM and PPC_TRAP_REGNUM are usable. */
int ppc_linux_trap_reg_p (struct gdbarch *gdbarch);
+/* Additional register sets, defined in ppc-linux-tdep.c. */
+extern const struct regset ppc32_linux_pprregset;
+extern const struct regset ppc32_linux_dscrregset;
+
#endif /* PPC_LINUX_TDEP_H */
diff --git a/gdb/ppc-tdep.h b/gdb/ppc-tdep.h
index c3571cbd51..86b5a3645d 100644
--- a/gdb/ppc-tdep.h
+++ b/gdb/ppc-tdep.h
@@ -253,6 +253,12 @@ struct gdbarch_tdep
int ppc_acc_regnum; /* SPE 'acc' register. */
int ppc_spefscr_regnum; /* SPE 'spefscr' register. */
+ /* Program Priority Register. */
+ int ppc_ppr_regnum;
+
+ /* Data Stream Control Register. */
+ int ppc_dscr_regnum;
+
/* Decimal 128 registers. */
int ppc_dl0_regnum; /* First Decimal128 argument register pair. */
@@ -309,6 +315,8 @@ enum {
PPC_VRSAVE_REGNUM = 139,
PPC_VSR0_UPPER_REGNUM = 140,
PPC_VSR31_UPPER_REGNUM = 171,
+ PPC_PPR_REGNUM = 172,
+ PPC_DSCR_REGNUM = 173,
PPC_NUM_REGS
};
diff --git a/gdb/regformats/rs6000/powerpc-isa205-ppr-dscr-vsx32l.dat b/gdb/regformats/rs6000/powerpc-isa205-ppr-dscr-vsx32l.dat
new file mode 100644
index 0000000000..31a7d02e95
--- /dev/null
+++ b/gdb/regformats/rs6000/powerpc-isa205-ppr-dscr-vsx32l.dat
@@ -0,0 +1,146 @@
+# THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi :set ro:
+# Generated from: rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml
+name:powerpc_isa205_ppr_dscr_vsx32l
+xmltarget:powerpc-isa205-ppr-dscr-vsx32l.xml
+expedite:r1,pc
+32:r0
+32:r1
+32:r2
+32:r3
+32:r4
+32:r5
+32:r6
+32:r7
+32:r8
+32:r9
+32:r10
+32:r11
+32:r12
+32:r13
+32:r14
+32:r15
+32:r16
+32:r17
+32:r18
+32:r19
+32:r20
+32:r21
+32:r22
+32:r23
+32:r24
+32:r25
+32:r26
+32:r27
+32:r28
+32:r29
+32:r30
+32:r31
+64:f0
+64:f1
+64:f2
+64:f3
+64:f4
+64:f5
+64:f6
+64:f7
+64:f8
+64:f9
+64:f10
+64:f11
+64:f12
+64:f13
+64:f14
+64:f15
+64:f16
+64:f17
+64:f18
+64:f19
+64:f20
+64:f21
+64:f22
+64:f23
+64:f24
+64:f25
+64:f26
+64:f27
+64:f28
+64:f29
+64:f30
+64:f31
+32:pc
+32:msr
+32:cr
+32:lr
+32:ctr
+32:xer
+64:fpscr
+32:orig_r3
+32:trap
+128:vr0
+128:vr1
+128:vr2
+128:vr3
+128:vr4
+128:vr5
+128:vr6
+128:vr7
+128:vr8
+128:vr9
+128:vr10
+128:vr11
+128:vr12
+128:vr13
+128:vr14
+128:vr15
+128:vr16
+128:vr17
+128:vr18
+128:vr19
+128:vr20
+128:vr21
+128:vr22
+128:vr23
+128:vr24
+128:vr25
+128:vr26
+128:vr27
+128:vr28
+128:vr29
+128:vr30
+128:vr31
+32:vscr
+32:vrsave
+64:vs0h
+64:vs1h
+64:vs2h
+64:vs3h
+64:vs4h
+64:vs5h
+64:vs6h
+64:vs7h
+64:vs8h
+64:vs9h
+64:vs10h
+64:vs11h
+64:vs12h
+64:vs13h
+64:vs14h
+64:vs15h
+64:vs16h
+64:vs17h
+64:vs18h
+64:vs19h
+64:vs20h
+64:vs21h
+64:vs22h
+64:vs23h
+64:vs24h
+64:vs25h
+64:vs26h
+64:vs27h
+64:vs28h
+64:vs29h
+64:vs30h
+64:vs31h
+64:ppr
+64:dscr
diff --git a/gdb/regformats/rs6000/powerpc-isa205-ppr-dscr-vsx64l.dat b/gdb/regformats/rs6000/powerpc-isa205-ppr-dscr-vsx64l.dat
new file mode 100644
index 0000000000..74c8feb3ee
--- /dev/null
+++ b/gdb/regformats/rs6000/powerpc-isa205-ppr-dscr-vsx64l.dat
@@ -0,0 +1,146 @@
+# THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi :set ro:
+# Generated from: rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml
+name:powerpc_isa205_ppr_dscr_vsx64l
+xmltarget:powerpc-isa205-ppr-dscr-vsx64l.xml
+expedite:r1,pc
+64:r0
+64:r1
+64:r2
+64:r3
+64:r4
+64:r5
+64:r6
+64:r7
+64:r8
+64:r9
+64:r10
+64:r11
+64:r12
+64:r13
+64:r14
+64:r15
+64:r16
+64:r17
+64:r18
+64:r19
+64:r20
+64:r21
+64:r22
+64:r23
+64:r24
+64:r25
+64:r26
+64:r27
+64:r28
+64:r29
+64:r30
+64:r31
+64:f0
+64:f1
+64:f2
+64:f3
+64:f4
+64:f5
+64:f6
+64:f7
+64:f8
+64:f9
+64:f10
+64:f11
+64:f12
+64:f13
+64:f14
+64:f15
+64:f16
+64:f17
+64:f18
+64:f19
+64:f20
+64:f21
+64:f22
+64:f23
+64:f24
+64:f25
+64:f26
+64:f27
+64:f28
+64:f29
+64:f30
+64:f31
+64:pc
+64:msr
+32:cr
+64:lr
+64:ctr
+32:xer
+64:fpscr
+64:orig_r3
+64:trap
+128:vr0
+128:vr1
+128:vr2
+128:vr3
+128:vr4
+128:vr5
+128:vr6
+128:vr7
+128:vr8
+128:vr9
+128:vr10
+128:vr11
+128:vr12
+128:vr13
+128:vr14
+128:vr15
+128:vr16
+128:vr17
+128:vr18
+128:vr19
+128:vr20
+128:vr21
+128:vr22
+128:vr23
+128:vr24
+128:vr25
+128:vr26
+128:vr27
+128:vr28
+128:vr29
+128:vr30
+128:vr31
+32:vscr
+32:vrsave
+64:vs0h
+64:vs1h
+64:vs2h
+64:vs3h
+64:vs4h
+64:vs5h
+64:vs6h
+64:vs7h
+64:vs8h
+64:vs9h
+64:vs10h
+64:vs11h
+64:vs12h
+64:vs13h
+64:vs14h
+64:vs15h
+64:vs16h
+64:vs17h
+64:vs18h
+64:vs19h
+64:vs20h
+64:vs21h
+64:vs22h
+64:vs23h
+64:vs24h
+64:vs25h
+64:vs26h
+64:vs27h
+64:vs28h
+64:vs29h
+64:vs30h
+64:vs31h
+64:ppr
+64:dscr
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index f9683887cc..294d6ea702 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -5817,7 +5817,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
enum powerpc_elf_abi elf_abi = POWERPC_ELF_AUTO;
int have_fpu = 0, have_spe = 0, have_mq = 0, have_altivec = 0;
- int have_dfp = 0, have_vsx = 0;
+ int have_dfp = 0, have_vsx = 0, have_ppr = 0, have_dscr = 0;
int tdesc_wordsize = -1;
const struct target_desc *tdesc = info.target_desc;
struct tdesc_arch_data *tdesc_data = NULL;
@@ -6100,6 +6100,44 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
}
else
have_spe = 0;
+
+ /* Program Priority Register. */
+ feature = tdesc_find_feature (tdesc,
+ "org.gnu.gdb.power.ppr");
+ if (feature != NULL)
+ {
+ valid_p = 1;
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ PPC_PPR_REGNUM, "ppr");
+
+ if (!valid_p)
+ {
+ tdesc_data_cleanup (tdesc_data);
+ return NULL;
+ }
+ have_ppr = 1;
+ }
+ else
+ have_ppr = 0;
+
+ /* Data Stream Control Register. */
+ feature = tdesc_find_feature (tdesc,
+ "org.gnu.gdb.power.dscr");
+ if (feature != NULL)
+ {
+ valid_p = 1;
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ PPC_DSCR_REGNUM, "dscr");
+
+ if (!valid_p)
+ {
+ tdesc_data_cleanup (tdesc_data);
+ return NULL;
+ }
+ have_dscr = 1;
+ }
+ else
+ have_dscr = 0;
}
/* If we have a 64-bit binary on a 32-bit target, complain. Also
@@ -6294,6 +6332,8 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
+ tdep->ppc_ppr_regnum = have_ppr ? PPC_PPR_REGNUM : -1;
+ tdep->ppc_dscr_regnum = have_dscr ? PPC_DSCR_REGNUM : -1;
set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
--
2.13.6
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 05/17] [PowerPC] Add support for PPR and DSCR
2018-07-13 13:53 ` [PATCH 05/17] [PowerPC] Add support for PPR and DSCR Pedro Franco de Carvalho
@ 2018-07-13 15:23 ` Ulrich Weigand
0 siblings, 0 replies; 38+ messages in thread
From: Ulrich Weigand @ 2018-07-13 15:23 UTC (permalink / raw)
To: Pedro Franco de Carvalho; +Cc: gdb-patches, edjunior
Pedro Franco de Carvalho wrote:
> The gdbserver implementation comes in the next patch. However, because
> powerpc target description declarations are common to gdb and
> gdbserver, the .dat files and gdbserver/configure.srv are altered
> here, in order to avoid breaking the build at the commit corresponding
> to this patch.
I guess it would make sense to combine those (together with the tests
and the record/replay support) into a single commit then.
> gdb/ChangeLog:
> YYYY-MM-DD Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
> Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
>
> * arch/ppc-linux-tdesc.h (tdesc_powerpc_isa205_ppr_dscr_vsx32l)
> (tdesc_powerpc_isa205_ppr_dscr_vsx64l): Declare.
> * arch/ppc-linux-common.h (PPC_LINUX_SIZEOF_PPRREGSET)
> (PPC_LINUX_SIZEOF_DSCRREGSET): Define.
> (struct ppc_linux_features) <ppr_dscr>: New field.
> (ppc_linux_no_features): Add initializer for ppr_dscr field.
> * arch/ppc-linux-common.c (ppc_linux_match_description): Return
> new tdescs.
> * nat/ppc-linux.h (PPC_FEATURE2_DSCR, NT_PPC_PPR, NT_PPC_DSCR):
> Define if not already defined.
> * features/Makefile (WHICH): Add
> rs6000/powerpc-isa205-ppr-dscr-vsx32l and
> rs6000/powerpc-isa205-ppr-dscr-vsx64l.
> (XMLTOC): Add rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml and
> rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml.
> * features/rs6000/power-dscr.xml: New file.
> * features/rs6000/power-ppr.xml: New file.
> * features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml: New file.
> * features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml: New file.
> * features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c: Generate.
> * features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c: Generate.
> * regformats/rs6000/powerpc-isa205-ppr-dscr-vsx32l.dat: Generate.
> * regformats/rs6000/powerpc-isa205-ppr-dscr-vsx64l.dat: Generate.
> * ppc-linux-nat.c: Include <sys/uio.h>.
> (fetch_regset, store_regset, check_regset): New functions.
> (fetch_register, fetch_ppc_registers): Call fetch_regset with DSCR
> and PPR regsets.
> (store_register, store_ppc_registers): Call store_regset with DSCR
> and PPR regsets..
> (ppc_linux_get_hwcap2): New function.
> (ppc_linux_nat_target::read_description): Call
> ppc_linux_get_hwcap2 and check_regset, set ppr_dscr field in the
> features struct if needed.
> * ppc-linux-tdep.c: Include
> features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c and
> features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c.
> (ppc32_regmap_ppr, ppc32_regmap_dscr, ppc32_linux_pprregset)
> (ppc32_linux_dscrregset): New globals.
> (ppc_linux_iterate_over_regset_sections): Call back with the ppr
> and dscr regsets.
> (ppc_linux_core_read_description): Check if the ppr and dscr
> sections are present and set ppr_dscr in the features struct.
> (_initialize_ppc_linux_tdep): Call
> initialize_tdesc_powerpc_isa205_ppr_dscr_vsx32l and
> initialize_tdesc_powerpc_isa205_ppr_dscr_vsx64l.
> * ppc-linux-tdep.h (ppc32_linux_pprregset)
> (ppc32_linux_dscrregset): Declare.
> * ppc-tdep.h (struct gdbarch_tdep) <ppc_ppr_regnum>: New field.
> <ppc_dscr_regnum>: New field.
> (enum) <PPC_PPR_REGNUM, PPC_DSCR_REGNUM>: New enum values.
> * rs6000-tdep.c (rs6000_gdbarch_init): Look for and validate ppr
> and dscr features.
>
> gdb/gdbserver/ChangeLog:
> YYYY-MM-DD Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
> Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
>
> * configure.srv (ipa_ppc_linux_regobj): Add
> powerpc-isa205-ppr-dscr-vsx32l-ipa.o and
> powerpc-isa205-ppr-dscr-vsx64l-ipa.o.
> (powerpc*-*-linux*): Add powerpc-isa205-ppr-dscr-vsx32l.o and
> powerpc-isa205-ppr-dscr-vsx64l.o to srv_regobj, add
> rs6000/power-dscr.xml, rs6000/power-ppr.xml,
> rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml and
> rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml to srv_xmlfiles.
This is OK.
Thanks,
Ulrich
--
Dr. Ulrich Weigand
GNU/Linux compilers and toolchain
Ulrich.Weigand@de.ibm.com
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 09/17] [PowerPC] Add support for TAR
2018-07-13 13:53 [PATCH 00/17] GDB support for more powerpc registers on linux Pedro Franco de Carvalho
2018-07-13 13:53 ` [PATCH 16/17] [PowerPC] Add support for EBB and PMU registers Pedro Franco de Carvalho
2018-07-13 13:53 ` [PATCH 05/17] [PowerPC] Add support for PPR and DSCR Pedro Franco de Carvalho
@ 2018-07-13 13:53 ` Pedro Franco de Carvalho
2018-07-13 15:30 ` Ulrich Weigand
2018-07-13 13:53 ` [PATCH 01/17] [PowerPC] Simplify rs6000_pseudo_register_reggroup_p Pedro Franco de Carvalho
` (13 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 13:53 UTC (permalink / raw)
To: gdb-patches; +Cc: uweigand, edjunior
From: Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
This patch adds support for the Target Address Register for powerpc
linux native and core file targets.
Like for the PPR and DSCR patch, the .dat files and configure.srv
changes are included here to avoid breaking the build at this point.
gdb/ChangeLog:
YYYY-MM-DD Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* arch/ppc-linux-tdesc.h (tdesc_powerpc_isa207_vsx32l)
(tdesc_powerpc_isa207_vsx64l): Declare.
* arch/ppc-linux-common.h (PPC_LINUX_SIZEOF_TARREGSET): Define.
(struct ppc_linux_features) <isa207>: New field.
(ppc_linux_no_features): Add initializer for isa207 field.
* arch/ppc-linux-common.c (ppc_linux_match_description): Return
new tdescs.
* nat/ppc-linux.h (PPC_FEATURE2_ARCH_2_07, PPC_FEATURE2_TAR)
(NT_PPC_TAR): Define if not already defined.
* features/Makefile (WHICH): Add rs6000/powerpc-isa207-vsx32l and
rs6000/powerpc-isa207-vsx64l.
(XMLTOC): Add rs6000/powerpc-isa207-vsx32l.xml and
rs6000/powerpc-isa207-vsx64l.xml.
* features/rs6000/power-tar.xml: New file.
* features/rs6000/powerpc-isa207-vsx32l.xml: New file.
* features/rs6000/powerpc-isa207-vsx64l.xml: New file.
* features/rs6000/powerpc-isa207-vsx32l.c: Generate.
* features/rs6000/powerpc-isa207-vsx64l.c: Generate.
* regformats/rs6000/powerpc-isa207-vsx32l.dat: Generate.
* regformats/rs6000/powerpc-isa207-vsx64l.dat: Generate.
* ppc-linux-nat.c (fetch_register, fetch_ppc_registers): Call
fetch_regset with the TAR regset.
(store_register, store_ppc_registers): Call store_regset with the
TAR regset.
(ppc_linux_nat_target::read_description): Set isa207 field in the
features struct if needed.
* ppc-linux-tdep.c: Include
features/rs6000/powerpc-isa207-vsx32l.c and
features/rs6000/powerpc-isa207-vsx64l.c.
(ppc32_regmap_tar, ppc32_linux_tarregset): New globals.
(ppc_linux_iterate_over_regset_sections): Call back with the tar
regset.
(ppc_linux_core_read_description): Check if the tar section is
present and set isa207 in the features struct.
(_initialize_ppc_linux_tdep): Call
initialize_tdesc_powerpc_isa207_vsx32l and
initialize_tdesc_powerpc_isa207_vsx64l.
* ppc-linux-tdep.h (ppc32_linux_tarregset): Declare.
* ppc-tdep.h (gdbarch_tdep) <ppc_tar_regnum>: New field.
(enum) <PPC_TAR_REGNUM>: New enum value.
* rs6000-tdep.c (rs6000_gdbarch_init): Look for and validate tar
feature.
gdb/gdbserver/ChangeLog:
YYYY-MM-DD Pedro Franco de Carvalho <pedromfc@linux.vnet.ibm.com>
* configure.srv (ipa_ppc_linux_regobj): Add
powerpc-isa207-vsx64l-ipa.o and powerpc-isa207-vsx32l-ipa.o.
(powerpc*-*-linux*): Add powerpc-isa207-vsx32l.o and
powerpc-isa207-vsx64l.o to srv_regobj, add rs6000/power-tar.xml,
rs6000/powerpc-isa207-vsx32l.xml, and
rs6000/powerpc-isa207-vsx64l.xml to srv_xmlfiles.
---
gdb/arch/ppc-linux-common.c | 6 +-
gdb/arch/ppc-linux-common.h | 3 +
gdb/arch/ppc-linux-tdesc.h | 2 +
gdb/features/Makefile | 3 +
gdb/features/rs6000/power-tar.xml | 12 ++
gdb/features/rs6000/powerpc-isa207-vsx32l.c | 203 ++++++++++++++++++++++++
gdb/features/rs6000/powerpc-isa207-vsx32l.xml | 19 +++
gdb/features/rs6000/powerpc-isa207-vsx64l.c | 203 ++++++++++++++++++++++++
gdb/features/rs6000/powerpc-isa207-vsx64l.xml | 19 +++
gdb/gdbserver/configure.srv | 7 +-
gdb/nat/ppc-linux.h | 11 ++
gdb/ppc-linux-nat.c | 34 +++-
gdb/ppc-linux-tdep.c | 28 +++-
gdb/ppc-linux-tdep.h | 1 +
gdb/ppc-tdep.h | 4 +
gdb/regformats/rs6000/powerpc-isa207-vsx32l.dat | 147 +++++++++++++++++
gdb/regformats/rs6000/powerpc-isa207-vsx64l.dat | 147 +++++++++++++++++
gdb/rs6000-tdep.c | 21 +++
18 files changed, 865 insertions(+), 5 deletions(-)
create mode 100644 gdb/features/rs6000/power-tar.xml
create mode 100644 gdb/features/rs6000/powerpc-isa207-vsx32l.c
create mode 100644 gdb/features/rs6000/powerpc-isa207-vsx32l.xml
create mode 100644 gdb/features/rs6000/powerpc-isa207-vsx64l.c
create mode 100644 gdb/features/rs6000/powerpc-isa207-vsx64l.xml
create mode 100644 gdb/regformats/rs6000/powerpc-isa207-vsx32l.dat
create mode 100644 gdb/regformats/rs6000/powerpc-isa207-vsx64l.dat
diff --git a/gdb/arch/ppc-linux-common.c b/gdb/arch/ppc-linux-common.c
index 7cf08eb7da..b8a7cdb2ad 100644
--- a/gdb/arch/ppc-linux-common.c
+++ b/gdb/arch/ppc-linux-common.c
@@ -53,7 +53,8 @@ ppc_linux_match_description (struct ppc_linux_features features)
if (features.cell)
tdesc = tdesc_powerpc_cell64l;
else if (features.vsx)
- tdesc = (features.ppr_dscr? tdesc_powerpc_isa205_ppr_dscr_vsx64l
+ tdesc = (features.isa207? tdesc_powerpc_isa207_vsx64l
+ : features.ppr_dscr? tdesc_powerpc_isa205_ppr_dscr_vsx64l
: features.isa205? tdesc_powerpc_isa205_vsx64l
: tdesc_powerpc_vsx64l);
else if (features.altivec)
@@ -70,7 +71,8 @@ ppc_linux_match_description (struct ppc_linux_features features)
if (features.cell)
tdesc = tdesc_powerpc_cell32l;
else if (features.vsx)
- tdesc = (features.ppr_dscr? tdesc_powerpc_isa205_ppr_dscr_vsx32l
+ tdesc = (features.isa207? tdesc_powerpc_isa207_vsx32l
+ : features.ppr_dscr? tdesc_powerpc_isa205_ppr_dscr_vsx32l
: features.isa205? tdesc_powerpc_isa205_vsx32l
: tdesc_powerpc_vsx32l);
else if (features.altivec)
diff --git a/gdb/arch/ppc-linux-common.h b/gdb/arch/ppc-linux-common.h
index 666954e765..f0e4a4221f 100644
--- a/gdb/arch/ppc-linux-common.h
+++ b/gdb/arch/ppc-linux-common.h
@@ -32,6 +32,7 @@ struct target_desc;
#define PPC_LINUX_SIZEOF_VSXREGSET 256
#define PPC_LINUX_SIZEOF_PPRREGSET 8
#define PPC_LINUX_SIZEOF_DSCRREGSET 8
+#define PPC_LINUX_SIZEOF_TARREGSET 8
/* Check if the hwcap auxv entry indicates that isa205 is supported. */
bool ppc_linux_has_isa205 (CORE_ADDR hwcap);
@@ -44,6 +45,7 @@ struct ppc_linux_features
bool vsx;
bool isa205;
bool ppr_dscr;
+ bool isa207;
bool cell;
};
@@ -55,6 +57,7 @@ const struct ppc_linux_features ppc_linux_no_features = {
false,
false,
false,
+ false,
};
/* Return a target description that matches FEATURES. */
diff --git a/gdb/arch/ppc-linux-tdesc.h b/gdb/arch/ppc-linux-tdesc.h
index 3b5a2286e0..9962879786 100644
--- a/gdb/arch/ppc-linux-tdesc.h
+++ b/gdb/arch/ppc-linux-tdesc.h
@@ -30,6 +30,7 @@ extern struct target_desc *tdesc_powerpc_isa205_32l;
extern struct target_desc *tdesc_powerpc_isa205_altivec32l;
extern struct target_desc *tdesc_powerpc_isa205_vsx32l;
extern struct target_desc *tdesc_powerpc_isa205_ppr_dscr_vsx32l;
+extern struct target_desc *tdesc_powerpc_isa207_vsx32l;
extern struct target_desc *tdesc_powerpc_e500l;
extern struct target_desc *tdesc_powerpc_64l;
@@ -40,5 +41,6 @@ extern struct target_desc *tdesc_powerpc_isa205_64l;
extern struct target_desc *tdesc_powerpc_isa205_altivec64l;
extern struct target_desc *tdesc_powerpc_isa205_vsx64l;
extern struct target_desc *tdesc_powerpc_isa205_ppr_dscr_vsx64l;
+extern struct target_desc *tdesc_powerpc_isa207_vsx64l;
#endif /* ARCH_PPC_LINUX_TDESC_H */
diff --git a/gdb/features/Makefile b/gdb/features/Makefile
index 9755646e2e..6eaa7db05f 100644
--- a/gdb/features/Makefile
+++ b/gdb/features/Makefile
@@ -75,6 +75,7 @@ WHICH = aarch64 \
rs6000/powerpc-isa205-vsx32l rs6000/powerpc-isa205-vsx64l \
rs6000/powerpc-isa205-ppr-dscr-vsx32l \
rs6000/powerpc-isa205-ppr-dscr-vsx64l \
+ rs6000/powerpc-isa207-vsx32l rs6000/powerpc-isa207-vsx64l \
s390-linux32 s390-linux64 s390x-linux64 \
s390-linux32v1 s390-linux64v1 s390x-linux64v1 \
s390-linux32v2 s390-linux64v2 s390x-linux64v2 \
@@ -171,6 +172,8 @@ XMLTOC = \
rs6000/powerpc-isa205-vsx64l.xml \
rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml \
rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml \
+ rs6000/powerpc-isa207-vsx32l.xml \
+ rs6000/powerpc-isa207-vsx64l.xml \
rs6000/powerpc-vsx32.xml \
rs6000/powerpc-vsx32l.xml \
rs6000/powerpc-vsx64.xml \
diff --git a/gdb/features/rs6000/power-tar.xml b/gdb/features/rs6000/power-tar.xml
new file mode 100644
index 0000000000..7861ccea18
--- /dev/null
+++ b/gdb/features/rs6000/power-tar.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- POWER8 Target Address Register. -->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.power.tar">
+ <reg name="tar" bitsize="64" type="uint64"/>
+</feature>
diff --git a/gdb/features/rs6000/powerpc-isa207-vsx32l.c b/gdb/features/rs6000/powerpc-isa207-vsx32l.c
new file mode 100644
index 0000000000..73c7a01077
--- /dev/null
+++ b/gdb/features/rs6000/powerpc-isa207-vsx32l.c
@@ -0,0 +1,203 @@
+/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
+ Original: powerpc-isa207-vsx32l.xml */
+
+#include "defs.h"
+#include "osabi.h"
+#include "target-descriptions.h"
+
+struct target_desc *tdesc_powerpc_isa207_vsx32l;
+static void
+initialize_tdesc_powerpc_isa207_vsx32l (void)
+{
+ struct target_desc *result = allocate_target_description ();
+ set_tdesc_architecture (result, bfd_scan_arch ("powerpc:common"));
+
+ struct tdesc_feature *feature;
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.core");
+ tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r13", 13, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r14", 14, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r15", 15, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r16", 16, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r17", 17, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r18", 18, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r19", 19, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r20", 20, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r21", 21, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r22", 22, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r23", 23, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r24", 24, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r25", 25, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r26", 26, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r27", 27, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r28", 28, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "pc", 64, 1, NULL, 32, "code_ptr");
+ tdesc_create_reg (feature, "msr", 65, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr", 66, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "lr", 67, 1, NULL, 32, "code_ptr");
+ tdesc_create_reg (feature, "ctr", 68, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "xer", 69, 1, NULL, 32, "uint32");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.fpu");
+ tdesc_create_reg (feature, "f0", 32, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f1", 33, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f2", 34, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f3", 35, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f4", 36, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f5", 37, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f6", 38, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f7", 39, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f8", 40, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f9", 41, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f10", 42, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f11", 43, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f12", 44, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f13", 45, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f14", 46, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f15", 47, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f16", 48, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f17", 49, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f18", 50, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f19", 51, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f20", 52, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f21", 53, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f22", 54, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f23", 55, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f24", 56, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f25", 57, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f26", 58, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f27", 59, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f28", 60, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f29", 61, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f30", 62, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f31", 63, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "fpscr", 70, 1, "float", 64, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.linux");
+ tdesc_create_reg (feature, "orig_r3", 71, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "trap", 72, 1, NULL, 32, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.altivec");
+ tdesc_type *element_type;
+ element_type = tdesc_named_type (feature, "ieee_single");
+ tdesc_create_vector (feature, "v4f", element_type, 4);
+
+ element_type = tdesc_named_type (feature, "int32");
+ tdesc_create_vector (feature, "v4i32", element_type, 4);
+
+ element_type = tdesc_named_type (feature, "int16");
+ tdesc_create_vector (feature, "v8i16", element_type, 8);
+
+ element_type = tdesc_named_type (feature, "int8");
+ tdesc_create_vector (feature, "v16i8", element_type, 16);
+
+ tdesc_type_with_fields *type_with_fields;
+ type_with_fields = tdesc_create_union (feature, "vec128");
+ tdesc_type *field_type;
+ field_type = tdesc_named_type (feature, "uint128");
+ tdesc_add_field (type_with_fields, "uint128", field_type);
+ field_type = tdesc_named_type (feature, "v4f");
+ tdesc_add_field (type_with_fields, "v4_float", field_type);
+ field_type = tdesc_named_type (feature, "v4i32");
+ tdesc_add_field (type_with_fields, "v4_int32", field_type);
+ field_type = tdesc_named_type (feature, "v8i16");
+ tdesc_add_field (type_with_fields, "v8_int16", field_type);
+ field_type = tdesc_named_type (feature, "v16i8");
+ tdesc_add_field (type_with_fields, "v16_int8", field_type);
+
+ tdesc_create_reg (feature, "vr0", 73, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr1", 74, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr2", 75, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr3", 76, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr4", 77, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr5", 78, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr6", 79, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr7", 80, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr8", 81, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr9", 82, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr10", 83, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr11", 84, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr12", 85, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr13", 86, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr14", 87, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr15", 88, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr16", 89, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr17", 90, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr18", 91, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr19", 92, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr20", 93, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr21", 94, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr22", 95, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr23", 96, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr24", 97, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr25", 98, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr26", 99, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr27", 100, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr28", 101, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr29", 102, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr30", 103, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr31", 104, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vscr", 105, 1, "vector", 32, "int");
+ tdesc_create_reg (feature, "vrsave", 106, 1, "vector", 32, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.vsx");
+ tdesc_create_reg (feature, "vs0h", 107, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs1h", 108, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs2h", 109, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs3h", 110, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs4h", 111, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs5h", 112, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs6h", 113, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs7h", 114, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs8h", 115, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs9h", 116, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs10h", 117, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs11h", 118, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs12h", 119, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs13h", 120, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs14h", 121, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs15h", 122, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs16h", 123, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs17h", 124, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs18h", 125, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs19h", 126, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs20h", 127, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs21h", 128, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs22h", 129, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs23h", 130, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs24h", 131, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs25h", 132, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs26h", 133, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs27h", 134, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs28h", 135, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs29h", 136, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs30h", 137, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs31h", 138, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.ppr");
+ tdesc_create_reg (feature, "ppr", 139, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.dscr");
+ tdesc_create_reg (feature, "dscr", 140, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.tar");
+ tdesc_create_reg (feature, "tar", 141, 1, NULL, 64, "uint64");
+
+ tdesc_powerpc_isa207_vsx32l = result;
+}
diff --git a/gdb/features/rs6000/powerpc-isa207-vsx32l.xml b/gdb/features/rs6000/powerpc-isa207-vsx32l.xml
new file mode 100644
index 0000000000..599e6a24a2
--- /dev/null
+++ b/gdb/features/rs6000/powerpc-isa207-vsx32l.xml
@@ -0,0 +1,19 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>powerpc:common</architecture>
+ <xi:include href="power-core.xml"/>
+ <xi:include href="power-fpu-isa205.xml"/>
+ <xi:include href="power-linux.xml"/>
+ <xi:include href="power-altivec.xml"/>
+ <xi:include href="power-vsx.xml"/>
+ <xi:include href="power-ppr.xml"/>
+ <xi:include href="power-dscr.xml"/>
+ <xi:include href="power-tar.xml"/>
+</target>
diff --git a/gdb/features/rs6000/powerpc-isa207-vsx64l.c b/gdb/features/rs6000/powerpc-isa207-vsx64l.c
new file mode 100644
index 0000000000..9c735522d2
--- /dev/null
+++ b/gdb/features/rs6000/powerpc-isa207-vsx64l.c
@@ -0,0 +1,203 @@
+/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
+ Original: powerpc-isa207-vsx64l.xml */
+
+#include "defs.h"
+#include "osabi.h"
+#include "target-descriptions.h"
+
+struct target_desc *tdesc_powerpc_isa207_vsx64l;
+static void
+initialize_tdesc_powerpc_isa207_vsx64l (void)
+{
+ struct target_desc *result = allocate_target_description ();
+ set_tdesc_architecture (result, bfd_scan_arch ("powerpc:common64"));
+
+ struct tdesc_feature *feature;
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.core");
+ tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "pc", 64, 1, NULL, 64, "code_ptr");
+ tdesc_create_reg (feature, "msr", 65, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr", 66, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "lr", 67, 1, NULL, 64, "code_ptr");
+ tdesc_create_reg (feature, "ctr", 68, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "xer", 69, 1, NULL, 32, "uint32");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.fpu");
+ tdesc_create_reg (feature, "f0", 32, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f1", 33, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f2", 34, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f3", 35, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f4", 36, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f5", 37, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f6", 38, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f7", 39, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f8", 40, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f9", 41, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f10", 42, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f11", 43, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f12", 44, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f13", 45, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f14", 46, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f15", 47, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f16", 48, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f17", 49, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f18", 50, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f19", 51, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f20", 52, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f21", 53, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f22", 54, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f23", 55, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f24", 56, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f25", 57, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f26", 58, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f27", 59, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f28", 60, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f29", 61, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f30", 62, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f31", 63, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "fpscr", 70, 1, "float", 64, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.linux");
+ tdesc_create_reg (feature, "orig_r3", 71, 1, NULL, 64, "int");
+ tdesc_create_reg (feature, "trap", 72, 1, NULL, 64, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.altivec");
+ tdesc_type *element_type;
+ element_type = tdesc_named_type (feature, "ieee_single");
+ tdesc_create_vector (feature, "v4f", element_type, 4);
+
+ element_type = tdesc_named_type (feature, "int32");
+ tdesc_create_vector (feature, "v4i32", element_type, 4);
+
+ element_type = tdesc_named_type (feature, "int16");
+ tdesc_create_vector (feature, "v8i16", element_type, 8);
+
+ element_type = tdesc_named_type (feature, "int8");
+ tdesc_create_vector (feature, "v16i8", element_type, 16);
+
+ tdesc_type_with_fields *type_with_fields;
+ type_with_fields = tdesc_create_union (feature, "vec128");
+ tdesc_type *field_type;
+ field_type = tdesc_named_type (feature, "uint128");
+ tdesc_add_field (type_with_fields, "uint128", field_type);
+ field_type = tdesc_named_type (feature, "v4f");
+ tdesc_add_field (type_with_fields, "v4_float", field_type);
+ field_type = tdesc_named_type (feature, "v4i32");
+ tdesc_add_field (type_with_fields, "v4_int32", field_type);
+ field_type = tdesc_named_type (feature, "v8i16");
+ tdesc_add_field (type_with_fields, "v8_int16", field_type);
+ field_type = tdesc_named_type (feature, "v16i8");
+ tdesc_add_field (type_with_fields, "v16_int8", field_type);
+
+ tdesc_create_reg (feature, "vr0", 73, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr1", 74, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr2", 75, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr3", 76, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr4", 77, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr5", 78, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr6", 79, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr7", 80, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr8", 81, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr9", 82, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr10", 83, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr11", 84, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr12", 85, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr13", 86, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr14", 87, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr15", 88, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr16", 89, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr17", 90, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr18", 91, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr19", 92, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr20", 93, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr21", 94, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr22", 95, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr23", 96, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr24", 97, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr25", 98, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr26", 99, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr27", 100, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr28", 101, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr29", 102, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr30", 103, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr31", 104, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vscr", 105, 1, "vector", 32, "int");
+ tdesc_create_reg (feature, "vrsave", 106, 1, "vector", 32, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.vsx");
+ tdesc_create_reg (feature, "vs0h", 107, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs1h", 108, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs2h", 109, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs3h", 110, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs4h", 111, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs5h", 112, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs6h", 113, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs7h", 114, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs8h", 115, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs9h", 116, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs10h", 117, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs11h", 118, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs12h", 119, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs13h", 120, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs14h", 121, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs15h", 122, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs16h", 123, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs17h", 124, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs18h", 125, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs19h", 126, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs20h", 127, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs21h", 128, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs22h", 129, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs23h", 130, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs24h", 131, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs25h", 132, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs26h", 133, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs27h", 134, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs28h", 135, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs29h", 136, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs30h", 137, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs31h", 138, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.ppr");
+ tdesc_create_reg (feature, "ppr", 139, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.dscr");
+ tdesc_create_reg (feature, "dscr", 140, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.tar");
+ tdesc_create_reg (feature, "tar", 141, 1, NULL, 64, "uint64");
+
+ tdesc_powerpc_isa207_vsx64l = result;
+}
diff --git a/gdb/features/rs6000/powerpc-isa207-vsx64l.xml b/gdb/features/rs6000/powerpc-isa207-vsx64l.xml
new file mode 100644
index 0000000000..42a23cc001
--- /dev/null
+++ b/gdb/features/rs6000/powerpc-isa207-vsx64l.xml
@@ -0,0 +1,19 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>powerpc:common64</architecture>
+ <xi:include href="power64-core.xml"/>
+ <xi:include href="power-fpu-isa205.xml"/>
+ <xi:include href="power64-linux.xml"/>
+ <xi:include href="power-altivec.xml"/>
+ <xi:include href="power-vsx.xml"/>
+ <xi:include href="power-ppr.xml"/>
+ <xi:include href="power-dscr.xml"/>
+ <xi:include href="power-tar.xml"/>
+</target>
diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
index eef13966f1..0cb50627aa 100644
--- a/gdb/gdbserver/configure.srv
+++ b/gdb/gdbserver/configure.srv
@@ -32,7 +32,7 @@ else
srv_amd64_linux_regobj=""
fi
-ipa_ppc_linux_regobj="powerpc-32l-ipa.o powerpc-altivec32l-ipa.o powerpc-cell32l-ipa.o powerpc-vsx32l-ipa.o powerpc-isa205-32l-ipa.o powerpc-isa205-altivec32l-ipa.o powerpc-isa205-vsx32l-ipa.o powerpc-isa205-ppr-dscr-vsx32l-ipa.o powerpc-e500l-ipa.o powerpc-64l-ipa.o powerpc-altivec64l-ipa.o powerpc-cell64l-ipa.o powerpc-vsx64l-ipa.o powerpc-isa205-64l-ipa.o powerpc-isa205-altivec64l-ipa.o powerpc-isa205-vsx64l-ipa.o powerpc-isa205-ppr-dscr-vsx64l-ipa.o"
+ipa_ppc_linux_regobj="powerpc-32l-ipa.o powerpc-altivec32l-ipa.o powerpc-cell32l-ipa.o powerpc-vsx32l-ipa.o powerpc-isa205-32l-ipa.o powerpc-isa205-altivec32l-ipa.o powerpc-isa205-vsx32l-ipa.o powerpc-isa205-ppr-dscr-vsx32l-ipa.o powerpc-isa207-vsx32l-ipa.o powerpc-e500l-ipa.o powerpc-64l-ipa.o powerpc-altivec64l-ipa.o powerpc-cell64l-ipa.o powerpc-vsx64l-ipa.o powerpc-isa205-64l-ipa.o powerpc-isa205-altivec64l-ipa.o powerpc-isa205-vsx64l-ipa.o powerpc-isa205-ppr-dscr-vsx64l-ipa.o powerpc-isa207-vsx64l-ipa.o"
# Linux object files. This is so we don't have to repeat
# these files over and over again.
@@ -218,6 +218,7 @@ case "${target}" in
srv_regobj="${srv_regobj} powerpc-isa205-altivec32l.o"
srv_regobj="${srv_regobj} powerpc-isa205-vsx32l.o"
srv_regobj="${srv_regobj} powerpc-isa205-ppr-dscr-vsx32l.o"
+ srv_regobj="${srv_regobj} powerpc-isa207-vsx32l.o"
srv_regobj="${srv_regobj} powerpc-e500l.o"
srv_regobj="${srv_regobj} powerpc-64l.o"
srv_regobj="${srv_regobj} powerpc-altivec64l.o"
@@ -227,6 +228,7 @@ case "${target}" in
srv_regobj="${srv_regobj} powerpc-isa205-altivec64l.o"
srv_regobj="${srv_regobj} powerpc-isa205-vsx64l.o"
srv_regobj="${srv_regobj} powerpc-isa205-ppr-dscr-vsx64l.o"
+ srv_regobj="${srv_regobj} powerpc-isa207-vsx64l.o"
srv_tgtobj="$srv_linux_obj linux-ppc-low.o ppc-linux.o"
srv_tgtobj="${srv_tgtobj} arch/ppc-linux-common.o"
srv_xmlfiles="rs6000/powerpc-32l.xml"
@@ -237,6 +239,7 @@ case "${target}" in
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-altivec32l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-vsx32l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml"
+ srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa207-vsx32l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-altivec.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-vsx.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-core.xml"
@@ -245,6 +248,7 @@ case "${target}" in
srv_xmlfiles="${srv_xmlfiles} rs6000/power-fpu-isa205.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-dscr.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-ppr.xml"
+ srv_xmlfiles="${srv_xmlfiles} rs6000/power-tar.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-e500l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-spe.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-64l.xml"
@@ -255,6 +259,7 @@ case "${target}" in
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-altivec64l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-vsx64l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml"
+ srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa207-vsx64l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power64-core.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power64-linux.xml"
srv_linux_usrregs=yes
diff --git a/gdb/nat/ppc-linux.h b/gdb/nat/ppc-linux.h
index c2b8b0e80c..913a9e0bd8 100644
--- a/gdb/nat/ppc-linux.h
+++ b/gdb/nat/ppc-linux.h
@@ -54,6 +54,12 @@
#ifndef PPC_FEATURE2_DSCR
#define PPC_FEATURE2_DSCR 0x20000000
#endif
+#ifndef PPC_FEATURE2_ARCH_2_07
+#define PPC_FEATURE2_ARCH_2_07 0x80000000
+#endif
+#ifndef PPC_FEATURE2_TAR
+#define PPC_FEATURE2_TAR 0x04000000
+#endif
/* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
configure time check. Some older glibc's (for instance 2.2.1)
@@ -85,6 +91,11 @@
#define PTRACE_SETEVRREGS 21
#endif
+/* Target Address Register. */
+#ifndef NT_PPC_TAR
+#define NT_PPC_TAR 0x103
+#endif
+
/* Program Priority Register. */
#ifndef NT_PPC_PPR
#define NT_PPC_PPR 0x104
diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c
index c560f88c7d..390df17c10 100644
--- a/gdb/ppc-linux-nat.c
+++ b/gdb/ppc-linux-nat.c
@@ -658,6 +658,15 @@ fetch_register (struct regcache *regcache, int tid, int regno)
&ppc32_linux_pprregset);
return;
}
+ else if (regno == PPC_TAR_REGNUM)
+ {
+ gdb_assert (tdep->ppc_tar_regnum != -1);
+
+ fetch_regset (regcache, tid, NT_PPC_TAR,
+ PPC_LINUX_SIZEOF_TARREGSET,
+ &ppc32_linux_tarregset);
+ return;
+ }
if (regaddr == -1)
{
@@ -862,6 +871,10 @@ fetch_ppc_registers (struct regcache *regcache, int tid)
fetch_regset (regcache, tid, NT_PPC_DSCR,
PPC_LINUX_SIZEOF_DSCRREGSET,
&ppc32_linux_dscrregset);
+ if (tdep->ppc_tar_regnum != -1)
+ fetch_regset (regcache, tid, NT_PPC_TAR,
+ PPC_LINUX_SIZEOF_TARREGSET,
+ &ppc32_linux_tarregset);
}
/* Fetch registers from the child process. Fetch all registers if
@@ -1060,6 +1073,15 @@ store_register (const struct regcache *regcache, int tid, int regno)
&ppc32_linux_pprregset);
return;
}
+ else if (regno == PPC_TAR_REGNUM)
+ {
+ gdb_assert (tdep->ppc_tar_regnum != -1);
+
+ store_regset (regcache, tid, regno, NT_PPC_TAR,
+ PPC_LINUX_SIZEOF_TARREGSET,
+ &ppc32_linux_tarregset);
+ return;
+ }
if (regaddr == -1)
return;
@@ -1282,6 +1304,10 @@ store_ppc_registers (const struct regcache *regcache, int tid)
store_regset (regcache, tid, -1, NT_PPC_DSCR,
PPC_LINUX_SIZEOF_DSCRREGSET,
&ppc32_linux_dscrregset);
+ if (tdep->ppc_tar_regnum != -1)
+ store_regset (regcache, tid, -1, NT_PPC_TAR,
+ PPC_LINUX_SIZEOF_TARREGSET,
+ &ppc32_linux_tarregset);
}
/* Fetch the AT_HWCAP entry from the aux vector. */
@@ -2408,7 +2434,13 @@ ppc_linux_nat_target::read_description ()
if ((hwcap2 & PPC_FEATURE2_DSCR)
&& check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET)
&& check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET))
- features.ppr_dscr = true;
+ {
+ features.ppr_dscr = true;
+ if ((hwcap2 & PPC_FEATURE2_ARCH_2_07)
+ && (hwcap2 & PPC_FEATURE2_TAR)
+ && check_regset (tid, NT_PPC_TAR, PPC_LINUX_SIZEOF_TARREGSET))
+ features.isa207 = true;
+ }
return ppc_linux_match_description (features);
}
diff --git a/gdb/ppc-linux-tdep.c b/gdb/ppc-linux-tdep.c
index 7dac5d22b9..9d952c3388 100644
--- a/gdb/ppc-linux-tdep.c
+++ b/gdb/ppc-linux-tdep.c
@@ -72,6 +72,7 @@
#include "features/rs6000/powerpc-isa205-altivec32l.c"
#include "features/rs6000/powerpc-isa205-vsx32l.c"
#include "features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c"
+#include "features/rs6000/powerpc-isa207-vsx32l.c"
#include "features/rs6000/powerpc-64l.c"
#include "features/rs6000/powerpc-altivec64l.c"
#include "features/rs6000/powerpc-cell64l.c"
@@ -80,6 +81,7 @@
#include "features/rs6000/powerpc-isa205-altivec64l.c"
#include "features/rs6000/powerpc-isa205-vsx64l.c"
#include "features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c"
+#include "features/rs6000/powerpc-isa207-vsx64l.c"
#include "features/rs6000/powerpc-e500l.c"
/* Shared library operations for PowerPC-Linux. */
@@ -517,6 +519,12 @@ static const struct regcache_map_entry ppc32_regmap_dscr[] =
{ 0 }
};
+static const struct regcache_map_entry ppc32_regmap_tar[] =
+ {
+ { 1, PPC_TAR_REGNUM, 8 },
+ { 0 }
+ };
+
static const struct regset ppc32_linux_gregset = {
&ppc32_linux_reg_offsets,
ppc_linux_supply_gregset,
@@ -591,6 +599,12 @@ const struct regset ppc32_linux_dscrregset = {
regcache_collect_regset
};
+const struct regset ppc32_linux_tarregset = {
+ ppc32_regmap_tar,
+ regcache_supply_regset,
+ regcache_collect_regset
+};
+
const struct regset *
ppc_linux_gregset (int wordsize)
{
@@ -631,6 +645,7 @@ ppc_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
int have_vsx = tdep->ppc_vsr0_upper_regnum != -1;
int have_ppr = tdep->ppc_ppr_regnum != -1;
int have_dscr = tdep->ppc_dscr_regnum != -1;
+ int have_tar = tdep->ppc_tar_regnum != -1;
if (tdep->wordsize == 4)
cb (".reg", 48 * 4, &ppc32_linux_gregset, NULL, cb_data);
@@ -658,6 +673,10 @@ ppc_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
cb (".reg-ppc-dscr", PPC_LINUX_SIZEOF_DSCRREGSET,
&ppc32_linux_dscrregset, "Data Stream Control Register",
cb_data);
+
+ if (have_tar)
+ cb (".reg-ppc-tar", PPC_LINUX_SIZEOF_TARREGSET,
+ &ppc32_linux_tarregset, "Target Address Register", cb_data);
}
static void
@@ -1072,6 +1091,7 @@ ppc_linux_core_read_description (struct gdbarch *gdbarch,
asection *section = bfd_get_section_by_name (abfd, ".reg");
asection *ppr = bfd_get_section_by_name (abfd, ".reg-ppc-ppr");
asection *dscr = bfd_get_section_by_name (abfd, ".reg-ppc-dscr");
+ asection *tar = bfd_get_section_by_name (abfd, ".reg-ppc-tar");
if (! section)
return NULL;
@@ -1105,7 +1125,11 @@ ppc_linux_core_read_description (struct gdbarch *gdbarch,
features.isa205 = ppc_linux_has_isa205 (hwcap);
if (ppr && dscr)
- features.ppr_dscr = true;
+ {
+ features.ppr_dscr = true;
+ if (tar)
+ features.isa207 = true;
+ }
return ppc_linux_match_description (features);
}
@@ -1981,6 +2005,7 @@ _initialize_ppc_linux_tdep (void)
initialize_tdesc_powerpc_isa205_altivec32l ();
initialize_tdesc_powerpc_isa205_vsx32l ();
initialize_tdesc_powerpc_isa205_ppr_dscr_vsx32l ();
+ initialize_tdesc_powerpc_isa207_vsx32l ();
initialize_tdesc_powerpc_64l ();
initialize_tdesc_powerpc_altivec64l ();
initialize_tdesc_powerpc_cell64l ();
@@ -1989,5 +2014,6 @@ _initialize_ppc_linux_tdep (void)
initialize_tdesc_powerpc_isa205_altivec64l ();
initialize_tdesc_powerpc_isa205_vsx64l ();
initialize_tdesc_powerpc_isa205_ppr_dscr_vsx64l ();
+ initialize_tdesc_powerpc_isa207_vsx64l ();
initialize_tdesc_powerpc_e500l ();
}
diff --git a/gdb/ppc-linux-tdep.h b/gdb/ppc-linux-tdep.h
index e8ae23137c..d6ddf69354 100644
--- a/gdb/ppc-linux-tdep.h
+++ b/gdb/ppc-linux-tdep.h
@@ -47,5 +47,6 @@ int ppc_linux_trap_reg_p (struct gdbarch *gdbarch);
/* Additional register sets, defined in ppc-linux-tdep.c. */
extern const struct regset ppc32_linux_pprregset;
extern const struct regset ppc32_linux_dscrregset;
+extern const struct regset ppc32_linux_tarregset;
#endif /* PPC_LINUX_TDEP_H */
diff --git a/gdb/ppc-tdep.h b/gdb/ppc-tdep.h
index 86b5a3645d..e2b968177e 100644
--- a/gdb/ppc-tdep.h
+++ b/gdb/ppc-tdep.h
@@ -259,6 +259,9 @@ struct gdbarch_tdep
/* Data Stream Control Register. */
int ppc_dscr_regnum;
+ /* Target Address Register. */
+ int ppc_tar_regnum;
+
/* Decimal 128 registers. */
int ppc_dl0_regnum; /* First Decimal128 argument register pair. */
@@ -317,6 +320,7 @@ enum {
PPC_VSR31_UPPER_REGNUM = 171,
PPC_PPR_REGNUM = 172,
PPC_DSCR_REGNUM = 173,
+ PPC_TAR_REGNUM = 174,
PPC_NUM_REGS
};
diff --git a/gdb/regformats/rs6000/powerpc-isa207-vsx32l.dat b/gdb/regformats/rs6000/powerpc-isa207-vsx32l.dat
new file mode 100644
index 0000000000..2b6e0a9c8d
--- /dev/null
+++ b/gdb/regformats/rs6000/powerpc-isa207-vsx32l.dat
@@ -0,0 +1,147 @@
+# THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi :set ro:
+# Generated from: rs6000/powerpc-isa207-vsx32l.xml
+name:powerpc_isa207_vsx32l
+xmltarget:powerpc-isa207-vsx32l.xml
+expedite:r1,pc
+32:r0
+32:r1
+32:r2
+32:r3
+32:r4
+32:r5
+32:r6
+32:r7
+32:r8
+32:r9
+32:r10
+32:r11
+32:r12
+32:r13
+32:r14
+32:r15
+32:r16
+32:r17
+32:r18
+32:r19
+32:r20
+32:r21
+32:r22
+32:r23
+32:r24
+32:r25
+32:r26
+32:r27
+32:r28
+32:r29
+32:r30
+32:r31
+64:f0
+64:f1
+64:f2
+64:f3
+64:f4
+64:f5
+64:f6
+64:f7
+64:f8
+64:f9
+64:f10
+64:f11
+64:f12
+64:f13
+64:f14
+64:f15
+64:f16
+64:f17
+64:f18
+64:f19
+64:f20
+64:f21
+64:f22
+64:f23
+64:f24
+64:f25
+64:f26
+64:f27
+64:f28
+64:f29
+64:f30
+64:f31
+32:pc
+32:msr
+32:cr
+32:lr
+32:ctr
+32:xer
+64:fpscr
+32:orig_r3
+32:trap
+128:vr0
+128:vr1
+128:vr2
+128:vr3
+128:vr4
+128:vr5
+128:vr6
+128:vr7
+128:vr8
+128:vr9
+128:vr10
+128:vr11
+128:vr12
+128:vr13
+128:vr14
+128:vr15
+128:vr16
+128:vr17
+128:vr18
+128:vr19
+128:vr20
+128:vr21
+128:vr22
+128:vr23
+128:vr24
+128:vr25
+128:vr26
+128:vr27
+128:vr28
+128:vr29
+128:vr30
+128:vr31
+32:vscr
+32:vrsave
+64:vs0h
+64:vs1h
+64:vs2h
+64:vs3h
+64:vs4h
+64:vs5h
+64:vs6h
+64:vs7h
+64:vs8h
+64:vs9h
+64:vs10h
+64:vs11h
+64:vs12h
+64:vs13h
+64:vs14h
+64:vs15h
+64:vs16h
+64:vs17h
+64:vs18h
+64:vs19h
+64:vs20h
+64:vs21h
+64:vs22h
+64:vs23h
+64:vs24h
+64:vs25h
+64:vs26h
+64:vs27h
+64:vs28h
+64:vs29h
+64:vs30h
+64:vs31h
+64:ppr
+64:dscr
+64:tar
diff --git a/gdb/regformats/rs6000/powerpc-isa207-vsx64l.dat b/gdb/regformats/rs6000/powerpc-isa207-vsx64l.dat
new file mode 100644
index 0000000000..095bd7f2d3
--- /dev/null
+++ b/gdb/regformats/rs6000/powerpc-isa207-vsx64l.dat
@@ -0,0 +1,147 @@
+# THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi :set ro:
+# Generated from: rs6000/powerpc-isa207-vsx64l.xml
+name:powerpc_isa207_vsx64l
+xmltarget:powerpc-isa207-vsx64l.xml
+expedite:r1,pc
+64:r0
+64:r1
+64:r2
+64:r3
+64:r4
+64:r5
+64:r6
+64:r7
+64:r8
+64:r9
+64:r10
+64:r11
+64:r12
+64:r13
+64:r14
+64:r15
+64:r16
+64:r17
+64:r18
+64:r19
+64:r20
+64:r21
+64:r22
+64:r23
+64:r24
+64:r25
+64:r26
+64:r27
+64:r28
+64:r29
+64:r30
+64:r31
+64:f0
+64:f1
+64:f2
+64:f3
+64:f4
+64:f5
+64:f6
+64:f7
+64:f8
+64:f9
+64:f10
+64:f11
+64:f12
+64:f13
+64:f14
+64:f15
+64:f16
+64:f17
+64:f18
+64:f19
+64:f20
+64:f21
+64:f22
+64:f23
+64:f24
+64:f25
+64:f26
+64:f27
+64:f28
+64:f29
+64:f30
+64:f31
+64:pc
+64:msr
+32:cr
+64:lr
+64:ctr
+32:xer
+64:fpscr
+64:orig_r3
+64:trap
+128:vr0
+128:vr1
+128:vr2
+128:vr3
+128:vr4
+128:vr5
+128:vr6
+128:vr7
+128:vr8
+128:vr9
+128:vr10
+128:vr11
+128:vr12
+128:vr13
+128:vr14
+128:vr15
+128:vr16
+128:vr17
+128:vr18
+128:vr19
+128:vr20
+128:vr21
+128:vr22
+128:vr23
+128:vr24
+128:vr25
+128:vr26
+128:vr27
+128:vr28
+128:vr29
+128:vr30
+128:vr31
+32:vscr
+32:vrsave
+64:vs0h
+64:vs1h
+64:vs2h
+64:vs3h
+64:vs4h
+64:vs5h
+64:vs6h
+64:vs7h
+64:vs8h
+64:vs9h
+64:vs10h
+64:vs11h
+64:vs12h
+64:vs13h
+64:vs14h
+64:vs15h
+64:vs16h
+64:vs17h
+64:vs18h
+64:vs19h
+64:vs20h
+64:vs21h
+64:vs22h
+64:vs23h
+64:vs24h
+64:vs25h
+64:vs26h
+64:vs27h
+64:vs28h
+64:vs29h
+64:vs30h
+64:vs31h
+64:ppr
+64:dscr
+64:tar
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index f390370455..b7891a04b9 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -5837,6 +5837,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
enum powerpc_elf_abi elf_abi = POWERPC_ELF_AUTO;
int have_fpu = 0, have_spe = 0, have_mq = 0, have_altivec = 0;
int have_dfp = 0, have_vsx = 0, have_ppr = 0, have_dscr = 0;
+ int have_tar = 0;
int tdesc_wordsize = -1;
const struct target_desc *tdesc = info.target_desc;
struct tdesc_arch_data *tdesc_data = NULL;
@@ -6157,6 +6158,25 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
}
else
have_dscr = 0;
+
+ /* Target Address Register. */
+ feature = tdesc_find_feature (tdesc,
+ "org.gnu.gdb.power.tar");
+ if (feature != NULL)
+ {
+ valid_p = 1;
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ PPC_TAR_REGNUM, "tar");
+
+ if (!valid_p)
+ {
+ tdesc_data_cleanup (tdesc_data);
+ return NULL;
+ }
+ have_tar = 1;
+ }
+ else
+ have_tar = 0;
}
/* If we have a 64-bit binary on a 32-bit target, complain. Also
@@ -6353,6 +6373,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
tdep->ppc_ppr_regnum = have_ppr ? PPC_PPR_REGNUM : -1;
tdep->ppc_dscr_regnum = have_dscr ? PPC_DSCR_REGNUM : -1;
+ tdep->ppc_tar_regnum = have_tar ? PPC_TAR_REGNUM : -1;
set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
--
2.13.6
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 09/17] [PowerPC] Add support for TAR
2018-07-13 13:53 ` [PATCH 09/17] [PowerPC] Add support for TAR Pedro Franco de Carvalho
@ 2018-07-13 15:30 ` Ulrich Weigand
0 siblings, 0 replies; 38+ messages in thread
From: Ulrich Weigand @ 2018-07-13 15:30 UTC (permalink / raw)
To: Pedro Franco de Carvalho; +Cc: gdb-patches, edjunior
Pedro Franco de Carvalho wrote:
> Like for the PPR and DSCR patch, the .dat files and configure.srv
> changes are included here to avoid breaking the build at this point.
Same comment as before: it would be better to merge everything into
a single commit then.
> gdb/ChangeLog:
> YYYY-MM-DD Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
> Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
>
> * arch/ppc-linux-tdesc.h (tdesc_powerpc_isa207_vsx32l)
> (tdesc_powerpc_isa207_vsx64l): Declare.
> * arch/ppc-linux-common.h (PPC_LINUX_SIZEOF_TARREGSET): Define.
> (struct ppc_linux_features) <isa207>: New field.
> (ppc_linux_no_features): Add initializer for isa207 field.
> * arch/ppc-linux-common.c (ppc_linux_match_description): Return
> new tdescs.
> * nat/ppc-linux.h (PPC_FEATURE2_ARCH_2_07, PPC_FEATURE2_TAR)
> (NT_PPC_TAR): Define if not already defined.
> * features/Makefile (WHICH): Add rs6000/powerpc-isa207-vsx32l and
> rs6000/powerpc-isa207-vsx64l.
> (XMLTOC): Add rs6000/powerpc-isa207-vsx32l.xml and
> rs6000/powerpc-isa207-vsx64l.xml.
> * features/rs6000/power-tar.xml: New file.
> * features/rs6000/powerpc-isa207-vsx32l.xml: New file.
> * features/rs6000/powerpc-isa207-vsx64l.xml: New file.
> * features/rs6000/powerpc-isa207-vsx32l.c: Generate.
> * features/rs6000/powerpc-isa207-vsx64l.c: Generate.
> * regformats/rs6000/powerpc-isa207-vsx32l.dat: Generate.
> * regformats/rs6000/powerpc-isa207-vsx64l.dat: Generate.
> * ppc-linux-nat.c (fetch_register, fetch_ppc_registers): Call
> fetch_regset with the TAR regset.
> (store_register, store_ppc_registers): Call store_regset with the
> TAR regset.
> (ppc_linux_nat_target::read_description): Set isa207 field in the
> features struct if needed.
> * ppc-linux-tdep.c: Include
> features/rs6000/powerpc-isa207-vsx32l.c and
> features/rs6000/powerpc-isa207-vsx64l.c.
> (ppc32_regmap_tar, ppc32_linux_tarregset): New globals.
> (ppc_linux_iterate_over_regset_sections): Call back with the tar
> regset.
> (ppc_linux_core_read_description): Check if the tar section is
> present and set isa207 in the features struct.
> (_initialize_ppc_linux_tdep): Call
> initialize_tdesc_powerpc_isa207_vsx32l and
> initialize_tdesc_powerpc_isa207_vsx64l.
> * ppc-linux-tdep.h (ppc32_linux_tarregset): Declare.
> * ppc-tdep.h (gdbarch_tdep) <ppc_tar_regnum>: New field.
> (enum) <PPC_TAR_REGNUM>: New enum value.
> * rs6000-tdep.c (rs6000_gdbarch_init): Look for and validate tar
> feature.
>
> gdb/gdbserver/ChangeLog:
> YYYY-MM-DD Pedro Franco de Carvalho <pedromfc@linux.vnet.ibm.com>
>
> * configure.srv (ipa_ppc_linux_regobj): Add
> powerpc-isa207-vsx64l-ipa.o and powerpc-isa207-vsx32l-ipa.o.
> (powerpc*-*-linux*): Add powerpc-isa207-vsx32l.o and
> powerpc-isa207-vsx64l.o to srv_regobj, add rs6000/power-tar.xml,
> rs6000/powerpc-isa207-vsx32l.xml, and
> rs6000/powerpc-isa207-vsx64l.xml to srv_xmlfiles.
This is OK.
Thanks,
Ulrich
--
Dr. Ulrich Weigand
GNU/Linux compilers and toolchain
Ulrich.Weigand@de.ibm.com
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 01/17] [PowerPC] Simplify rs6000_pseudo_register_reggroup_p
2018-07-13 13:53 [PATCH 00/17] GDB support for more powerpc registers on linux Pedro Franco de Carvalho
` (2 preceding siblings ...)
2018-07-13 13:53 ` [PATCH 09/17] [PowerPC] Add support for TAR Pedro Franco de Carvalho
@ 2018-07-13 13:53 ` Pedro Franco de Carvalho
2018-07-13 15:17 ` Ulrich Weigand
2018-07-13 13:53 ` [PATCH 10/17] [PowerPC] Add record/replay support for TAR Pedro Franco de Carvalho
` (12 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 13:53 UTC (permalink / raw)
To: gdb-patches; +Cc: uweigand, edjunior
This patch changes rs6000_register_reggroup_p to use
default_register_reggroup_p when possible.
Group membership for SPE, VSX and EFP pseudoregisters can be detected
through their types in default_register_reggroup_p. DFP pseudoregs
still need special handling when checking membership to the float
group, because default_register_reggroup_p doesn't consider registers
with type code TYPE_CODE_DECFLOAT to be part of the float group.
gdb/ChangeLog:
YYYY-MM-DD Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* rs6000-tdep.c (rs6000_pseudo_register_reggroup_p): Call
default_register_reggroup_p.
---
gdb/rs6000-tdep.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index 4eeb62ac52..55ce22ea85 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -2423,12 +2423,12 @@ rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
|| IS_VSX_PSEUDOREG (tdep, regnum)
|| IS_EFP_PSEUDOREG (tdep, regnum));
- /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
- if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum))
- return group == all_reggroup || group == vector_reggroup;
- else
- /* PPC decimal128 or Extended FP pseudo-registers. */
- return group == all_reggroup || group == float_reggroup;
+ /* builtin_declong doesn't have TYPE_CODE_FLT, so it won't be
+ detected as a float register by default_register_reggroup_p. */
+ if (IS_DFP_PSEUDOREG (tdep, regnum) && group == float_reggroup)
+ return 1;
+
+ return default_register_reggroup_p (gdbarch, regnum, group);
}
/* The register format for RS/6000 floating point registers is always
--
2.13.6
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 01/17] [PowerPC] Simplify rs6000_pseudo_register_reggroup_p
2018-07-13 13:53 ` [PATCH 01/17] [PowerPC] Simplify rs6000_pseudo_register_reggroup_p Pedro Franco de Carvalho
@ 2018-07-13 15:17 ` Ulrich Weigand
0 siblings, 0 replies; 38+ messages in thread
From: Ulrich Weigand @ 2018-07-13 15:17 UTC (permalink / raw)
To: Pedro Franco de Carvalho; +Cc: gdb-patches, edjunior
Pedro Franco de Carvalho wrote:
> Group membership for SPE, VSX and EFP pseudoregisters can be detected
> through their types in default_register_reggroup_p. DFP pseudoregs
> still need special handling when checking membership to the float
> group, because default_register_reggroup_p doesn't consider registers
> with type code TYPE_CODE_DECFLOAT to be part of the float group.
>
> gdb/ChangeLog:
> YYYY-MM-DD Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
>
> * rs6000-tdep.c (rs6000_pseudo_register_reggroup_p): Call
> default_register_reggroup_p.
This is OK with me, but it might actually be even better to change
default_register_reggroup_p to consider TYPE_CODE_DECFLOAT registers
to be part o the float group as well.
Bye,
Ulrich
--
Dr. Ulrich Weigand
GNU/Linux compilers and toolchain
Ulrich.Weigand@de.ibm.com
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 10/17] [PowerPC] Add record/replay support for TAR
2018-07-13 13:53 [PATCH 00/17] GDB support for more powerpc registers on linux Pedro Franco de Carvalho
` (3 preceding siblings ...)
2018-07-13 13:53 ` [PATCH 01/17] [PowerPC] Simplify rs6000_pseudo_register_reggroup_p Pedro Franco de Carvalho
@ 2018-07-13 13:53 ` Pedro Franco de Carvalho
2018-07-13 15:31 ` Ulrich Weigand
2018-07-13 13:53 ` [PATCH 08/17] [PowerPC] Add tests for PPR and DSCR Pedro Franco de Carvalho
` (11 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 13:53 UTC (permalink / raw)
To: gdb-patches; +Cc: uweigand, edjunior
This patch changes ppc_process_record_op31 to handele moves to TAR.
gdb/ChangeLog:
2018-07-04 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* rs6000-tdep.c (ppc_process_record_op31): Record changes to TAR.
---
gdb/rs6000-tdep.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index b7891a04b9..134e9d0cbc 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -4669,6 +4669,10 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
case 256: /* VRSAVE */
record_full_arch_list_add_reg (regcache, tdep->ppc_vrsave_regnum);
return 0;
+ case 815: /* TAR */
+ if (tdep->ppc_tar_regnum >= 0)
+ record_full_arch_list_add_reg (regcache, tdep->ppc_tar_regnum);
+ return 0;
case 896:
case 898: /* PPR */
if (tdep->ppc_ppr_regnum >= 0)
--
2.13.6
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 08/17] [PowerPC] Add tests for PPR and DSCR
2018-07-13 13:53 [PATCH 00/17] GDB support for more powerpc registers on linux Pedro Franco de Carvalho
` (4 preceding siblings ...)
2018-07-13 13:53 ` [PATCH 10/17] [PowerPC] Add record/replay support for TAR Pedro Franco de Carvalho
@ 2018-07-13 13:53 ` Pedro Franco de Carvalho
2018-07-13 15:27 ` Ulrich Weigand
2018-07-13 13:53 ` [PATCH 12/17] [PowerPC] Add tests for TAR Pedro Franco de Carvalho
` (10 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 13:53 UTC (permalink / raw)
To: gdb-patches; +Cc: uweigand, edjunior
This patch adds a testcase for GDB access to the Program Priorty
Register and Data Stream Control Register.
gdb/ChangeLog:
YYYY-MM-DD Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.arch/powerpc-ppr-dscr.c: New file.
* gdb.arch/powerpc-ppr-dscr.exp: New file.
---
gdb/testsuite/gdb.arch/powerpc-ppr-dscr.c | 32 ++++++++
gdb/testsuite/gdb.arch/powerpc-ppr-dscr.exp | 110 ++++++++++++++++++++++++++++
2 files changed, 142 insertions(+)
create mode 100644 gdb/testsuite/gdb.arch/powerpc-ppr-dscr.c
create mode 100644 gdb/testsuite/gdb.arch/powerpc-ppr-dscr.exp
diff --git a/gdb/testsuite/gdb.arch/powerpc-ppr-dscr.c b/gdb/testsuite/gdb.arch/powerpc-ppr-dscr.c
new file mode 100644
index 0000000000..b53bf0d4d3
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/powerpc-ppr-dscr.c
@@ -0,0 +1,32 @@
+/* This test is part of GDB, the GNU debugger.
+
+ Copyright 2018 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+int main (void)
+{
+ /* Set Load Stream Disable bit in DSCR. */
+ unsigned long dscr = 0x20;
+
+ /* This is the non-privileged SPR number to access DSCR,
+ available since isa 207. */
+ asm volatile ("mtspr 3,%0" : : "r" (dscr));
+
+ /* Set PPR to low priority (010 in bits 11:13, or
+ 0x0008000000000000). */
+ asm volatile ("or 1,1,1");
+ asm volatile ("nop"); // marker
+ asm volatile ("nop");
+}
diff --git a/gdb/testsuite/gdb.arch/powerpc-ppr-dscr.exp b/gdb/testsuite/gdb.arch/powerpc-ppr-dscr.exp
new file mode 100644
index 0000000000..14cfa344bd
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/powerpc-ppr-dscr.exp
@@ -0,0 +1,110 @@
+# Copyright 2018 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+# This file is part of the gdb testsuite.
+
+# Test access to special purpose registers PPR and DSCR.
+
+if {![istarget "powerpc*-*-linux*"]} then {
+ verbose "Skipping PowerPC test for PPR and DSCR registers."
+ return
+}
+
+standard_testfile .c
+
+if {[build_executable "compile" $binfile $srcfile {debug}] == -1} {
+ return
+}
+
+proc check_register_access { regname } {
+ global gdb_prompt
+
+ set test "$regname register access"
+ gdb_test_multiple "info reg $regname" "$test" {
+ -re "Invalid register.*\r\n$gdb_prompt $" {
+ unsupported "$test"
+ return 0
+ }
+ -re "\r\n$regname.*\r\n$gdb_prompt $" {
+ pass "$test"
+ return 1
+ }
+ }
+ return 0
+}
+
+clean_restart $binfile
+
+if ![runto_main] {
+ return
+}
+
+if {![check_register_access "ppr"]} {
+ return
+}
+
+if {![check_register_access "dscr"]} {
+ return
+}
+
+# Do one pass to check if the instructions in our test programs are
+# available to this processor (e.g. mtspr 3, RS for accessing DSCR).
+proc ppr_dscr_available {} {
+ global gdb_prompt
+ global inferior_exited_re
+
+ set test "PPR/DSCR available to inferior"
+ gdb_test_multiple "continue" "" {
+ -re "Illegal instruction.*\r\n$gdb_prompt $" {
+ unsupported "$test"
+ return 0
+ }
+ -re "$inferior_exited_re normally.*$gdb_prompt $" {
+ pass "$test"
+ return 1
+ }
+ }
+ return 0
+}
+
+if {![ppr_dscr_available]} {
+ return
+}
+
+# Now do the actual test
+clean_restart $binfile
+
+runto_main
+
+set bp_line [gdb_get_line_number "marker"]
+
+gdb_breakpoint ${srcfile}:${bp_line}
+
+gdb_continue_to_breakpoint "continue to marker"
+
+# At the breakpoint the inferior should have set the
+# registers to these expected values.
+gdb_test "info reg dscr" "dscr.*0x0*20\[ \t\]+.*"
+gdb_test "info reg ppr" "ppr.*0x0*8000000000000\[ \t\]+.*"
+
+# Set Store Stream Enable in DSCR and set PPR to the medium-low
+# priority.
+gdb_test_no_output "set \$dscr = 0x8"
+gdb_test_no_output "set \$ppr = 0xC000000000000"
+
+gdb_test "stepi" "asm.*"
+
+gdb_test "info reg dscr" "dscr.*0x0*8+\[ \t\]+.*"
+gdb_test "info reg ppr" "ppr.*0x0*\[cC\]000000000000\[ \t\]+.*"
--
2.13.6
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 12/17] [PowerPC] Add tests for TAR
2018-07-13 13:53 [PATCH 00/17] GDB support for more powerpc registers on linux Pedro Franco de Carvalho
` (5 preceding siblings ...)
2018-07-13 13:53 ` [PATCH 08/17] [PowerPC] Add tests for PPR and DSCR Pedro Franco de Carvalho
@ 2018-07-13 13:53 ` Pedro Franco de Carvalho
2018-07-13 15:33 ` Ulrich Weigand
2018-07-13 13:53 ` [PATCH 04/17] [PowerPC] Refactor have_ initializers in rs6000-tdep.c Pedro Franco de Carvalho
` (9 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 13:53 UTC (permalink / raw)
To: gdb-patches; +Cc: uweigand, edjunior
This patch adds a testcase for GDB access to the Target Address
Register.
gdb/testsuite/ChangeLog:
YYYY-MM-DD Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.arch/powerpc-tar.c: New file.
* gdb.arch/powerpc-tar.exp: New file.
---
gdb/testsuite/gdb.arch/powerpc-tar.c | 33 ++++++++++
gdb/testsuite/gdb.arch/powerpc-tar.exp | 115 +++++++++++++++++++++++++++++++++
2 files changed, 148 insertions(+)
create mode 100644 gdb/testsuite/gdb.arch/powerpc-tar.c
create mode 100644 gdb/testsuite/gdb.arch/powerpc-tar.exp
diff --git a/gdb/testsuite/gdb.arch/powerpc-tar.c b/gdb/testsuite/gdb.arch/powerpc-tar.c
new file mode 100644
index 0000000000..8e545b2ba3
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/powerpc-tar.c
@@ -0,0 +1,33 @@
+/* This test is part of GDB, the GNU debugger.
+
+ Copyright 2018 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+int main (void)
+{
+ void * target1 = &&target1_l;
+ void * target2 = &&target2_l;
+ asm volatile ("mtspr 815,%0" : : "r" (target1) : );
+
+ /* Branch always to TAR. */
+ asm volatile ("bctar 20,0,0"); // marker
+
+ target2_l:
+ asm volatile ("nop"); // marker 2
+ target1_l:
+ asm volatile ("nop");
+
+ return 0;
+}
diff --git a/gdb/testsuite/gdb.arch/powerpc-tar.exp b/gdb/testsuite/gdb.arch/powerpc-tar.exp
new file mode 100644
index 0000000000..f3c77a960e
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/powerpc-tar.exp
@@ -0,0 +1,115 @@
+# Copyright 2018 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+# This file is part of the gdb testsuite.
+
+# Test access to special purpose register TAR.
+
+if {![istarget "powerpc*-*-linux*"]} then {
+ verbose "Skipping PowerPC test for the TAR register."
+ return
+}
+
+standard_testfile .c
+
+if {[build_executable "compile" $binfile $srcfile {debug}] == -1} {
+ return -1
+}
+
+proc check_register_access { regname } {
+ global gdb_prompt
+
+ set test "$regname register access"
+ gdb_test_multiple "info reg $regname" "$test" {
+ -re "Invalid register.*\r\n$gdb_prompt $" {
+ unsupported "$test"
+ return 0
+ }
+ -re "\r\n$regname.*\r\n$gdb_prompt $" {
+ pass "$test"
+ return 1
+ }
+ }
+ return 0
+}
+
+clean_restart $binfile
+
+runto_main
+
+if {![check_register_access "tar"]} {
+ return
+}
+
+# Do one pass to check if TAR is usable, system
+# software can prevent it from being used.
+proc tar_available {} {
+ global gdb_prompt
+ global inferior_exited_re
+
+ set test "TAR available to inferior"
+ gdb_test_multiple "continue" "" {
+ -re "Illegal instruction.*\r\n$gdb_prompt $" {
+ unsupported "$test"
+ return 0
+ }
+ -re "$inferior_exited_re normally.*$gdb_prompt $" {
+ pass "$test"
+ return 1
+ }
+ }
+ return 0
+}
+
+if {![tar_available]} {
+ return
+}
+
+# Now do the actual test
+clean_restart $binfile
+
+runto_main
+
+set bp_line [gdb_get_line_number "marker"]
+
+gdb_breakpoint ${srcfile}:${bp_line}
+
+gdb_continue_to_breakpoint "continue to marker"
+
+set target1 [get_hexadecimal_valueof "target1" -1]
+set tar [get_hexadecimal_valueof "\$tar" -2]
+
+set test "TAR value from mtspr"
+
+if {${target1} == ${tar}} {
+ pass $test
+} else {
+ fail $test
+}
+
+set target2 [get_hexadecimal_valueof "target2" -1]
+
+if {$target2 == -1} {
+ fail "Could not get value of label2"
+ return
+}
+
+gdb_test_no_output "set \$tar = $target2"
+
+set bp_line [gdb_get_line_number "marker 2"]
+
+gdb_breakpoint ${srcfile}:${bp_line}
+
+gdb_continue_to_breakpoint "continue to new target address" ".*marker 2.*"
--
2.13.6
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 04/17] [PowerPC] Refactor have_ initializers in rs6000-tdep.c
2018-07-13 13:53 [PATCH 00/17] GDB support for more powerpc registers on linux Pedro Franco de Carvalho
` (6 preceding siblings ...)
2018-07-13 13:53 ` [PATCH 12/17] [PowerPC] Add tests for TAR Pedro Franco de Carvalho
@ 2018-07-13 13:53 ` Pedro Franco de Carvalho
2018-07-13 15:19 ` Ulrich Weigand
2018-07-13 13:53 ` [PATCH 03/17] [PowerPC] Fix indentation in arch/ppc-linux-common.c Pedro Franco de Carvalho
` (8 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 13:53 UTC (permalink / raw)
To: gdb-patches; +Cc: uweigand, edjunior
This patch refactor a series of initializers in rs6000_gdbarch_init
for clarity. The have_fpu initializers is also changed to set the
variable to 0, like the other similar variables. This doesn't affect
program behavior.
gdb/ChangeLog:
YYYY-MM-DD Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* rs6000-tdep.c (rs6000_gdbarch_init): Replace line wrapping by a
second initializer line for the have_* variables. Initialize
have_fpu to 0 instead of 1.
---
gdb/rs6000-tdep.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index 55ce22ea85..f9683887cc 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -5816,8 +5816,8 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
enum powerpc_long_double_abi long_double_abi = POWERPC_LONG_DOUBLE_AUTO;
enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
enum powerpc_elf_abi elf_abi = POWERPC_ELF_AUTO;
- int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0,
- have_vsx = 0;
+ int have_fpu = 0, have_spe = 0, have_mq = 0, have_altivec = 0;
+ int have_dfp = 0, have_vsx = 0;
int tdesc_wordsize = -1;
const struct target_desc *tdesc = info.target_desc;
struct tdesc_arch_data *tdesc_data = NULL;
--
2.13.6
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 03/17] [PowerPC] Fix indentation in arch/ppc-linux-common.c
2018-07-13 13:53 [PATCH 00/17] GDB support for more powerpc registers on linux Pedro Franco de Carvalho
` (7 preceding siblings ...)
2018-07-13 13:53 ` [PATCH 04/17] [PowerPC] Refactor have_ initializers in rs6000-tdep.c Pedro Franco de Carvalho
@ 2018-07-13 13:53 ` Pedro Franco de Carvalho
2018-07-13 15:18 ` Ulrich Weigand
2018-07-13 13:53 ` [PATCH 02/17] [PowerPC] Fix two if statements in gdb/ppc-linux-nat.c Pedro Franco de Carvalho
` (7 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 13:53 UTC (permalink / raw)
To: gdb-patches; +Cc: uweigand, edjunior
This patch parenthesizes the tdesc selection expressions in
arch/ppc-linux-common.c so that they can be tab-indented.
gdb/ChangeLog:
YYYY-MM-DD Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* arch/ppc-linux-common.c (ppc_linux_match_description):
Parenthesize tdesc assignements and indent them properly.
---
gdb/arch/ppc-linux-common.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/gdb/arch/ppc-linux-common.c b/gdb/arch/ppc-linux-common.c
index 45da105de6..eb7de40af0 100644
--- a/gdb/arch/ppc-linux-common.c
+++ b/gdb/arch/ppc-linux-common.c
@@ -53,14 +53,14 @@ ppc_linux_match_description (struct ppc_linux_features features)
if (features.cell)
tdesc = tdesc_powerpc_cell64l;
else if (features.vsx)
- tdesc = features.isa205
- ? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l;
+ tdesc = (features.isa205? tdesc_powerpc_isa205_vsx64l
+ : tdesc_powerpc_vsx64l);
else if (features.altivec)
- tdesc = features.isa205
- ? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l;
+ tdesc = (features.isa205? tdesc_powerpc_isa205_altivec64l
+ : tdesc_powerpc_altivec64l);
else
- tdesc = features.isa205?
- tdesc_powerpc_isa205_64l : tdesc_powerpc_64l;
+ tdesc = (features.isa205? tdesc_powerpc_isa205_64l
+ : tdesc_powerpc_64l);
}
else
{
@@ -69,14 +69,14 @@ ppc_linux_match_description (struct ppc_linux_features features)
if (features.cell)
tdesc = tdesc_powerpc_cell32l;
else if (features.vsx)
- tdesc = features.isa205
- ? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l;
+ tdesc = (features.isa205? tdesc_powerpc_isa205_vsx32l
+ : tdesc_powerpc_vsx32l);
else if (features.altivec)
- tdesc = features.isa205
- ? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l;
+ tdesc = (features.isa205? tdesc_powerpc_isa205_altivec32l
+ : tdesc_powerpc_altivec32l);
else
- tdesc = features.isa205
- ? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l;
+ tdesc = (features.isa205? tdesc_powerpc_isa205_32l
+ : tdesc_powerpc_32l);
}
gdb_assert (tdesc != NULL);
--
2.13.6
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 02/17] [PowerPC] Fix two if statements in gdb/ppc-linux-nat.c
2018-07-13 13:53 [PATCH 00/17] GDB support for more powerpc registers on linux Pedro Franco de Carvalho
` (8 preceding siblings ...)
2018-07-13 13:53 ` [PATCH 03/17] [PowerPC] Fix indentation in arch/ppc-linux-common.c Pedro Franco de Carvalho
@ 2018-07-13 13:53 ` Pedro Franco de Carvalho
2018-07-13 15:17 ` Ulrich Weigand
2018-07-13 13:53 ` [PATCH 13/17] [PowerPC] Add support for HTM registers Pedro Franco de Carvalho
` (6 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 13:53 UTC (permalink / raw)
To: gdb-patches; +Cc: uweigand, edjunior
This patch changes two if statements to else if statements in
ppc-linux-nat.c:fetch_register for clarity.
gdb/ChangeLog:
YYYY-MM-DD Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* ppc-linux-nat.c (fetch_register): Change if statement to else
if.
(store_register): Likewise.
---
gdb/ppc-linux-nat.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c
index 9719a0e906..47028b8688 100644
--- a/gdb/ppc-linux-nat.c
+++ b/gdb/ppc-linux-nat.c
@@ -554,7 +554,7 @@ fetch_register (struct regcache *regcache, int tid, int regno)
AltiVec registers, fall through and return zeroes, because
regaddr will be -1 in this case. */
}
- if (vsx_register_p (gdbarch, regno))
+ else if (vsx_register_p (gdbarch, regno))
{
if (have_ptrace_getsetvsxregs)
{
@@ -933,7 +933,7 @@ store_register (const struct regcache *regcache, int tid, int regno)
store_altivec_registers (regcache, tid, regno);
return;
}
- if (vsx_register_p (gdbarch, regno))
+ else if (vsx_register_p (gdbarch, regno))
{
store_vsx_registers (regcache, tid, regno);
return;
--
2.13.6
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 13/17] [PowerPC] Add support for HTM registers
2018-07-13 13:53 [PATCH 00/17] GDB support for more powerpc registers on linux Pedro Franco de Carvalho
` (9 preceding siblings ...)
2018-07-13 13:53 ` [PATCH 02/17] [PowerPC] Fix two if statements in gdb/ppc-linux-nat.c Pedro Franco de Carvalho
@ 2018-07-13 13:53 ` Pedro Franco de Carvalho
2018-07-13 16:24 ` Ulrich Weigand
2018-07-13 13:53 ` [PATCH 07/17] [PowerPC] Add gdbserver support for PPR and DSCR Pedro Franco de Carvalho
` (5 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 13:53 UTC (permalink / raw)
To: gdb-patches; +Cc: uweigand, edjunior
From: Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
This patch adds support for Hardware Transactional Memory registers
for the powerpc linux native and core file targets.
These registers include both the HTM special-purpose registers (TFHAR,
TEXASR and TFIAR) as well as the set of registers that are
checkpointed (saved) when a transaction is initiated, which the
processor restores in the event of a transaction failure.
The set of checkpointed general-purpose registers is returned by the
linux kernel in the same format as the regular general-purpose
registers, defined in struct pt_regs. However, the architecture
specifies that only some of the registers present in pt_regs are
checkpointed (GPRs 0-31, CR, XER, LR and CTR). The kernel fills the
slots for other registers with other info (e.g., nip is filled with
the contents of TFHAR). GDB doesn't handle these other registers. This
means that core files generated by GDB will show values of zero for
these registers, while core files generated by the kernel will have
other values. Core files generated by the kernel have a note section
for checkpointed GPRs with the same size for both 32-bit and 64-bit
threads, and the values for the registers of a 32-bit thread are
squeezed in the first half, with no useful data in the second
half. GDB generates a smaller note section for 32-bit threads, but can
read both sizes.
Access to the checkpointed CR (condition register) can be
confusing. The architecture only specifies that CR fields 1 to 7 (the
24 least significant bits) are checkpointed, but the kernel provides
all 8 fields (32 bits). The value of field 0 is not masked by ptrace,
so it will sometimes show the result of some kernel operation,
probably treclaim., which sets this field.
The checkpointed registers are marked not to be saved and
restored. Inferior function calls during an active transaction don't
work well, and it's unclear what should be done in this case. TEXASR
and TFIAR can be altered asynchronously, during transaction failure
recording, so they are also not saved and restored. For consistency
neither is TFHAR.
Record and replay also doesn't work well when transactions are
involved. This patch doesn't address this, so the values of the HTM
SPRs will sometimes be innacurate when the record/relay target is
enabled. For instance, executing a "tbegin." alters TFHAR and TEXASR,
but these changes are not currently recorded.
Because the checkpointed registers are only available when a
transaction is active (or suspended), ptrace can return ENODATA when
gdb tries to read these registers and the inferior is not in a
transactional state. The registers are set to the unavailable state
when this happens. When gbd tries to write to one of these registers,
and it is unavailable, an error is raised. When gdb tries to store to
all registers in one go (when store_registers called with -1), the
state of these registers is checked. If they are all unavailable, no
write is attempted, so that writes to all the other registers are
unaffected. If all are available, the write is attempted. Otherwise an
internal_error is raised.
Like for the previous patches, configure.srv is updated here to avoid
breaking the build at this patch.
gdb/ChangeLog:
YYYY-MM-DD Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* arch/ppc-linux-tdesc.h (tdesc_powerpc_isa207_htm_vsx32l)
(tdesc_powerpc_isa207_htm_vsx64l): Declare.
* arch/ppc-linux-common.h (PPC_LINUX_SIZEOF_TM_SPRREGSET)
(PPC32_LINUX_SIZEOF_CGPRREGSET, PPC64_LINUX_SIZEOF_CGPRREGSET)
(PPC_LINUX_SIZEOF_CFPRREGSET, PPC_LINUX_SIZEOF_CVMXREGSET)
(PPC_LINUX_SIZEOF_CVSXREGSET, PPC_LINUX_SIZEOF_CPPRREGSET)
(PPC_LINUX_SIZEOF_CDSCRREGSET, PPC_LINUX_SIZEOF_CTARREGSET):
Define.
(struct ppc_linux_features) <htm>: New field.
(ppc_linux_no_features): Add initializer for htm field.
* arch/ppc-linux-common.c (ppc_linux_match_description): Return
new tdescs.
* nat/ppc-linux.h (PPC_FEATURE2_HTM, NT_PPC_TM_CGPR)
(NT_PPC_TM_CFPR, NT_PPC_TM_CVMX, NT_PPC_TM_CVSX)
(NT_PPC_TM_SPR, NT_PPC_TM_CTAR, NT_PPC_TM_CPPR, NT_PPC_TM_CDSCR):
Define if not already defined.
* features/Makefile (WHICH): Add rs6000/powerpc-isa207-htm-vsx32l
and rs6000/powerpc-isa207-htm-vsx64l.
(XMLTOC): Add rs6000/powerpc-isa207-htm-vsx32l.xml and
rs6000/powerpc-isa207-htm-vsx64l.xml.
* features/rs6000/power-htm.xml: New file.
* features/rs6000/power64-htm.xml: New file.
* features/rs6000/powerpc-isa207-htm-vsx32l.xml: New file.
* features/rs6000/powerpc-isa207-htm-vsx64l.xml: New file.
* features/rs6000/powerpc-isa207-htm-vsx32l.c: Generate.
* features/rs6000/powerpc-isa207-htm-vsx64l.c: Generate.
* regformats/rs6000/powerpc-isa207-htm-vsx32l.dat: Generate.
* regformats/rs6000/powerpc-isa207-htm-vsx64l.dat: Generate.
* ppc-linux-nat.c (fetch_register, fetch_ppc_registers): Call
fetch_regset with HTM regsets.
(ppc_linux_regset_available_p): New function.
(store_register, store_ppc_registers): Call store_regset with HTM
regsets.
(ppc_linux_nat_target::read_description): Set htm field in the
features struct if needed.
* ppc-linux-tdep.c: Include
features/rs6000/powerpc-isa207-htm-vsx32l.c and
features/rs6000/powerpc-isa207-htm-vsx64l.c.
(ppc_linux_collect_vrregset): Zero pad if regno is the
checkpointed VSCR or the checkpointed VRSAVE.
(ppc_linux_collect_and_clear_cgprregset): New function.
(ppc32_regmap_tm_spr, ppc32_regmap_cgpr, ppc64_le_regmap_cgpr)
(ppc64_be_regmap_cgpr, ppc32_regmap_cfpr, ppc32_le_regmap_cvmx)
(ppc32_be_regmap_cvmx, ppc32_regmap_cvsx, ppc32_regmap_cppr)
(ppc32_regmap_cdscr, ppc32_regmap_ctar): New globals.
(ppc32_linux_tm_sprregset, ppc32_linux_cfprregset)
(ppc32_le_linux_cvmxregset, ppc32_be_linux_cvmxregset)
(ppc32_linux_cvsxregset, ppc32_linux_cpprregset)
(ppc32_linux_cdscrregset, ppc32_linux_ctarregset): New globals.
(ppc_linux_cgprregset, ppc_linux_cvmxregset): New functions.
(ppc_linux_iterate_over_regset_sections): Call back with the htm
regsets.
(ppc_linux_core_read_description): Check if the tm spr section is
present and set htm in the features struct.
(_initialize_ppc_linux_tdep): Call
initialize_tdesc_powerpc_isa207_htm_vsx32l and
initialize_tdesc_powerpc_isa207_htm_vsx64l.
* ppc-linux-tdep.h (ppc_linux_cgprregset)
(ppc32_linux_tm_sprregset, ppc32_linux_cfprregset)
(ppc32_linux_cvsxregset, ppc32_linux_cpprregset)
(ppc32_linux_cdscrregset, ppc32_linux_ctarregset)
(ppc_linux_cvmxregset): Declare.
* ppc-tdep.h (struct gdbarch_tdep) <have_htm, ppc_cvsr0_regnum>:
New fields.
(enum) <PPC_TFHAR_REGNUM, PPC_TEXASR_REGNUM, PPC_TFIAR_REGNUM>:
New enum fields.
<PPC_CR0_REGNUM, PPC_CCR_REGNUM, PPC_CXER_REGNUM>: Likewise.
<PPC_CLR_REGNUM, PPC_CCTR_REGNUM, PPC_CF0_REGNUM>: Likewise.
<PPC_CFPSCR_REGNUM, PPC_CVR0_REGNUM, PPC_CVSCR_REGNUM>: Likewise.
<PPC_CVRSAVE_REGNUM, PPC_CVS0H_REGNUM, PPC_CPPR_REGNUM>: Likewise.
<PPC_CDSCR_REGNUM, PPC_CTAR_REGNUM>: Likewise.
(PPC_IS_TMSPR_REGNUM, PPC_IS_CKPTGP_REGNUM, PPC_IS_CKPTFP_REGNUM)
(PPC_IS_CKPTVMX_REGNUM, PPC_IS_CKPTVSX_REGNUM): Define.
* rs6000-tdep.c (IS_CVSX_PSEUDOREG): Define.
(rs6000_register_name): Hide the upper halves of checkpointed VSX
registers. Return names for the full checkpointed VSX registers.
(rs6000_pseudo_register_type): Include checkpointed VSX registers
in the assert expression and return rs6000_builtin_type_vec128 for
them.
(rs6000_pseudo_register_reggroup_p): Include checkpointed VSX
registers in the assert expression.
(cvsx_pseudo_register_read, cvsx_pseudo_register_write): New
functions.
(rs6000_pseudo_register_read, rs6000_pseudo_register_write)
(rs6000_ax_pseudo_register_collect): Handle checkpointed VSX
registers.
(rs6000_gdbarch_init): Look for and validate the htm
feature. Include checkpointed VSX pseudo-registers.
gdb/gdbserver/ChangeLog:
YYYY-MM-DD Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* configure.srv (ipa_ppc_linux_regobj): Add
powerpc-isa207-htm-vsx32l-ipa.o and
powerpc-isa207-htm-vsx64l-ipa.o.
(powerpc*-*-linux*): Add powerpc-isa207-htm-vsx32l.o and
powerpc-isa207-htm-vsx64l.o to srv_regobj, add
rs6000/power-htm.xml, rs6000/power64-htm.xml,
rs6000/powerpc-isa207-htm-vsx32l.xml, and
rs6000/powerpc-isa207-htm-vsx64l.xml to srv_xmlfiles.
---
gdb/arch/ppc-linux-common.c | 6 +-
gdb/arch/ppc-linux-common.h | 11 +
gdb/arch/ppc-linux-tdesc.h | 2 +
gdb/features/Makefile | 4 +
gdb/features/rs6000/power-htm.xml | 174 ++++++++++
gdb/features/rs6000/power64-htm.xml | 174 ++++++++++
gdb/features/rs6000/powerpc-isa207-htm-vsx32l.c | 370 +++++++++++++++++++++
gdb/features/rs6000/powerpc-isa207-htm-vsx32l.xml | 20 ++
gdb/features/rs6000/powerpc-isa207-htm-vsx64l.c | 370 +++++++++++++++++++++
gdb/features/rs6000/powerpc-isa207-htm-vsx64l.xml | 20 ++
gdb/gdbserver/configure.srv | 8 +-
gdb/nat/ppc-linux.h | 43 +++
gdb/ppc-linux-nat.c | 304 ++++++++++++++++-
gdb/ppc-linux-tdep.c | 292 +++++++++++++++-
gdb/ppc-linux-tdep.h | 22 ++
gdb/ppc-tdep.h | 44 +++
.../rs6000/powerpc-isa207-htm-vsx32l.dat | 288 ++++++++++++++++
.../rs6000/powerpc-isa207-htm-vsx64l.dat | 288 ++++++++++++++++
gdb/rs6000-tdep.c | 239 ++++++++++++-
19 files changed, 2661 insertions(+), 18 deletions(-)
create mode 100644 gdb/features/rs6000/power-htm.xml
create mode 100644 gdb/features/rs6000/power64-htm.xml
create mode 100644 gdb/features/rs6000/powerpc-isa207-htm-vsx32l.c
create mode 100644 gdb/features/rs6000/powerpc-isa207-htm-vsx32l.xml
create mode 100644 gdb/features/rs6000/powerpc-isa207-htm-vsx64l.c
create mode 100644 gdb/features/rs6000/powerpc-isa207-htm-vsx64l.xml
create mode 100644 gdb/regformats/rs6000/powerpc-isa207-htm-vsx32l.dat
create mode 100644 gdb/regformats/rs6000/powerpc-isa207-htm-vsx64l.dat
diff --git a/gdb/arch/ppc-linux-common.c b/gdb/arch/ppc-linux-common.c
index b8a7cdb2ad..cc4d164320 100644
--- a/gdb/arch/ppc-linux-common.c
+++ b/gdb/arch/ppc-linux-common.c
@@ -53,7 +53,8 @@ ppc_linux_match_description (struct ppc_linux_features features)
if (features.cell)
tdesc = tdesc_powerpc_cell64l;
else if (features.vsx)
- tdesc = (features.isa207? tdesc_powerpc_isa207_vsx64l
+ tdesc = (features.htm? tdesc_powerpc_isa207_htm_vsx64l
+ : features.isa207? tdesc_powerpc_isa207_vsx64l
: features.ppr_dscr? tdesc_powerpc_isa205_ppr_dscr_vsx64l
: features.isa205? tdesc_powerpc_isa205_vsx64l
: tdesc_powerpc_vsx64l);
@@ -71,7 +72,8 @@ ppc_linux_match_description (struct ppc_linux_features features)
if (features.cell)
tdesc = tdesc_powerpc_cell32l;
else if (features.vsx)
- tdesc = (features.isa207? tdesc_powerpc_isa207_vsx32l
+ tdesc = (features.htm? tdesc_powerpc_isa207_htm_vsx32l
+ : features.isa207? tdesc_powerpc_isa207_vsx32l
: features.ppr_dscr? tdesc_powerpc_isa205_ppr_dscr_vsx32l
: features.isa205? tdesc_powerpc_isa205_vsx32l
: tdesc_powerpc_vsx32l);
diff --git a/gdb/arch/ppc-linux-common.h b/gdb/arch/ppc-linux-common.h
index f0e4a4221f..71e2d5d173 100644
--- a/gdb/arch/ppc-linux-common.h
+++ b/gdb/arch/ppc-linux-common.h
@@ -33,6 +33,15 @@ struct target_desc;
#define PPC_LINUX_SIZEOF_PPRREGSET 8
#define PPC_LINUX_SIZEOF_DSCRREGSET 8
#define PPC_LINUX_SIZEOF_TARREGSET 8
+#define PPC_LINUX_SIZEOF_TM_SPRREGSET (3*8)
+#define PPC32_LINUX_SIZEOF_CGPRREGSET (48*4)
+#define PPC64_LINUX_SIZEOF_CGPRREGSET (48*8)
+#define PPC_LINUX_SIZEOF_CFPRREGSET (32*8+8)
+#define PPC_LINUX_SIZEOF_CVMXREGSET (34*16)
+#define PPC_LINUX_SIZEOF_CVSXREGSET (32*8)
+#define PPC_LINUX_SIZEOF_CPPRREGSET 8
+#define PPC_LINUX_SIZEOF_CDSCRREGSET 8
+#define PPC_LINUX_SIZEOF_CTARREGSET 8
/* Check if the hwcap auxv entry indicates that isa205 is supported. */
bool ppc_linux_has_isa205 (CORE_ADDR hwcap);
@@ -46,6 +55,7 @@ struct ppc_linux_features
bool isa205;
bool ppr_dscr;
bool isa207;
+ bool htm;
bool cell;
};
@@ -58,6 +68,7 @@ const struct ppc_linux_features ppc_linux_no_features = {
false,
false,
false,
+ false,
};
/* Return a target description that matches FEATURES. */
diff --git a/gdb/arch/ppc-linux-tdesc.h b/gdb/arch/ppc-linux-tdesc.h
index 9962879786..2716be7e53 100644
--- a/gdb/arch/ppc-linux-tdesc.h
+++ b/gdb/arch/ppc-linux-tdesc.h
@@ -31,6 +31,7 @@ extern struct target_desc *tdesc_powerpc_isa205_altivec32l;
extern struct target_desc *tdesc_powerpc_isa205_vsx32l;
extern struct target_desc *tdesc_powerpc_isa205_ppr_dscr_vsx32l;
extern struct target_desc *tdesc_powerpc_isa207_vsx32l;
+extern struct target_desc *tdesc_powerpc_isa207_htm_vsx32l;
extern struct target_desc *tdesc_powerpc_e500l;
extern struct target_desc *tdesc_powerpc_64l;
@@ -42,5 +43,6 @@ extern struct target_desc *tdesc_powerpc_isa205_altivec64l;
extern struct target_desc *tdesc_powerpc_isa205_vsx64l;
extern struct target_desc *tdesc_powerpc_isa205_ppr_dscr_vsx64l;
extern struct target_desc *tdesc_powerpc_isa207_vsx64l;
+extern struct target_desc *tdesc_powerpc_isa207_htm_vsx64l;
#endif /* ARCH_PPC_LINUX_TDESC_H */
diff --git a/gdb/features/Makefile b/gdb/features/Makefile
index 6eaa7db05f..150fef23f0 100644
--- a/gdb/features/Makefile
+++ b/gdb/features/Makefile
@@ -76,6 +76,8 @@ WHICH = aarch64 \
rs6000/powerpc-isa205-ppr-dscr-vsx32l \
rs6000/powerpc-isa205-ppr-dscr-vsx64l \
rs6000/powerpc-isa207-vsx32l rs6000/powerpc-isa207-vsx64l \
+ rs6000/powerpc-isa207-htm-vsx32l \
+ rs6000/powerpc-isa207-htm-vsx64l \
s390-linux32 s390-linux64 s390x-linux64 \
s390-linux32v1 s390-linux64v1 s390x-linux64v1 \
s390-linux32v2 s390-linux64v2 s390x-linux64v2 \
@@ -174,6 +176,8 @@ XMLTOC = \
rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml \
rs6000/powerpc-isa207-vsx32l.xml \
rs6000/powerpc-isa207-vsx64l.xml \
+ rs6000/powerpc-isa207-htm-vsx32l.xml \
+ rs6000/powerpc-isa207-htm-vsx64l.xml \
rs6000/powerpc-vsx32.xml \
rs6000/powerpc-vsx32l.xml \
rs6000/powerpc-vsx64.xml \
diff --git a/gdb/features/rs6000/power-htm.xml b/gdb/features/rs6000/power-htm.xml
new file mode 100644
index 0000000000..5dab31b82f
--- /dev/null
+++ b/gdb/features/rs6000/power-htm.xml
@@ -0,0 +1,174 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- POWER8 Hardware Transactional Memory Registers. -->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.power.htm">
+ <reg name="tfhar" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="texasr" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="tfiar" bitsize="64" type="uint64" save-restore="no"/>
+
+ <reg name="cr0" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr1" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr2" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr3" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr4" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr5" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr6" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr7" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr8" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr9" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr10" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr11" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr12" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr13" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr14" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr15" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr16" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr17" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr18" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr19" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr20" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr21" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr22" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr23" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr24" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr25" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr26" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr27" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr28" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr29" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr30" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cr31" bitsize="32" type="uint32" save-restore="no"/>
+
+ <reg name="ccr" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cxer" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="clr" bitsize="32" type="code_ptr" save-restore="no"/>
+ <reg name="cctr" bitsize="32" type="uint32" save-restore="no"/>
+
+ <reg name="cf0" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf1" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf2" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf3" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf4" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf5" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf6" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf7" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf8" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf9" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf10" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf11" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf12" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf13" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf14" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf15" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf16" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf17" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf18" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf19" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf20" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf21" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf22" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf23" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf24" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf25" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf26" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf27" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf28" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf29" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf30" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf31" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cfpscr" bitsize="64" type="uint64" group="float"
+ save-restore="no"/>
+
+ <!-- HTM Checkpointed Altivec (VMX) registers -->
+ <vector id="v4f" type="ieee_single" count="4"/>
+ <vector id="v4i32" type="int32" count="4"/>
+ <vector id="v8i16" type="int16" count="8"/>
+ <vector id="v16i8" type="int8" count="16"/>
+ <union id="vec128">
+ <field name="uint128" type="uint128"/>
+ <field name="v4_float" type="v4f"/>
+ <field name="v4_int32" type="v4i32"/>
+ <field name="v8_int16" type="v8i16"/>
+ <field name="v16_int8" type="v16i8"/>
+ </union>
+
+ <reg name="cvr0" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr1" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr2" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr3" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr4" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr5" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr6" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr7" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr8" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr9" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr10" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr11" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr12" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr13" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr14" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr15" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr16" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr17" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr18" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr19" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr20" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr21" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr22" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr23" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr24" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr25" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr26" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr27" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr28" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr29" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr30" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr31" bitsize="128" type="vec128" save-restore="no"/>
+
+ <reg name="cvscr" bitsize="32" save-restore="no"/>
+ <reg name="cvrsave" bitsize="32" save-restore="no"/>
+
+ <!-- HTM Checkpointed VSX registers -->
+ <reg name="cvs0h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs1h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs2h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs3h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs4h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs5h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs6h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs7h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs8h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs9h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs10h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs11h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs12h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs13h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs14h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs15h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs16h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs17h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs18h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs19h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs20h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs21h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs22h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs23h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs24h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs25h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs26h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs27h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs28h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs29h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs30h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs31h" bitsize="64" type="uint64" save-restore="no"/>
+
+ <reg name="cppr" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cdscr" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="ctar" bitsize="64" type="uint64" save-restore="no"/>
+</feature>
diff --git a/gdb/features/rs6000/power64-htm.xml b/gdb/features/rs6000/power64-htm.xml
new file mode 100644
index 0000000000..6900418bd7
--- /dev/null
+++ b/gdb/features/rs6000/power64-htm.xml
@@ -0,0 +1,174 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- POWER8 Hardware Transactional Memory Registers. -->
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.power.htm">
+ <reg name="tfhar" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="texasr" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="tfiar" bitsize="64" type="uint64" save-restore="no"/>
+
+ <reg name="cr0" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr1" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr2" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr3" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr4" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr5" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr6" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr7" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr8" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr9" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr10" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr11" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr12" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr13" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr14" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr15" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr16" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr17" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr18" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr19" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr20" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr21" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr22" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr23" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr24" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr25" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr26" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr27" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr28" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr29" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr30" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cr31" bitsize="64" type="uint64" save-restore="no"/>
+
+ <reg name="ccr" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="cxer" bitsize="32" type="uint32" save-restore="no"/>
+ <reg name="clr" bitsize="64" type="code_ptr" save-restore="no"/>
+ <reg name="cctr" bitsize="64" type="uint64" save-restore="no"/>
+
+ <reg name="cf0" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf1" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf2" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf3" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf4" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf5" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf6" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf7" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf8" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf9" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf10" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf11" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf12" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf13" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf14" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf15" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf16" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf17" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf18" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf19" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf20" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf21" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf22" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf23" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf24" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf25" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf26" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf27" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf28" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf29" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf30" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cf31" bitsize="64" type="ieee_double" save-restore="no"/>
+ <reg name="cfpscr" bitsize="64" type="uint64" group="float"
+ save-restore="no"/>
+
+ <!-- HTM Checkpointed Altivec (VMX) registers -->
+ <vector id="v4f" type="ieee_single" count="4"/>
+ <vector id="v4i32" type="int32" count="4"/>
+ <vector id="v8i16" type="int16" count="8"/>
+ <vector id="v16i8" type="int8" count="16"/>
+ <union id="vec128">
+ <field name="uint128" type="uint128"/>
+ <field name="v4_float" type="v4f"/>
+ <field name="v4_int32" type="v4i32"/>
+ <field name="v8_int16" type="v8i16"/>
+ <field name="v16_int8" type="v16i8"/>
+ </union>
+
+ <reg name="cvr0" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr1" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr2" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr3" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr4" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr5" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr6" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr7" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr8" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr9" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr10" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr11" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr12" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr13" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr14" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr15" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr16" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr17" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr18" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr19" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr20" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr21" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr22" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr23" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr24" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr25" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr26" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr27" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr28" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr29" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr30" bitsize="128" type="vec128" save-restore="no"/>
+ <reg name="cvr31" bitsize="128" type="vec128" save-restore="no"/>
+
+ <reg name="cvscr" bitsize="32" save-restore="no"/>
+ <reg name="cvrsave" bitsize="32" save-restore="no"/>
+
+ <!-- HTM Checkpointed VSX registers -->
+ <reg name="cvs0h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs1h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs2h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs3h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs4h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs5h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs6h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs7h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs8h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs9h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs10h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs11h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs12h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs13h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs14h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs15h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs16h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs17h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs18h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs19h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs20h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs21h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs22h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs23h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs24h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs25h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs26h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs27h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs28h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs29h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs30h" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cvs31h" bitsize="64" type="uint64" save-restore="no"/>
+
+ <reg name="cppr" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="cdscr" bitsize="64" type="uint64" save-restore="no"/>
+ <reg name="ctar" bitsize="64" type="uint64" save-restore="no"/>
+</feature>
diff --git a/gdb/features/rs6000/powerpc-isa207-htm-vsx32l.c b/gdb/features/rs6000/powerpc-isa207-htm-vsx32l.c
new file mode 100644
index 0000000000..99c6a7feb7
--- /dev/null
+++ b/gdb/features/rs6000/powerpc-isa207-htm-vsx32l.c
@@ -0,0 +1,370 @@
+/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
+ Original: powerpc-isa207-htm-vsx32l.xml */
+
+#include "defs.h"
+#include "osabi.h"
+#include "target-descriptions.h"
+
+struct target_desc *tdesc_powerpc_isa207_htm_vsx32l;
+static void
+initialize_tdesc_powerpc_isa207_htm_vsx32l (void)
+{
+ struct target_desc *result = allocate_target_description ();
+ set_tdesc_architecture (result, bfd_scan_arch ("powerpc:common"));
+
+ struct tdesc_feature *feature;
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.core");
+ tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r5", 5, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r6", 6, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r7", 7, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r8", 8, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r9", 9, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r10", 10, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r11", 11, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r12", 12, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r13", 13, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r14", 14, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r15", 15, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r16", 16, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r17", 17, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r18", 18, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r19", 19, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r20", 20, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r21", 21, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r22", 22, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r23", 23, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r24", 24, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r25", 25, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r26", 26, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r27", 27, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r28", 28, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "pc", 64, 1, NULL, 32, "code_ptr");
+ tdesc_create_reg (feature, "msr", 65, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr", 66, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "lr", 67, 1, NULL, 32, "code_ptr");
+ tdesc_create_reg (feature, "ctr", 68, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "xer", 69, 1, NULL, 32, "uint32");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.fpu");
+ tdesc_create_reg (feature, "f0", 32, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f1", 33, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f2", 34, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f3", 35, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f4", 36, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f5", 37, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f6", 38, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f7", 39, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f8", 40, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f9", 41, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f10", 42, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f11", 43, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f12", 44, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f13", 45, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f14", 46, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f15", 47, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f16", 48, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f17", 49, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f18", 50, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f19", 51, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f20", 52, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f21", 53, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f22", 54, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f23", 55, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f24", 56, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f25", 57, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f26", 58, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f27", 59, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f28", 60, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f29", 61, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f30", 62, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f31", 63, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "fpscr", 70, 1, "float", 64, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.linux");
+ tdesc_create_reg (feature, "orig_r3", 71, 1, NULL, 32, "int");
+ tdesc_create_reg (feature, "trap", 72, 1, NULL, 32, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.altivec");
+ tdesc_type *element_type;
+ element_type = tdesc_named_type (feature, "ieee_single");
+ tdesc_create_vector (feature, "v4f", element_type, 4);
+
+ element_type = tdesc_named_type (feature, "int32");
+ tdesc_create_vector (feature, "v4i32", element_type, 4);
+
+ element_type = tdesc_named_type (feature, "int16");
+ tdesc_create_vector (feature, "v8i16", element_type, 8);
+
+ element_type = tdesc_named_type (feature, "int8");
+ tdesc_create_vector (feature, "v16i8", element_type, 16);
+
+ tdesc_type_with_fields *type_with_fields;
+ type_with_fields = tdesc_create_union (feature, "vec128");
+ tdesc_type *field_type;
+ field_type = tdesc_named_type (feature, "uint128");
+ tdesc_add_field (type_with_fields, "uint128", field_type);
+ field_type = tdesc_named_type (feature, "v4f");
+ tdesc_add_field (type_with_fields, "v4_float", field_type);
+ field_type = tdesc_named_type (feature, "v4i32");
+ tdesc_add_field (type_with_fields, "v4_int32", field_type);
+ field_type = tdesc_named_type (feature, "v8i16");
+ tdesc_add_field (type_with_fields, "v8_int16", field_type);
+ field_type = tdesc_named_type (feature, "v16i8");
+ tdesc_add_field (type_with_fields, "v16_int8", field_type);
+
+ tdesc_create_reg (feature, "vr0", 73, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr1", 74, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr2", 75, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr3", 76, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr4", 77, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr5", 78, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr6", 79, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr7", 80, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr8", 81, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr9", 82, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr10", 83, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr11", 84, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr12", 85, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr13", 86, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr14", 87, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr15", 88, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr16", 89, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr17", 90, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr18", 91, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr19", 92, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr20", 93, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr21", 94, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr22", 95, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr23", 96, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr24", 97, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr25", 98, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr26", 99, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr27", 100, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr28", 101, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr29", 102, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr30", 103, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr31", 104, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vscr", 105, 1, "vector", 32, "int");
+ tdesc_create_reg (feature, "vrsave", 106, 1, "vector", 32, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.vsx");
+ tdesc_create_reg (feature, "vs0h", 107, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs1h", 108, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs2h", 109, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs3h", 110, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs4h", 111, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs5h", 112, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs6h", 113, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs7h", 114, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs8h", 115, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs9h", 116, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs10h", 117, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs11h", 118, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs12h", 119, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs13h", 120, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs14h", 121, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs15h", 122, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs16h", 123, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs17h", 124, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs18h", 125, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs19h", 126, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs20h", 127, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs21h", 128, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs22h", 129, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs23h", 130, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs24h", 131, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs25h", 132, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs26h", 133, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs27h", 134, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs28h", 135, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs29h", 136, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs30h", 137, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs31h", 138, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.ppr");
+ tdesc_create_reg (feature, "ppr", 139, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.dscr");
+ tdesc_create_reg (feature, "dscr", 140, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.tar");
+ tdesc_create_reg (feature, "tar", 141, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.htm");
+ element_type = tdesc_named_type (feature, "ieee_single");
+ tdesc_create_vector (feature, "v4f", element_type, 4);
+
+ element_type = tdesc_named_type (feature, "int32");
+ tdesc_create_vector (feature, "v4i32", element_type, 4);
+
+ element_type = tdesc_named_type (feature, "int16");
+ tdesc_create_vector (feature, "v8i16", element_type, 8);
+
+ element_type = tdesc_named_type (feature, "int8");
+ tdesc_create_vector (feature, "v16i8", element_type, 16);
+
+ type_with_fields = tdesc_create_union (feature, "vec128");
+ field_type = tdesc_named_type (feature, "uint128");
+ tdesc_add_field (type_with_fields, "uint128", field_type);
+ field_type = tdesc_named_type (feature, "v4f");
+ tdesc_add_field (type_with_fields, "v4_float", field_type);
+ field_type = tdesc_named_type (feature, "v4i32");
+ tdesc_add_field (type_with_fields, "v4_int32", field_type);
+ field_type = tdesc_named_type (feature, "v8i16");
+ tdesc_add_field (type_with_fields, "v8_int16", field_type);
+ field_type = tdesc_named_type (feature, "v16i8");
+ tdesc_add_field (type_with_fields, "v16_int8", field_type);
+
+ tdesc_create_reg (feature, "tfhar", 142, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "texasr", 143, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "tfiar", 144, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr0", 145, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr1", 146, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr2", 147, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr3", 148, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr4", 149, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr5", 150, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr6", 151, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr7", 152, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr8", 153, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr9", 154, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr10", 155, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr11", 156, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr12", 157, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr13", 158, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr14", 159, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr15", 160, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr16", 161, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr17", 162, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr18", 163, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr19", 164, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr20", 165, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr21", 166, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr22", 167, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr23", 168, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr24", 169, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr25", 170, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr26", 171, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr27", 172, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr28", 173, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr29", 174, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr30", 175, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cr31", 176, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "ccr", 177, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cxer", 178, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "clr", 179, 0, NULL, 32, "code_ptr");
+ tdesc_create_reg (feature, "cctr", 180, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cf0", 181, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf1", 182, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf2", 183, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf3", 184, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf4", 185, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf5", 186, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf6", 187, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf7", 188, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf8", 189, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf9", 190, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf10", 191, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf11", 192, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf12", 193, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf13", 194, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf14", 195, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf15", 196, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf16", 197, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf17", 198, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf18", 199, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf19", 200, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf20", 201, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf21", 202, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf22", 203, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf23", 204, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf24", 205, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf25", 206, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf26", 207, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf27", 208, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf28", 209, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf29", 210, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf30", 211, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf31", 212, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cfpscr", 213, 0, "float", 64, "uint64");
+ tdesc_create_reg (feature, "cvr0", 214, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr1", 215, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr2", 216, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr3", 217, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr4", 218, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr5", 219, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr6", 220, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr7", 221, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr8", 222, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr9", 223, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr10", 224, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr11", 225, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr12", 226, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr13", 227, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr14", 228, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr15", 229, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr16", 230, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr17", 231, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr18", 232, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr19", 233, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr20", 234, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr21", 235, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr22", 236, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr23", 237, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr24", 238, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr25", 239, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr26", 240, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr27", 241, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr28", 242, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr29", 243, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr30", 244, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr31", 245, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvscr", 246, 0, NULL, 32, "int");
+ tdesc_create_reg (feature, "cvrsave", 247, 0, NULL, 32, "int");
+ tdesc_create_reg (feature, "cvs0h", 248, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs1h", 249, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs2h", 250, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs3h", 251, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs4h", 252, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs5h", 253, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs6h", 254, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs7h", 255, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs8h", 256, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs9h", 257, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs10h", 258, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs11h", 259, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs12h", 260, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs13h", 261, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs14h", 262, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs15h", 263, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs16h", 264, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs17h", 265, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs18h", 266, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs19h", 267, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs20h", 268, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs21h", 269, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs22h", 270, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs23h", 271, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs24h", 272, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs25h", 273, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs26h", 274, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs27h", 275, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs28h", 276, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs29h", 277, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs30h", 278, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs31h", 279, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cppr", 280, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cdscr", 281, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "ctar", 282, 0, NULL, 64, "uint64");
+
+ tdesc_powerpc_isa207_htm_vsx32l = result;
+}
diff --git a/gdb/features/rs6000/powerpc-isa207-htm-vsx32l.xml b/gdb/features/rs6000/powerpc-isa207-htm-vsx32l.xml
new file mode 100644
index 0000000000..84192b0c38
--- /dev/null
+++ b/gdb/features/rs6000/powerpc-isa207-htm-vsx32l.xml
@@ -0,0 +1,20 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>powerpc:common</architecture>
+ <xi:include href="power-core.xml"/>
+ <xi:include href="power-fpu-isa205.xml"/>
+ <xi:include href="power-linux.xml"/>
+ <xi:include href="power-altivec.xml"/>
+ <xi:include href="power-vsx.xml"/>
+ <xi:include href="power-ppr.xml"/>
+ <xi:include href="power-dscr.xml"/>
+ <xi:include href="power-tar.xml"/>
+ <xi:include href="power-htm.xml"/>
+</target>
diff --git a/gdb/features/rs6000/powerpc-isa207-htm-vsx64l.c b/gdb/features/rs6000/powerpc-isa207-htm-vsx64l.c
new file mode 100644
index 0000000000..2647a077dd
--- /dev/null
+++ b/gdb/features/rs6000/powerpc-isa207-htm-vsx64l.c
@@ -0,0 +1,370 @@
+/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro:
+ Original: powerpc-isa207-htm-vsx64l.xml */
+
+#include "defs.h"
+#include "osabi.h"
+#include "target-descriptions.h"
+
+struct target_desc *tdesc_powerpc_isa207_htm_vsx64l;
+static void
+initialize_tdesc_powerpc_isa207_htm_vsx64l (void)
+{
+ struct target_desc *result = allocate_target_description ();
+ set_tdesc_architecture (result, bfd_scan_arch ("powerpc:common64"));
+
+ struct tdesc_feature *feature;
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.core");
+ tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "pc", 64, 1, NULL, 64, "code_ptr");
+ tdesc_create_reg (feature, "msr", 65, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr", 66, 1, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "lr", 67, 1, NULL, 64, "code_ptr");
+ tdesc_create_reg (feature, "ctr", 68, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "xer", 69, 1, NULL, 32, "uint32");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.fpu");
+ tdesc_create_reg (feature, "f0", 32, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f1", 33, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f2", 34, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f3", 35, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f4", 36, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f5", 37, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f6", 38, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f7", 39, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f8", 40, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f9", 41, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f10", 42, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f11", 43, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f12", 44, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f13", 45, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f14", 46, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f15", 47, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f16", 48, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f17", 49, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f18", 50, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f19", 51, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f20", 52, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f21", 53, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f22", 54, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f23", 55, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f24", 56, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f25", 57, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f26", 58, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f27", 59, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f28", 60, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f29", 61, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f30", 62, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "f31", 63, 1, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "fpscr", 70, 1, "float", 64, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.linux");
+ tdesc_create_reg (feature, "orig_r3", 71, 1, NULL, 64, "int");
+ tdesc_create_reg (feature, "trap", 72, 1, NULL, 64, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.altivec");
+ tdesc_type *element_type;
+ element_type = tdesc_named_type (feature, "ieee_single");
+ tdesc_create_vector (feature, "v4f", element_type, 4);
+
+ element_type = tdesc_named_type (feature, "int32");
+ tdesc_create_vector (feature, "v4i32", element_type, 4);
+
+ element_type = tdesc_named_type (feature, "int16");
+ tdesc_create_vector (feature, "v8i16", element_type, 8);
+
+ element_type = tdesc_named_type (feature, "int8");
+ tdesc_create_vector (feature, "v16i8", element_type, 16);
+
+ tdesc_type_with_fields *type_with_fields;
+ type_with_fields = tdesc_create_union (feature, "vec128");
+ tdesc_type *field_type;
+ field_type = tdesc_named_type (feature, "uint128");
+ tdesc_add_field (type_with_fields, "uint128", field_type);
+ field_type = tdesc_named_type (feature, "v4f");
+ tdesc_add_field (type_with_fields, "v4_float", field_type);
+ field_type = tdesc_named_type (feature, "v4i32");
+ tdesc_add_field (type_with_fields, "v4_int32", field_type);
+ field_type = tdesc_named_type (feature, "v8i16");
+ tdesc_add_field (type_with_fields, "v8_int16", field_type);
+ field_type = tdesc_named_type (feature, "v16i8");
+ tdesc_add_field (type_with_fields, "v16_int8", field_type);
+
+ tdesc_create_reg (feature, "vr0", 73, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr1", 74, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr2", 75, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr3", 76, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr4", 77, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr5", 78, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr6", 79, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr7", 80, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr8", 81, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr9", 82, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr10", 83, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr11", 84, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr12", 85, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr13", 86, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr14", 87, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr15", 88, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr16", 89, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr17", 90, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr18", 91, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr19", 92, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr20", 93, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr21", 94, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr22", 95, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr23", 96, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr24", 97, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr25", 98, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr26", 99, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr27", 100, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr28", 101, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr29", 102, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr30", 103, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vr31", 104, 1, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "vscr", 105, 1, "vector", 32, "int");
+ tdesc_create_reg (feature, "vrsave", 106, 1, "vector", 32, "int");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.vsx");
+ tdesc_create_reg (feature, "vs0h", 107, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs1h", 108, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs2h", 109, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs3h", 110, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs4h", 111, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs5h", 112, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs6h", 113, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs7h", 114, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs8h", 115, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs9h", 116, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs10h", 117, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs11h", 118, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs12h", 119, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs13h", 120, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs14h", 121, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs15h", 122, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs16h", 123, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs17h", 124, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs18h", 125, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs19h", 126, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs20h", 127, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs21h", 128, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs22h", 129, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs23h", 130, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs24h", 131, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs25h", 132, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs26h", 133, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs27h", 134, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs28h", 135, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs29h", 136, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs30h", 137, 1, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "vs31h", 138, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.ppr");
+ tdesc_create_reg (feature, "ppr", 139, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.dscr");
+ tdesc_create_reg (feature, "dscr", 140, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.tar");
+ tdesc_create_reg (feature, "tar", 141, 1, NULL, 64, "uint64");
+
+ feature = tdesc_create_feature (result, "org.gnu.gdb.power.htm");
+ element_type = tdesc_named_type (feature, "ieee_single");
+ tdesc_create_vector (feature, "v4f", element_type, 4);
+
+ element_type = tdesc_named_type (feature, "int32");
+ tdesc_create_vector (feature, "v4i32", element_type, 4);
+
+ element_type = tdesc_named_type (feature, "int16");
+ tdesc_create_vector (feature, "v8i16", element_type, 8);
+
+ element_type = tdesc_named_type (feature, "int8");
+ tdesc_create_vector (feature, "v16i8", element_type, 16);
+
+ type_with_fields = tdesc_create_union (feature, "vec128");
+ field_type = tdesc_named_type (feature, "uint128");
+ tdesc_add_field (type_with_fields, "uint128", field_type);
+ field_type = tdesc_named_type (feature, "v4f");
+ tdesc_add_field (type_with_fields, "v4_float", field_type);
+ field_type = tdesc_named_type (feature, "v4i32");
+ tdesc_add_field (type_with_fields, "v4_int32", field_type);
+ field_type = tdesc_named_type (feature, "v8i16");
+ tdesc_add_field (type_with_fields, "v8_int16", field_type);
+ field_type = tdesc_named_type (feature, "v16i8");
+ tdesc_add_field (type_with_fields, "v16_int8", field_type);
+
+ tdesc_create_reg (feature, "tfhar", 142, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "texasr", 143, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "tfiar", 144, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr0", 145, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr1", 146, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr2", 147, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr3", 148, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr4", 149, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr5", 150, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr6", 151, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr7", 152, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr8", 153, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr9", 154, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr10", 155, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr11", 156, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr12", 157, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr13", 158, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr14", 159, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr15", 160, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr16", 161, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr17", 162, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr18", 163, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr19", 164, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr20", 165, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr21", 166, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr22", 167, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr23", 168, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr24", 169, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr25", 170, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr26", 171, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr27", 172, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr28", 173, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr29", 174, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr30", 175, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cr31", 176, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "ccr", 177, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "cxer", 178, 0, NULL, 32, "uint32");
+ tdesc_create_reg (feature, "clr", 179, 0, NULL, 64, "code_ptr");
+ tdesc_create_reg (feature, "cctr", 180, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cf0", 181, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf1", 182, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf2", 183, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf3", 184, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf4", 185, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf5", 186, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf6", 187, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf7", 188, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf8", 189, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf9", 190, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf10", 191, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf11", 192, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf12", 193, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf13", 194, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf14", 195, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf15", 196, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf16", 197, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf17", 198, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf18", 199, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf19", 200, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf20", 201, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf21", 202, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf22", 203, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf23", 204, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf24", 205, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf25", 206, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf26", 207, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf27", 208, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf28", 209, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf29", 210, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf30", 211, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cf31", 212, 0, NULL, 64, "ieee_double");
+ tdesc_create_reg (feature, "cfpscr", 213, 0, "float", 64, "uint64");
+ tdesc_create_reg (feature, "cvr0", 214, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr1", 215, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr2", 216, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr3", 217, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr4", 218, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr5", 219, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr6", 220, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr7", 221, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr8", 222, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr9", 223, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr10", 224, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr11", 225, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr12", 226, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr13", 227, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr14", 228, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr15", 229, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr16", 230, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr17", 231, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr18", 232, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr19", 233, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr20", 234, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr21", 235, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr22", 236, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr23", 237, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr24", 238, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr25", 239, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr26", 240, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr27", 241, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr28", 242, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr29", 243, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr30", 244, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvr31", 245, 0, NULL, 128, "vec128");
+ tdesc_create_reg (feature, "cvscr", 246, 0, NULL, 32, "int");
+ tdesc_create_reg (feature, "cvrsave", 247, 0, NULL, 32, "int");
+ tdesc_create_reg (feature, "cvs0h", 248, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs1h", 249, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs2h", 250, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs3h", 251, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs4h", 252, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs5h", 253, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs6h", 254, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs7h", 255, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs8h", 256, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs9h", 257, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs10h", 258, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs11h", 259, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs12h", 260, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs13h", 261, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs14h", 262, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs15h", 263, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs16h", 264, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs17h", 265, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs18h", 266, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs19h", 267, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs20h", 268, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs21h", 269, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs22h", 270, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs23h", 271, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs24h", 272, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs25h", 273, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs26h", 274, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs27h", 275, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs28h", 276, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs29h", 277, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs30h", 278, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cvs31h", 279, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cppr", 280, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "cdscr", 281, 0, NULL, 64, "uint64");
+ tdesc_create_reg (feature, "ctar", 282, 0, NULL, 64, "uint64");
+
+ tdesc_powerpc_isa207_htm_vsx64l = result;
+}
diff --git a/gdb/features/rs6000/powerpc-isa207-htm-vsx64l.xml b/gdb/features/rs6000/powerpc-isa207-htm-vsx64l.xml
new file mode 100644
index 0000000000..e1649d0d9e
--- /dev/null
+++ b/gdb/features/rs6000/powerpc-isa207-htm-vsx64l.xml
@@ -0,0 +1,20 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>powerpc:common64</architecture>
+ <xi:include href="power64-core.xml"/>
+ <xi:include href="power-fpu-isa205.xml"/>
+ <xi:include href="power64-linux.xml"/>
+ <xi:include href="power-altivec.xml"/>
+ <xi:include href="power-vsx.xml"/>
+ <xi:include href="power-ppr.xml"/>
+ <xi:include href="power-dscr.xml"/>
+ <xi:include href="power-tar.xml"/>
+ <xi:include href="power64-htm.xml"/>
+</target>
diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
index 0cb50627aa..6559ab1643 100644
--- a/gdb/gdbserver/configure.srv
+++ b/gdb/gdbserver/configure.srv
@@ -32,7 +32,7 @@ else
srv_amd64_linux_regobj=""
fi
-ipa_ppc_linux_regobj="powerpc-32l-ipa.o powerpc-altivec32l-ipa.o powerpc-cell32l-ipa.o powerpc-vsx32l-ipa.o powerpc-isa205-32l-ipa.o powerpc-isa205-altivec32l-ipa.o powerpc-isa205-vsx32l-ipa.o powerpc-isa205-ppr-dscr-vsx32l-ipa.o powerpc-isa207-vsx32l-ipa.o powerpc-e500l-ipa.o powerpc-64l-ipa.o powerpc-altivec64l-ipa.o powerpc-cell64l-ipa.o powerpc-vsx64l-ipa.o powerpc-isa205-64l-ipa.o powerpc-isa205-altivec64l-ipa.o powerpc-isa205-vsx64l-ipa.o powerpc-isa205-ppr-dscr-vsx64l-ipa.o powerpc-isa207-vsx64l-ipa.o"
+ipa_ppc_linux_regobj="powerpc-32l-ipa.o powerpc-altivec32l-ipa.o powerpc-cell32l-ipa.o powerpc-vsx32l-ipa.o powerpc-isa205-32l-ipa.o powerpc-isa205-altivec32l-ipa.o powerpc-isa205-vsx32l-ipa.o powerpc-isa205-ppr-dscr-vsx32l-ipa.o powerpc-isa207-vsx32l-ipa.o powerpc-isa207-htm-vsx32l-ipa.o powerpc-e500l-ipa.o powerpc-64l-ipa.o powerpc-altivec64l-ipa.o powerpc-cell64l-ipa.o powerpc-vsx64l-ipa.o powerpc-isa205-64l-ipa.o powerpc-isa205-altivec64l-ipa.o powerpc-isa205-vsx64l-ipa.o powerpc-isa205-ppr-dscr-vsx64l-ipa.o powerpc-isa207-vsx64l-ipa.o powerpc-isa207-htm-vsx64l-ipa.o"
# Linux object files. This is so we don't have to repeat
# these files over and over again.
@@ -219,6 +219,7 @@ case "${target}" in
srv_regobj="${srv_regobj} powerpc-isa205-vsx32l.o"
srv_regobj="${srv_regobj} powerpc-isa205-ppr-dscr-vsx32l.o"
srv_regobj="${srv_regobj} powerpc-isa207-vsx32l.o"
+ srv_regobj="${srv_regobj} powerpc-isa207-htm-vsx32l.o"
srv_regobj="${srv_regobj} powerpc-e500l.o"
srv_regobj="${srv_regobj} powerpc-64l.o"
srv_regobj="${srv_regobj} powerpc-altivec64l.o"
@@ -229,6 +230,7 @@ case "${target}" in
srv_regobj="${srv_regobj} powerpc-isa205-vsx64l.o"
srv_regobj="${srv_regobj} powerpc-isa205-ppr-dscr-vsx64l.o"
srv_regobj="${srv_regobj} powerpc-isa207-vsx64l.o"
+ srv_regobj="${srv_regobj} powerpc-isa207-htm-vsx64l.o"
srv_tgtobj="$srv_linux_obj linux-ppc-low.o ppc-linux.o"
srv_tgtobj="${srv_tgtobj} arch/ppc-linux-common.o"
srv_xmlfiles="rs6000/powerpc-32l.xml"
@@ -240,6 +242,7 @@ case "${target}" in
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-vsx32l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-ppr-dscr-vsx32l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa207-vsx32l.xml"
+ srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa207-htm-vsx32l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-altivec.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-vsx.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-core.xml"
@@ -249,6 +252,7 @@ case "${target}" in
srv_xmlfiles="${srv_xmlfiles} rs6000/power-dscr.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-ppr.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-tar.xml"
+ srv_xmlfiles="${srv_xmlfiles} rs6000/power-htm.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-e500l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power-spe.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-64l.xml"
@@ -260,8 +264,10 @@ case "${target}" in
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-vsx64l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa205-ppr-dscr-vsx64l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa207-vsx64l.xml"
+ srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-isa207-htm-vsx64l.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power64-core.xml"
srv_xmlfiles="${srv_xmlfiles} rs6000/power64-linux.xml"
+ srv_xmlfiles="${srv_xmlfiles} rs6000/power64-htm.xml"
srv_linux_usrregs=yes
srv_linux_regsets=yes
srv_linux_thread_db=yes
diff --git a/gdb/nat/ppc-linux.h b/gdb/nat/ppc-linux.h
index 913a9e0bd8..44b76e2891 100644
--- a/gdb/nat/ppc-linux.h
+++ b/gdb/nat/ppc-linux.h
@@ -60,6 +60,9 @@
#ifndef PPC_FEATURE2_TAR
#define PPC_FEATURE2_TAR 0x04000000
#endif
+#ifndef PPC_FEATURE2_HTM
+#define PPC_FEATURE2_HTM 0x40000000
+#endif
/* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
configure time check. Some older glibc's (for instance 2.2.1)
@@ -106,6 +109,46 @@
#define NT_PPC_DSCR 0x105
#endif
+/* TM checkpointed GPR Registers. */
+#ifndef NT_PPC_TM_CGPR
+#define NT_PPC_TM_CGPR 0x108
+#endif
+
+/* TM checkpointed FPR Registers. */
+#ifndef NT_PPC_TM_CFPR
+#define NT_PPC_TM_CFPR 0x109
+#endif
+
+/* TM checkpointed VMX Registers. */
+#ifndef NT_PPC_TM_CVMX
+#define NT_PPC_TM_CVMX 0x10a
+#endif
+
+/* TM checkpointed VSX Registers. */
+#ifndef NT_PPC_TM_CVSX
+#define NT_PPC_TM_CVSX 0x10b
+#endif
+
+/* TM Special Purpose Registers. */
+#ifndef NT_PPC_TM_SPR
+#define NT_PPC_TM_SPR 0x10c
+#endif
+
+/* TM checkpointed Target Address Register. */
+#ifndef NT_PPC_TM_CTAR
+#define NT_PPC_TM_CTAR 0x10d
+#endif
+
+/* TM checkpointed Program Priority Register. */
+#ifndef NT_PPC_TM_CPPR
+#define NT_PPC_TM_CPPR 0x10e
+#endif
+
+/* TM checkpointed Data Stream Control Register. */
+#ifndef NT_PPC_TM_CDSCR
+#define NT_PPC_TM_CDSCR 0x10f
+#endif
+
/* Return the wordsize of the target, either 4 or 8 bytes. */
int ppc_linux_target_wordsize (int tid);
diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c
index 390df17c10..b084934b22 100644
--- a/gdb/ppc-linux-nat.c
+++ b/gdb/ppc-linux-nat.c
@@ -667,6 +667,83 @@ fetch_register (struct regcache *regcache, int tid, int regno)
&ppc32_linux_tarregset);
return;
}
+ else if (PPC_IS_TMSPR_REGNUM (regno))
+ {
+ gdb_assert (tdep->have_htm);
+
+ fetch_regset (regcache, tid, NT_PPC_TM_SPR,
+ PPC_LINUX_SIZEOF_TM_SPRREGSET,
+ &ppc32_linux_tm_sprregset);
+ return;
+ }
+ else if (PPC_IS_CKPTGP_REGNUM (regno))
+ {
+ gdb_assert (tdep->have_htm);
+
+ const struct regset cgprregset =
+ ppc_linux_cgprregset (gdbarch, false);
+
+ fetch_regset (regcache, tid, NT_PPC_TM_CGPR,
+ tdep->wordsize == 4? PPC32_LINUX_SIZEOF_CGPRREGSET
+ : PPC64_LINUX_SIZEOF_CGPRREGSET,
+ &cgprregset);
+ return;
+ }
+ else if (PPC_IS_CKPTFP_REGNUM (regno))
+ {
+ gdb_assert (tdep->have_htm);
+
+ fetch_regset (regcache, tid, NT_PPC_TM_CFPR,
+ PPC_LINUX_SIZEOF_CFPRREGSET,
+ &ppc32_linux_cfprregset);
+ return;
+ }
+ else if (PPC_IS_CKPTVMX_REGNUM (regno))
+ {
+ gdb_assert (tdep->have_htm);
+
+ const struct regset *cvmxregset = ppc_linux_cvmxregset (gdbarch);
+ fetch_regset (regcache, tid, NT_PPC_TM_CVMX,
+ PPC_LINUX_SIZEOF_CVMXREGSET,
+ cvmxregset);
+ return;
+ }
+ else if (PPC_IS_CKPTVSX_REGNUM (regno))
+ {
+ gdb_assert (tdep->have_htm);
+
+ fetch_regset (regcache, tid, NT_PPC_TM_CVSX,
+ PPC_LINUX_SIZEOF_CVSXREGSET,
+ &ppc32_linux_cvsxregset);
+ return;
+ }
+ else if (regno == PPC_CPPR_REGNUM)
+ {
+ gdb_assert (tdep->have_htm);
+
+ fetch_regset (regcache, tid, NT_PPC_TM_CPPR,
+ PPC_LINUX_SIZEOF_CPPRREGSET,
+ &ppc32_linux_cpprregset);
+ return;
+ }
+ else if (regno == PPC_CDSCR_REGNUM)
+ {
+ gdb_assert (tdep->have_htm);
+
+ fetch_regset (regcache, tid, NT_PPC_TM_CDSCR,
+ PPC_LINUX_SIZEOF_CDSCRREGSET,
+ &ppc32_linux_cdscrregset);
+ return;
+ }
+ else if (regno == PPC_CTAR_REGNUM)
+ {
+ gdb_assert (tdep->have_htm);
+
+ fetch_regset (regcache, tid, NT_PPC_TM_CTAR,
+ PPC_LINUX_SIZEOF_CTARREGSET,
+ &ppc32_linux_ctarregset);
+ return;
+ }
if (regaddr == -1)
{
@@ -875,6 +952,43 @@ fetch_ppc_registers (struct regcache *regcache, int tid)
fetch_regset (regcache, tid, NT_PPC_TAR,
PPC_LINUX_SIZEOF_TARREGSET,
&ppc32_linux_tarregset);
+
+ if (tdep->have_htm)
+ {
+ fetch_regset (regcache, tid, NT_PPC_TM_SPR,
+ PPC_LINUX_SIZEOF_TM_SPRREGSET,
+ &ppc32_linux_tm_sprregset);
+
+ const struct regset cgprregset =
+ ppc_linux_cgprregset (gdbarch, false);
+
+ fetch_regset (regcache, tid, NT_PPC_TM_CGPR,
+ tdep->wordsize == 4? PPC32_LINUX_SIZEOF_CGPRREGSET
+ : PPC64_LINUX_SIZEOF_CGPRREGSET,
+ &cgprregset);
+
+ fetch_regset (regcache, tid, NT_PPC_TM_CFPR,
+ PPC_LINUX_SIZEOF_CFPRREGSET,
+ &ppc32_linux_cfprregset);
+
+ const struct regset *cvmxregset = ppc_linux_cvmxregset (gdbarch);
+ fetch_regset (regcache, tid, NT_PPC_TM_CVMX,
+ PPC_LINUX_SIZEOF_CVMXREGSET,
+ cvmxregset);
+
+ fetch_regset (regcache, tid, NT_PPC_TM_CVSX,
+ PPC_LINUX_SIZEOF_CVSXREGSET,
+ &ppc32_linux_cvsxregset);
+ fetch_regset (regcache, tid, NT_PPC_TM_CPPR,
+ PPC_LINUX_SIZEOF_CPPRREGSET,
+ &ppc32_linux_cpprregset);
+ fetch_regset (regcache, tid, NT_PPC_TM_CDSCR,
+ PPC_LINUX_SIZEOF_CDSCRREGSET,
+ &ppc32_linux_cdscrregset);
+ fetch_regset (regcache, tid, NT_PPC_TM_CTAR,
+ PPC_LINUX_SIZEOF_CTARREGSET,
+ &ppc32_linux_ctarregset);
+ }
}
/* Fetch registers from the child process. Fetch all registers if
@@ -1082,6 +1196,83 @@ store_register (const struct regcache *regcache, int tid, int regno)
&ppc32_linux_tarregset);
return;
}
+ else if (PPC_IS_TMSPR_REGNUM (regno))
+ {
+ gdb_assert (tdep->have_htm);
+
+ store_regset (regcache, tid, regno, NT_PPC_TM_SPR,
+ PPC_LINUX_SIZEOF_TM_SPRREGSET,
+ &ppc32_linux_tm_sprregset);
+ return;
+ }
+ else if (PPC_IS_CKPTGP_REGNUM (regno))
+ {
+ gdb_assert (tdep->have_htm);
+
+ const struct regset cgprregset =
+ ppc_linux_cgprregset (gdbarch, false);
+
+ store_regset (regcache, tid, regno, NT_PPC_TM_CGPR,
+ tdep->wordsize == 4? PPC32_LINUX_SIZEOF_CGPRREGSET
+ : PPC64_LINUX_SIZEOF_CGPRREGSET,
+ &cgprregset);
+ return;
+ }
+ else if (PPC_IS_CKPTFP_REGNUM (regno))
+ {
+ gdb_assert (tdep->have_htm);
+
+ store_regset (regcache, tid, regno, NT_PPC_TM_CFPR,
+ PPC_LINUX_SIZEOF_CFPRREGSET,
+ &ppc32_linux_cfprregset);
+ return;
+ }
+ else if (PPC_IS_CKPTVMX_REGNUM (regno))
+ {
+ gdb_assert (tdep->have_htm);
+
+ const struct regset *cvmxregset = ppc_linux_cvmxregset (gdbarch);
+ store_regset (regcache, tid, regno, NT_PPC_TM_CVMX,
+ PPC_LINUX_SIZEOF_CVMXREGSET,
+ cvmxregset);
+ return;
+ }
+ else if (PPC_IS_CKPTVSX_REGNUM (regno))
+ {
+ gdb_assert (tdep->have_htm);
+
+ store_regset (regcache, tid, regno, NT_PPC_TM_CVSX,
+ PPC_LINUX_SIZEOF_CVSXREGSET,
+ &ppc32_linux_cvsxregset);
+ return;
+ }
+ else if (regno == PPC_CPPR_REGNUM)
+ {
+ gdb_assert (tdep->have_htm);
+
+ store_regset (regcache, tid, regno, NT_PPC_TM_CPPR,
+ PPC_LINUX_SIZEOF_CPPRREGSET,
+ &ppc32_linux_cpprregset);
+ return;
+ }
+ else if (regno == PPC_CDSCR_REGNUM)
+ {
+ gdb_assert (tdep->have_htm);
+
+ store_regset (regcache, tid, regno, NT_PPC_TM_CDSCR,
+ PPC_LINUX_SIZEOF_CDSCRREGSET,
+ &ppc32_linux_cdscrregset);
+ return;
+ }
+ else if (regno == PPC_CTAR_REGNUM)
+ {
+ gdb_assert (tdep->have_htm);
+
+ store_regset (regcache, tid, regno, NT_PPC_TM_CTAR,
+ PPC_LINUX_SIZEOF_CTARREGSET,
+ &ppc32_linux_ctarregset);
+ return;
+ }
if (regaddr == -1)
return;
@@ -1258,6 +1449,50 @@ store_fp_regs (const struct regcache *regcache, int tid, int regno)
store_register (regcache, tid, tdep->ppc_fp0_regnum + i);
}
+/* Returns true if all the registers in REGSET are valid in REGCACHE,
+ false if no registers are valid, and throws an internal error if
+ only some are valid. The regmap field in REGSET must be of type
+ regcache_map_entry. */
+
+static bool
+ppc_linux_regset_available_p (const struct regcache *regcache,
+ const struct regset *regset)
+{
+ struct gdbarch *gdbarch = regcache->arch ();
+ const struct regcache_map_entry *map;
+ int count;
+ int valid = 0;
+ int total = 0;
+
+ for (map = (const struct regcache_map_entry *) regset->regmap;
+ (count = map->count) != 0;
+ map++)
+ {
+ int regno = map->regno;
+
+ /* Ignore REGCACHE_MAP_SKIP. */
+ if (regno >= 0 && regno < gdbarch_num_regs (gdbarch))
+ {
+ for (int i = regno; i < regno + count; i++)
+ {
+ if (regcache->get_register_status (i) == REG_VALID)
+ valid++;
+ total++;
+ }
+ }
+ }
+
+ if (valid > 0 && valid < total)
+ internal_error (__FILE__, __LINE__,
+ _("Only some registers in a regset"
+ "are valid."));
+
+ if (valid == total)
+ return true;
+ else
+ return false;
+}
+
static void
store_ppc_registers (const struct regcache *regcache, int tid)
{
@@ -1308,6 +1543,67 @@ store_ppc_registers (const struct regcache *regcache, int tid)
store_regset (regcache, tid, -1, NT_PPC_TAR,
PPC_LINUX_SIZEOF_TARREGSET,
&ppc32_linux_tarregset);
+
+ if (tdep->have_htm)
+ {
+ store_regset (regcache, tid, -1, NT_PPC_TM_SPR,
+ PPC_LINUX_SIZEOF_TM_SPRREGSET,
+ &ppc32_linux_tm_sprregset);
+
+ /* Checkpointed registers are unavailable if the inferior is not
+ in a transaction, which would cause calls to store_regset to
+ fail. Only try to store them if they are all valid in the
+ regcache. */
+
+ const struct regset cgprregset =
+ ppc_linux_cgprregset (gdbarch, false);
+
+ if (ppc_linux_regset_available_p (regcache, &cgprregset))
+ store_regset (regcache, tid, -1, NT_PPC_TM_CGPR,
+ tdep->wordsize == 4?
+ PPC32_LINUX_SIZEOF_CGPRREGSET
+ : PPC64_LINUX_SIZEOF_CGPRREGSET,
+ &cgprregset);
+
+ if (ppc_linux_regset_available_p (regcache,
+ &ppc32_linux_cfprregset))
+ store_regset (regcache, tid, -1, NT_PPC_TM_CFPR,
+ PPC_LINUX_SIZEOF_CFPRREGSET,
+ &ppc32_linux_cfprregset);
+
+ const struct regset *cvmxregset =
+ ppc_linux_cvmxregset (gdbarch);
+
+ if (ppc_linux_regset_available_p (regcache, cvmxregset))
+ store_regset (regcache, tid, -1, NT_PPC_TM_CVMX,
+ PPC_LINUX_SIZEOF_CVMXREGSET,
+ cvmxregset);
+
+ if (ppc_linux_regset_available_p (regcache,
+ &ppc32_linux_cvsxregset))
+ store_regset (regcache, tid, -1, NT_PPC_TM_CVSX,
+ PPC_LINUX_SIZEOF_CVSXREGSET,
+ &ppc32_linux_cvsxregset);
+
+ if (ppc_linux_regset_available_p (regcache,
+ &ppc32_linux_cpprregset))
+ store_regset (regcache, tid, -1, NT_PPC_TM_CPPR,
+ PPC_LINUX_SIZEOF_CPPRREGSET,
+ &ppc32_linux_cpprregset);
+
+ if (ppc_linux_regset_available_p (regcache,
+ &ppc32_linux_cdscrregset))
+ store_regset (regcache, tid, -1, NT_PPC_TM_CDSCR,
+ PPC_LINUX_SIZEOF_CDSCRREGSET,
+ &ppc32_linux_cdscrregset);
+
+ if (ppc_linux_regset_available_p (regcache,
+ &ppc32_linux_ctarregset))
+ store_regset (regcache, tid, -1, NT_PPC_TM_CTAR,
+ PPC_LINUX_SIZEOF_CTARREGSET,
+ &ppc32_linux_ctarregset);
+
+ }
}
/* Fetch the AT_HWCAP entry from the aux vector. */
@@ -2439,7 +2735,13 @@ ppc_linux_nat_target::read_description ()
if ((hwcap2 & PPC_FEATURE2_ARCH_2_07)
&& (hwcap2 & PPC_FEATURE2_TAR)
&& check_regset (tid, NT_PPC_TAR, PPC_LINUX_SIZEOF_TARREGSET))
- features.isa207 = true;
+ {
+ features.isa207 = true;
+ if ((hwcap2 & PPC_FEATURE2_HTM)
+ && check_regset (tid, NT_PPC_TM_SPR,
+ PPC_LINUX_SIZEOF_TM_SPRREGSET))
+ features.htm = true;
+ }
}
return ppc_linux_match_description (features);
diff --git a/gdb/ppc-linux-tdep.c b/gdb/ppc-linux-tdep.c
index 9d952c3388..74e4eec413 100644
--- a/gdb/ppc-linux-tdep.c
+++ b/gdb/ppc-linux-tdep.c
@@ -73,6 +73,7 @@
#include "features/rs6000/powerpc-isa205-vsx32l.c"
#include "features/rs6000/powerpc-isa205-ppr-dscr-vsx32l.c"
#include "features/rs6000/powerpc-isa207-vsx32l.c"
+#include "features/rs6000/powerpc-isa207-htm-vsx32l.c"
#include "features/rs6000/powerpc-64l.c"
#include "features/rs6000/powerpc-altivec64l.c"
#include "features/rs6000/powerpc-cell64l.c"
@@ -82,6 +83,7 @@
#include "features/rs6000/powerpc-isa205-vsx64l.c"
#include "features/rs6000/powerpc-isa205-ppr-dscr-vsx64l.c"
#include "features/rs6000/powerpc-isa207-vsx64l.c"
+#include "features/rs6000/powerpc-isa207-htm-vsx64l.c"
#include "features/rs6000/powerpc-e500l.c"
/* Shared library operations for PowerPC-Linux. */
@@ -457,15 +459,29 @@ ppc_linux_collect_vrregset (const struct regset *regset,
/* Zero-pad the unused bytes in the fields for vscr and vrsave
in case they get displayed somewhere (e.g. in core files). */
- if (regnum == PPC_VSCR_REGNUM || regnum == -1)
+ if (regnum == PPC_VSCR_REGNUM || regnum == PPC_CVSCR_REGNUM
+ || regnum == -1)
memset (&vrregs[32 * 16], 0, 16);
- if (regnum == PPC_VRSAVE_REGNUM || regnum == -1)
+ if (regnum == PPC_VRSAVE_REGNUM || regnum == PPC_CVRSAVE_REGNUM
+ || regnum == -1)
memset (&vrregs[33 * 16], 0, 16);
regcache_collect_regset (regset, regcache, regnum, buf, len);
}
+static void
+ppc_linux_collect_and_clear_cgprregset (const struct regset *regset,
+ const struct regcache *regcache,
+ int regnum, void *buf,
+ size_t len)
+{
+ if (regnum == -1)
+ memset (buf, 0, len);
+
+ regcache_collect_regset (regset, regcache, regnum, buf, len);
+}
+
/* Regset descriptions. */
static const struct ppc_reg_offsets ppc32_linux_reg_offsets =
{
@@ -525,6 +541,116 @@ static const struct regcache_map_entry ppc32_regmap_tar[] =
{ 0 }
};
+static const struct regcache_map_entry ppc32_regmap_tm_spr[] =
+ {
+ { 1, PPC_TFHAR_REGNUM, 8 },
+ { 1, PPC_TEXASR_REGNUM, 8 },
+ { 1, PPC_TFIAR_REGNUM, 8 },
+ { 0 }
+ };
+
+/* The layout of checkpointed CGPR regset is the same as a regular
+ struct pt_regs, but we skip all registers that are not actually
+ checkpointed by the processor (e.g. msr, nip). The 64-bit regset
+ is 48 * 8 bytes long. If the kernel is 64-bit, the regset for a
+ 32-bit inferior has the same length, but all the registers are
+ squeezed in the first half (48 * 4 bytes). The pt_regs struct
+ calls the regular cr ccr, but we use ccr for "checkpointed
+ condition register". Note that CR0 is not checkpointed. The
+ skipped regisers should not be touched when writing the regset to
+ the inferior (with PTRACE_SETREGSET). */
+
+static const struct regcache_map_entry ppc32_regmap_cgpr[] =
+ {
+ { 32, PPC_CR0_REGNUM, 4 },
+ { 3, REGCACHE_MAP_SKIP, 4 }, /* nip, msr, orig_gpr3. */
+ { 1, PPC_CCTR_REGNUM, 4 },
+ { 1, PPC_CLR_REGNUM, 4 },
+ { 1, PPC_CXER_REGNUM, 4 },
+ { 1, PPC_CCR_REGNUM, 4 },
+ { 9, REGCACHE_MAP_SKIP, 4 }, /* All the rest. */
+ { 0 }
+ };
+
+static const struct regcache_map_entry ppc64_le_regmap_cgpr[] =
+ {
+ { 32, PPC_CR0_REGNUM, 8 },
+ { 3, REGCACHE_MAP_SKIP, 8 },
+ { 1, PPC_CCTR_REGNUM, 8 },
+ { 1, PPC_CLR_REGNUM, 8 },
+ { 1, PPC_CXER_REGNUM, 4 },
+ { 1, REGCACHE_MAP_SKIP, 4 }, /* CXER padding. */
+ { 1, PPC_CCR_REGNUM, 4 },
+ { 1, REGCACHE_MAP_SKIP, 4}, /* CCR padding. */
+ { 9, REGCACHE_MAP_SKIP, 8},
+ { 0 }
+ };
+
+static const struct regcache_map_entry ppc64_be_regmap_cgpr[] =
+ {
+ { 32, PPC_CR0_REGNUM, 8 },
+ { 3, REGCACHE_MAP_SKIP, 8 },
+ { 1, PPC_CCTR_REGNUM, 8 },
+ { 1, PPC_CLR_REGNUM, 8 },
+ { 1, REGCACHE_MAP_SKIP, 4}, /* CXER padding. */
+ { 1, PPC_CXER_REGNUM, 4 },
+ { 1, REGCACHE_MAP_SKIP, 4}, /* CCR padding. */
+ { 1, PPC_CCR_REGNUM, 4 },
+ { 9, REGCACHE_MAP_SKIP, 8},
+ { 0 }
+ };
+
+static const struct regcache_map_entry ppc32_regmap_cfpr[] =
+ {
+ { 32, PPC_CF0_REGNUM, 8 },
+ { 1, PPC_CFPSCR_REGNUM, 8 },
+ { 0 }
+ };
+
+static const struct regcache_map_entry ppc32_le_regmap_cvmx[] =
+ {
+ { 32, PPC_CVR0_REGNUM, 16 },
+ { 1, PPC_CVSCR_REGNUM, 4 },
+ { 1, REGCACHE_MAP_SKIP, 12 },
+ { 1, PPC_CVRSAVE_REGNUM, 4 },
+ { 1, REGCACHE_MAP_SKIP, 12 },
+ { 0 }
+ };
+
+static const struct regcache_map_entry ppc32_be_regmap_cvmx[] =
+ {
+ { 32, PPC_CVR0_REGNUM, 16 },
+ { 1, REGCACHE_MAP_SKIP, 12 },
+ { 1, PPC_CVSCR_REGNUM, 4 },
+ { 1, PPC_CVRSAVE_REGNUM, 4 },
+ { 1, REGCACHE_MAP_SKIP, 12},
+ { 0 }
+ };
+
+static const struct regcache_map_entry ppc32_regmap_cvsx[] =
+ {
+ { 32, PPC_CVS0H_REGNUM, 8 },
+ { 0 }
+ };
+
+static const struct regcache_map_entry ppc32_regmap_cppr[] =
+ {
+ { 1, PPC_CPPR_REGNUM, 8 },
+ { 0 }
+ };
+
+static const struct regcache_map_entry ppc32_regmap_cdscr[] =
+ {
+ { 1, PPC_CDSCR_REGNUM, 8 },
+ { 0 }
+ };
+
+static const struct regcache_map_entry ppc32_regmap_ctar[] =
+ {
+ { 1, PPC_CTAR_REGNUM, 8 },
+ { 0 }
+ };
+
static const struct regset ppc32_linux_gregset = {
&ppc32_linux_reg_offsets,
ppc_linux_supply_gregset,
@@ -605,6 +731,54 @@ const struct regset ppc32_linux_tarregset = {
regcache_collect_regset
};
+const struct regset ppc32_linux_tm_sprregset = {
+ ppc32_regmap_tm_spr,
+ regcache_supply_regset,
+ regcache_collect_regset
+};
+
+const struct regset ppc32_linux_cfprregset = {
+ ppc32_regmap_cfpr,
+ regcache_supply_regset,
+ regcache_collect_regset
+};
+
+static const struct regset ppc32_le_linux_cvmxregset = {
+ ppc32_le_regmap_cvmx,
+ regcache_supply_regset,
+ ppc_linux_collect_vrregset
+};
+
+static const struct regset ppc32_be_linux_cvmxregset = {
+ ppc32_be_regmap_cvmx,
+ regcache_supply_regset,
+ ppc_linux_collect_vrregset
+};
+
+const struct regset ppc32_linux_cvsxregset = {
+ ppc32_regmap_cvsx,
+ regcache_supply_regset,
+ regcache_collect_regset
+};
+
+const struct regset ppc32_linux_cpprregset = {
+ ppc32_regmap_cppr,
+ regcache_supply_regset,
+ regcache_collect_regset
+};
+
+const struct regset ppc32_linux_cdscrregset = {
+ ppc32_regmap_cdscr,
+ regcache_supply_regset,
+ regcache_collect_regset
+};
+
+const struct regset ppc32_linux_ctarregset = {
+ ppc32_regmap_ctar,
+ regcache_supply_regset,
+ regcache_collect_regset
+};
+
const struct regset *
ppc_linux_gregset (int wordsize)
{
@@ -632,6 +806,46 @@ ppc_linux_vsxregset (void)
return &ppc32_linux_vsxregset;
}
+const struct regset
+ppc_linux_cgprregset (struct gdbarch *gdbarch, bool clear_on_collect)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ struct regset ret;
+
+ ret.flags = 0;
+
+ if (tdep->wordsize == 4)
+ {
+ ret.regmap = ppc32_regmap_cgpr;
+ ret.flags = REGSET_VARIABLE_SIZE;
+ }
+ else
+ {
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+ ret.regmap = ppc64_be_regmap_cgpr;
+ else
+ ret.regmap = ppc64_le_regmap_cgpr;
+ }
+
+ ret.supply_regset = regcache_supply_regset;
+
+ if (clear_on_collect)
+ ret.collect_regset = ppc_linux_collect_and_clear_cgprregset;
+ else
+ ret.collect_regset = regcache_collect_regset;
+
+ return ret;
+}
+
+const struct regset *
+ppc_linux_cvmxregset (struct gdbarch *gdbarch)
+{
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+ return &ppc32_be_linux_cvmxregset;
+ else
+ return &ppc32_le_linux_cvmxregset;
+}
+
/* Iterate over supported core file register note sections. */
static void
@@ -677,6 +891,71 @@ ppc_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
if (have_tar)
cb (".reg-ppc-tar", PPC_LINUX_SIZEOF_TARREGSET,
&ppc32_linux_tarregset, "Target Address Register", cb_data);
+
+ if (tdep->have_htm)
+ {
+ cb (".reg-ppc-tm-spr", PPC_LINUX_SIZEOF_TM_SPRREGSET,
+ &ppc32_linux_tm_sprregset,
+ "Hardware Transactional Memory Special Purpose Registers",
+ cb_data);
+
+ /* Checkpointed registers can be unavailable, don't call back if
+ we are generating a core file. */
+
+ if (regcache == NULL ||
+ REG_VALID == regcache->get_register_status (PPC_CR0_REGNUM))
+ {
+ const struct regset cgprregset =
+ ppc_linux_cgprregset (gdbarch, regcache != NULL);
+
+ cb (".reg-ppc-tm-cgpr",
+ tdep->wordsize == 4? PPC32_LINUX_SIZEOF_CGPRREGSET
+ : PPC64_LINUX_SIZEOF_CGPRREGSET,
+ &cgprregset,
+ "Checkpointed General Purpose Registers", cb_data);
+ }
+
+ if (regcache == NULL ||
+ REG_VALID == regcache->get_register_status (PPC_CF0_REGNUM))
+ cb (".reg-ppc-tm-cfpr", PPC_LINUX_SIZEOF_CFPRREGSET,
+ &ppc32_linux_cfprregset,
+ "Checkpointed Floating Point Registers", cb_data);
+
+ if (regcache == NULL ||
+ REG_VALID == regcache->get_register_status (PPC_CVR0_REGNUM))
+ {
+ const struct regset *cvmxregset =
+ ppc_linux_cvmxregset (gdbarch);
+
+ cb (".reg-ppc-tm-cvmx", PPC_LINUX_SIZEOF_CVMXREGSET,
+ cvmxregset,
+ "Checkpointed Altivec (VMX) Registers", cb_data);
+ }
+
+ if (regcache == NULL ||
+ REG_VALID == regcache->get_register_status (PPC_CVS0H_REGNUM))
+ cb (".reg-ppc-tm-cvsx", PPC_LINUX_SIZEOF_CVSXREGSET,
+ &ppc32_linux_cvsxregset,
+ "Checkpointed VSX Registers", cb_data);
+
+ if (regcache == NULL ||
+ REG_VALID == regcache->get_register_status (PPC_CPPR_REGNUM))
+ cb (".reg-ppc-tm-cppr", PPC_LINUX_SIZEOF_CPPRREGSET,
+ &ppc32_linux_cpprregset,
+ "Checkpointed Priority Program Register", cb_data);
+
+ if (regcache == NULL ||
+ REG_VALID == regcache->get_register_status (PPC_CDSCR_REGNUM))
+ cb (".reg-ppc-tm-cdscr", PPC_LINUX_SIZEOF_CDSCRREGSET,
+ &ppc32_linux_cdscrregset,
+ "Checkpointed Data Stream Control Register", cb_data);
+
+ if ( regcache == NULL ||
+ REG_VALID == regcache->get_register_status (PPC_CTAR_REGNUM))
+ cb (".reg-ppc-tm-ctar", PPC_LINUX_SIZEOF_CTARREGSET,
+ &ppc32_linux_ctarregset,
+ "Checkpointed Target Address Register", cb_data);
+ }
}
static void
@@ -1092,6 +1371,7 @@ ppc_linux_core_read_description (struct gdbarch *gdbarch,
asection *ppr = bfd_get_section_by_name (abfd, ".reg-ppc-ppr");
asection *dscr = bfd_get_section_by_name (abfd, ".reg-ppc-dscr");
asection *tar = bfd_get_section_by_name (abfd, ".reg-ppc-tar");
+ asection *htmspr = bfd_get_section_by_name (abfd, ".reg-ppc-tm-spr");
if (! section)
return NULL;
@@ -1128,7 +1408,11 @@ ppc_linux_core_read_description (struct gdbarch *gdbarch,
{
features.ppr_dscr = true;
if (tar)
- features.isa207 = true;
+ {
+ features.isa207 = true;
+ if (htmspr)
+ features.htm = true;
+ }
}
return ppc_linux_match_description (features);
@@ -2006,6 +2290,7 @@ _initialize_ppc_linux_tdep (void)
initialize_tdesc_powerpc_isa205_vsx32l ();
initialize_tdesc_powerpc_isa205_ppr_dscr_vsx32l ();
initialize_tdesc_powerpc_isa207_vsx32l ();
+ initialize_tdesc_powerpc_isa207_htm_vsx32l ();
initialize_tdesc_powerpc_64l ();
initialize_tdesc_powerpc_altivec64l ();
initialize_tdesc_powerpc_cell64l ();
@@ -2015,5 +2300,6 @@ _initialize_ppc_linux_tdep (void)
initialize_tdesc_powerpc_isa205_vsx64l ();
initialize_tdesc_powerpc_isa205_ppr_dscr_vsx64l ();
initialize_tdesc_powerpc_isa207_vsx64l ();
+ initialize_tdesc_powerpc_isa207_htm_vsx64l ();
initialize_tdesc_powerpc_e500l ();
}
diff --git a/gdb/ppc-linux-tdep.h b/gdb/ppc-linux-tdep.h
index d6ddf69354..a68eca6d42 100644
--- a/gdb/ppc-linux-tdep.h
+++ b/gdb/ppc-linux-tdep.h
@@ -32,6 +32,17 @@ const struct regset *ppc_linux_fpregset (void);
const struct regset *ppc_linux_vrregset (struct gdbarch *gdbarch);
const struct regset *ppc_linux_vsxregset (void);
+/* Get the checkpointed GPR regset that matches the target wordsize
+ and byteorder of GDBARCH. The collect function of the returned
+ regset will clear the buffer passed to it before collecting the
+ registers to 0 if CLEAR_ON_COLLECT is true and the collect function
+ is called with regno == -1 (collect all regs in the regset). This
+ is useful for generating core files without garbage in the register
+ slots that are not seen by gdb. When collecting for storing the
+ registers in the inferior, these slots should not be cleared. */
+const struct regset ppc_linux_cgprregset (struct gdbarch *gdbarch,
+ bool clear_on_collect);
+
/* Extra register number constants. The Linux kernel stores a
"trap" code and the original value of r3 into special "registers";
these need to be saved and restored when performing an inferior
@@ -48,5 +59,16 @@ int ppc_linux_trap_reg_p (struct gdbarch *gdbarch);
extern const struct regset ppc32_linux_pprregset;
extern const struct regset ppc32_linux_dscrregset;
extern const struct regset ppc32_linux_tarregset;
+extern const struct regset ppc32_linux_tm_sprregset;
+extern const struct regset ppc32_linux_cfprregset;
+extern const struct regset ppc32_linux_cvsxregset;
+extern const struct regset ppc32_linux_cpprregset;
+extern const struct regset ppc32_linux_cdscrregset;
+extern const struct regset ppc32_linux_ctarregset;
+
+/* Get the checkpointed vector regset that matches the target byte
+ order. */
+const struct regset*
+ppc_linux_cvmxregset (struct gdbarch *gdbarch);
#endif /* PPC_LINUX_TDEP_H */
diff --git a/gdb/ppc-tdep.h b/gdb/ppc-tdep.h
index e2b968177e..ddb1c5e84b 100644
--- a/gdb/ppc-tdep.h
+++ b/gdb/ppc-tdep.h
@@ -262,6 +262,11 @@ struct gdbarch_tdep
/* Target Address Register. */
int ppc_tar_regnum;
+ int have_htm;
+
+ /* HTM pseudo registers. */
+ int ppc_cvsr0_regnum;
+
/* Decimal 128 registers. */
int ppc_dl0_regnum; /* First Decimal128 argument register pair. */
@@ -321,12 +326,51 @@ enum {
PPC_PPR_REGNUM = 172,
PPC_DSCR_REGNUM = 173,
PPC_TAR_REGNUM = 174,
+
+ /* Hardware transactional memory registers. */
+ PPC_TFHAR_REGNUM = 175,
+ PPC_TEXASR_REGNUM = 176,
+ PPC_TFIAR_REGNUM = 177,
+
+ PPC_CR0_REGNUM = 178,
+ PPC_CCR_REGNUM = 210,
+ PPC_CXER_REGNUM = 211,
+ PPC_CLR_REGNUM = 212,
+ PPC_CCTR_REGNUM = 213,
+
+ PPC_CF0_REGNUM = 214,
+ PPC_CFPSCR_REGNUM = 246,
+
+ PPC_CVR0_REGNUM = 247,
+ PPC_CVSCR_REGNUM = 279,
+ PPC_CVRSAVE_REGNUM = 280,
+
+ PPC_CVS0H_REGNUM = 281,
+
+ PPC_CPPR_REGNUM = 313,
+ PPC_CDSCR_REGNUM = 314,
+ PPC_CTAR_REGNUM = 315,
PPC_NUM_REGS
};
/* Big enough to hold the size of the largest register in bytes. */
#define PPC_MAX_REGISTER_SIZE 64
+#define PPC_IS_TMSPR_REGNUM(i) \
+ ((i) >= PPC_TFHAR_REGNUM && (i) <= PPC_TFIAR_REGNUM)
+
+#define PPC_IS_CKPTGP_REGNUM(i) \
+ ((i) >= PPC_CR0_REGNUM && (i) <= PPC_CCTR_REGNUM)
+
+#define PPC_IS_CKPTFP_REGNUM(i) \
+ ((i) >= PPC_CF0_REGNUM && (i) <= PPC_CFPSCR_REGNUM)
+
+#define PPC_IS_CKPTVMX_REGNUM(i) \
+ ((i) >= PPC_CVR0_REGNUM && (i) <= PPC_CVRSAVE_REGNUM)
+
+#define PPC_IS_CKPTVSX_REGNUM(i) \
+ ((i) >= PPC_CVS0H_REGNUM && (i) < (PPC_CVS0H_REGNUM + 32))
+
/* An instruction to match. */
struct ppc_insn_pattern
diff --git a/gdb/regformats/rs6000/powerpc-isa207-htm-vsx32l.dat b/gdb/regformats/rs6000/powerpc-isa207-htm-vsx32l.dat
new file mode 100644
index 0000000000..6f5bbad28f
--- /dev/null
+++ b/gdb/regformats/rs6000/powerpc-isa207-htm-vsx32l.dat
@@ -0,0 +1,288 @@
+# THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi :set ro:
+# Generated from: rs6000/powerpc-isa207-htm-vsx32l.xml
+name:powerpc_isa207_htm_vsx32l
+xmltarget:powerpc-isa207-htm-vsx32l.xml
+expedite:r1,pc
+32:r0
+32:r1
+32:r2
+32:r3
+32:r4
+32:r5
+32:r6
+32:r7
+32:r8
+32:r9
+32:r10
+32:r11
+32:r12
+32:r13
+32:r14
+32:r15
+32:r16
+32:r17
+32:r18
+32:r19
+32:r20
+32:r21
+32:r22
+32:r23
+32:r24
+32:r25
+32:r26
+32:r27
+32:r28
+32:r29
+32:r30
+32:r31
+64:f0
+64:f1
+64:f2
+64:f3
+64:f4
+64:f5
+64:f6
+64:f7
+64:f8
+64:f9
+64:f10
+64:f11
+64:f12
+64:f13
+64:f14
+64:f15
+64:f16
+64:f17
+64:f18
+64:f19
+64:f20
+64:f21
+64:f22
+64:f23
+64:f24
+64:f25
+64:f26
+64:f27
+64:f28
+64:f29
+64:f30
+64:f31
+32:pc
+32:msr
+32:cr
+32:lr
+32:ctr
+32:xer
+64:fpscr
+32:orig_r3
+32:trap
+128:vr0
+128:vr1
+128:vr2
+128:vr3
+128:vr4
+128:vr5
+128:vr6
+128:vr7
+128:vr8
+128:vr9
+128:vr10
+128:vr11
+128:vr12
+128:vr13
+128:vr14
+128:vr15
+128:vr16
+128:vr17
+128:vr18
+128:vr19
+128:vr20
+128:vr21
+128:vr22
+128:vr23
+128:vr24
+128:vr25
+128:vr26
+128:vr27
+128:vr28
+128:vr29
+128:vr30
+128:vr31
+32:vscr
+32:vrsave
+64:vs0h
+64:vs1h
+64:vs2h
+64:vs3h
+64:vs4h
+64:vs5h
+64:vs6h
+64:vs7h
+64:vs8h
+64:vs9h
+64:vs10h
+64:vs11h
+64:vs12h
+64:vs13h
+64:vs14h
+64:vs15h
+64:vs16h
+64:vs17h
+64:vs18h
+64:vs19h
+64:vs20h
+64:vs21h
+64:vs22h
+64:vs23h
+64:vs24h
+64:vs25h
+64:vs26h
+64:vs27h
+64:vs28h
+64:vs29h
+64:vs30h
+64:vs31h
+64:ppr
+64:dscr
+64:tar
+64:tfhar
+64:texasr
+64:tfiar
+32:cr0
+32:cr1
+32:cr2
+32:cr3
+32:cr4
+32:cr5
+32:cr6
+32:cr7
+32:cr8
+32:cr9
+32:cr10
+32:cr11
+32:cr12
+32:cr13
+32:cr14
+32:cr15
+32:cr16
+32:cr17
+32:cr18
+32:cr19
+32:cr20
+32:cr21
+32:cr22
+32:cr23
+32:cr24
+32:cr25
+32:cr26
+32:cr27
+32:cr28
+32:cr29
+32:cr30
+32:cr31
+32:ccr
+32:cxer
+32:clr
+32:cctr
+64:cf0
+64:cf1
+64:cf2
+64:cf3
+64:cf4
+64:cf5
+64:cf6
+64:cf7
+64:cf8
+64:cf9
+64:cf10
+64:cf11
+64:cf12
+64:cf13
+64:cf14
+64:cf15
+64:cf16
+64:cf17
+64:cf18
+64:cf19
+64:cf20
+64:cf21
+64:cf22
+64:cf23
+64:cf24
+64:cf25
+64:cf26
+64:cf27
+64:cf28
+64:cf29
+64:cf30
+64:cf31
+64:cfpscr
+128:cvr0
+128:cvr1
+128:cvr2
+128:cvr3
+128:cvr4
+128:cvr5
+128:cvr6
+128:cvr7
+128:cvr8
+128:cvr9
+128:cvr10
+128:cvr11
+128:cvr12
+128:cvr13
+128:cvr14
+128:cvr15
+128:cvr16
+128:cvr17
+128:cvr18
+128:cvr19
+128:cvr20
+128:cvr21
+128:cvr22
+128:cvr23
+128:cvr24
+128:cvr25
+128:cvr26
+128:cvr27
+128:cvr28
+128:cvr29
+128:cvr30
+128:cvr31
+32:cvscr
+32:cvrsave
+64:cvs0h
+64:cvs1h
+64:cvs2h
+64:cvs3h
+64:cvs4h
+64:cvs5h
+64:cvs6h
+64:cvs7h
+64:cvs8h
+64:cvs9h
+64:cvs10h
+64:cvs11h
+64:cvs12h
+64:cvs13h
+64:cvs14h
+64:cvs15h
+64:cvs16h
+64:cvs17h
+64:cvs18h
+64:cvs19h
+64:cvs20h
+64:cvs21h
+64:cvs22h
+64:cvs23h
+64:cvs24h
+64:cvs25h
+64:cvs26h
+64:cvs27h
+64:cvs28h
+64:cvs29h
+64:cvs30h
+64:cvs31h
+64:cppr
+64:cdscr
+64:ctar
diff --git a/gdb/regformats/rs6000/powerpc-isa207-htm-vsx64l.dat b/gdb/regformats/rs6000/powerpc-isa207-htm-vsx64l.dat
new file mode 100644
index 0000000000..2f3d21c4c6
--- /dev/null
+++ b/gdb/regformats/rs6000/powerpc-isa207-htm-vsx64l.dat
@@ -0,0 +1,288 @@
+# THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi :set ro:
+# Generated from: rs6000/powerpc-isa207-htm-vsx64l.xml
+name:powerpc_isa207_htm_vsx64l
+xmltarget:powerpc-isa207-htm-vsx64l.xml
+expedite:r1,pc
+64:r0
+64:r1
+64:r2
+64:r3
+64:r4
+64:r5
+64:r6
+64:r7
+64:r8
+64:r9
+64:r10
+64:r11
+64:r12
+64:r13
+64:r14
+64:r15
+64:r16
+64:r17
+64:r18
+64:r19
+64:r20
+64:r21
+64:r22
+64:r23
+64:r24
+64:r25
+64:r26
+64:r27
+64:r28
+64:r29
+64:r30
+64:r31
+64:f0
+64:f1
+64:f2
+64:f3
+64:f4
+64:f5
+64:f6
+64:f7
+64:f8
+64:f9
+64:f10
+64:f11
+64:f12
+64:f13
+64:f14
+64:f15
+64:f16
+64:f17
+64:f18
+64:f19
+64:f20
+64:f21
+64:f22
+64:f23
+64:f24
+64:f25
+64:f26
+64:f27
+64:f28
+64:f29
+64:f30
+64:f31
+64:pc
+64:msr
+32:cr
+64:lr
+64:ctr
+32:xer
+64:fpscr
+64:orig_r3
+64:trap
+128:vr0
+128:vr1
+128:vr2
+128:vr3
+128:vr4
+128:vr5
+128:vr6
+128:vr7
+128:vr8
+128:vr9
+128:vr10
+128:vr11
+128:vr12
+128:vr13
+128:vr14
+128:vr15
+128:vr16
+128:vr17
+128:vr18
+128:vr19
+128:vr20
+128:vr21
+128:vr22
+128:vr23
+128:vr24
+128:vr25
+128:vr26
+128:vr27
+128:vr28
+128:vr29
+128:vr30
+128:vr31
+32:vscr
+32:vrsave
+64:vs0h
+64:vs1h
+64:vs2h
+64:vs3h
+64:vs4h
+64:vs5h
+64:vs6h
+64:vs7h
+64:vs8h
+64:vs9h
+64:vs10h
+64:vs11h
+64:vs12h
+64:vs13h
+64:vs14h
+64:vs15h
+64:vs16h
+64:vs17h
+64:vs18h
+64:vs19h
+64:vs20h
+64:vs21h
+64:vs22h
+64:vs23h
+64:vs24h
+64:vs25h
+64:vs26h
+64:vs27h
+64:vs28h
+64:vs29h
+64:vs30h
+64:vs31h
+64:ppr
+64:dscr
+64:tar
+64:tfhar
+64:texasr
+64:tfiar
+64:cr0
+64:cr1
+64:cr2
+64:cr3
+64:cr4
+64:cr5
+64:cr6
+64:cr7
+64:cr8
+64:cr9
+64:cr10
+64:cr11
+64:cr12
+64:cr13
+64:cr14
+64:cr15
+64:cr16
+64:cr17
+64:cr18
+64:cr19
+64:cr20
+64:cr21
+64:cr22
+64:cr23
+64:cr24
+64:cr25
+64:cr26
+64:cr27
+64:cr28
+64:cr29
+64:cr30
+64:cr31
+32:ccr
+32:cxer
+64:clr
+64:cctr
+64:cf0
+64:cf1
+64:cf2
+64:cf3
+64:cf4
+64:cf5
+64:cf6
+64:cf7
+64:cf8
+64:cf9
+64:cf10
+64:cf11
+64:cf12
+64:cf13
+64:cf14
+64:cf15
+64:cf16
+64:cf17
+64:cf18
+64:cf19
+64:cf20
+64:cf21
+64:cf22
+64:cf23
+64:cf24
+64:cf25
+64:cf26
+64:cf27
+64:cf28
+64:cf29
+64:cf30
+64:cf31
+64:cfpscr
+128:cvr0
+128:cvr1
+128:cvr2
+128:cvr3
+128:cvr4
+128:cvr5
+128:cvr6
+128:cvr7
+128:cvr8
+128:cvr9
+128:cvr10
+128:cvr11
+128:cvr12
+128:cvr13
+128:cvr14
+128:cvr15
+128:cvr16
+128:cvr17
+128:cvr18
+128:cvr19
+128:cvr20
+128:cvr21
+128:cvr22
+128:cvr23
+128:cvr24
+128:cvr25
+128:cvr26
+128:cvr27
+128:cvr28
+128:cvr29
+128:cvr30
+128:cvr31
+32:cvscr
+32:cvrsave
+64:cvs0h
+64:cvs1h
+64:cvs2h
+64:cvs3h
+64:cvs4h
+64:cvs5h
+64:cvs6h
+64:cvs7h
+64:cvs8h
+64:cvs9h
+64:cvs10h
+64:cvs11h
+64:cvs12h
+64:cvs13h
+64:cvs14h
+64:cvs15h
+64:cvs16h
+64:cvs17h
+64:cvs18h
+64:cvs19h
+64:cvs20h
+64:cvs21h
+64:cvs22h
+64:cvs23h
+64:cvs24h
+64:cvs25h
+64:cvs26h
+64:cvs27h
+64:cvs28h
+64:cvs29h
+64:cvs30h
+64:cvs31h
+64:cppr
+64:cdscr
+64:ctar
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index 134e9d0cbc..6687e20d2b 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -109,6 +109,11 @@
/* Holds the current set of options to be passed to the disassembler. */
static char *powerpc_disassembler_options;
+/* Determine if regnum is a Checkpointed POWER7 VSX register. */
+#define IS_CVSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cvsr0_regnum >= 0 \
+ && (regnum) >= (tdep)->ppc_cvsr0_regnum \
+ && (regnum) < (tdep)->ppc_cvsr0_regnum + ppc_num_vsrs)
+
/* The list of available "set powerpc ..." and "show powerpc ..."
commands. */
static struct cmd_list_element *setpowerpccmdlist = NULL;
@@ -2325,6 +2330,11 @@ rs6000_register_name (struct gdbarch *gdbarch, int regno)
&& regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs)
return "";
+ /* Hide the upper halves of the cvs0~cvs31 registers. */
+ if (PPC_CVS0H_REGNUM <= regno
+ && regno < PPC_CVS0H_REGNUM + ppc_num_gprs)
+ return "";
+
/* Check if the SPE pseudo registers are available. */
if (IS_SPE_PSEUDOREG (tdep, regno))
{
@@ -2379,6 +2389,23 @@ rs6000_register_name (struct gdbarch *gdbarch, int regno)
return efpr_regnames[regno - tdep->ppc_efpr0_regnum];
}
+ /* Check if this is a Checkpointed VSX pseudo-register. */
+ if (IS_CVSX_PSEUDOREG (tdep, regno))
+ {
+ static const char *const cvsx_regnames[] = {
+ "cvs0", "cvs1", "cvs2", "cvs3", "cvs4", "cvs5", "cvs6", "cvs7",
+ "cvs8", "cvs9", "cvs10", "cvs11", "cvs12", "cvs13", "cvs14",
+ "cvs15", "cvs16", "cvs17", "cvs18", "cvs19", "cvs20", "cvs21",
+ "cvs22", "cvs23", "cvs24", "cvs25", "cvs26", "cvs27", "cvs28",
+ "cvs29", "cvs30", "cvs31", "cvs32", "cvs33", "cvs34", "cvs35",
+ "cvs36", "cvs37", "cvs38", "cvs39", "cvs40", "cvs41", "cvs42",
+ "cvs43", "cvs44", "cvs45", "cvs46", "cvs47", "cvs48", "cvs49",
+ "cvs50", "cvs51", "cvs52", "cvs53", "cvs54", "cvs55", "cvs56",
+ "cvs57", "cvs58", "cvs59", "cvs60", "cvs61", "cvs62", "cvs63"
+ };
+ return cvsx_regnames[regno - tdep->ppc_cvsr0_regnum];
+ }
+
return tdesc_register_name (gdbarch, regno);
}
@@ -2394,7 +2421,8 @@ rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
|| IS_DFP_PSEUDOREG (tdep, regnum)
|| IS_VSX_PSEUDOREG (tdep, regnum)
- || IS_EFP_PSEUDOREG (tdep, regnum));
+ || IS_EFP_PSEUDOREG (tdep, regnum)
+ || IS_CVSX_PSEUDOREG (tdep, regnum));
/* These are the e500 pseudo-registers. */
if (IS_SPE_PSEUDOREG (tdep, regnum))
@@ -2402,7 +2430,8 @@ rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
else if (IS_DFP_PSEUDOREG (tdep, regnum))
/* PPC decimal128 pseudo-registers. */
return builtin_type (gdbarch)->builtin_declong;
- else if (IS_VSX_PSEUDOREG (tdep, regnum))
+ else if (IS_VSX_PSEUDOREG (tdep, regnum)
+ || IS_CVSX_PSEUDOREG (tdep, regnum))
/* POWER7 VSX pseudo-registers. */
return rs6000_builtin_type_vec128 (gdbarch);
else
@@ -2421,7 +2450,8 @@ rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
|| IS_DFP_PSEUDOREG (tdep, regnum)
|| IS_VSX_PSEUDOREG (tdep, regnum)
- || IS_EFP_PSEUDOREG (tdep, regnum));
+ || IS_EFP_PSEUDOREG (tdep, regnum)
+ || IS_CVSX_PSEUDOREG (tdep, regnum));
/* builtin_declong doesn't have TYPE_CODE_FLT, so it won't be
detected as a float register by default_register_reggroup_p. */
@@ -2689,6 +2719,42 @@ vsx_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache,
return status;
}
+/* Read method for checkpointed POWER7 VSX pseudo-registers. */
+static enum register_status
+cvsx_pseudo_register_read (struct gdbarch *gdbarch,
+ readable_regcache *regcache,
+ int reg_nr, gdb_byte *buffer)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ int reg_index = reg_nr - tdep->ppc_cvsr0_regnum;
+ enum register_status status;
+
+ /* Read the portion that overlaps the VMX registers. */
+ if (reg_index > 31)
+ status = regcache->raw_read (PPC_CVR0_REGNUM + reg_index - 32,
+ buffer);
+ else
+ /* Read the portion that overlaps the FPR registers. */
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+ {
+ status = regcache->raw_read (PPC_CF0_REGNUM + reg_index,
+ buffer);
+ if (status == REG_VALID)
+ status = regcache->raw_read (PPC_CVS0H_REGNUM + reg_index,
+ buffer + 8);
+ }
+ else
+ {
+ status = regcache->raw_read (PPC_CF0_REGNUM + reg_index,
+ buffer + 8);
+ if (status == REG_VALID)
+ status = regcache->raw_read (PPC_CVS0H_REGNUM + reg_index,
+ buffer);
+ }
+
+ return status;
+}
+
/* Write method for POWER7 VSX pseudo-registers. */
static void
vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
@@ -2719,6 +2785,32 @@ vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
}
}
+/* Write method for checkpointed VSX pseudo-registers. */
+static void
+cvsx_pseudo_register_write (struct gdbarch *gdbarch,
+ struct regcache *regcache,
+ int reg_nr, const gdb_byte *buffer)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ int reg_index = reg_nr - tdep->ppc_cvsr0_regnum;
+
+ /* Write the portion that overlaps the CVMX registers. */
+ if (reg_index > 31)
+ regcache->raw_write (PPC_CVR0_REGNUM + reg_index - 32, buffer);
+ else
+ /* Write the portion that overlaps the CFPR registers. */
+ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+ {
+ regcache->raw_write (PPC_CF0_REGNUM + reg_index, buffer);
+ regcache->raw_write (PPC_CVS0H_REGNUM + reg_index, buffer + 8);
+ }
+ else
+ {
+ regcache->raw_write (PPC_CF0_REGNUM + reg_index, buffer + 8);
+ regcache->raw_write (PPC_CVS0H_REGNUM + reg_index, buffer);
+ }
+}
+
/* Read method for POWER7 Extended FP pseudo-registers. */
static enum register_status
efpr_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache,
@@ -2766,6 +2858,8 @@ rs6000_pseudo_register_read (struct gdbarch *gdbarch,
return vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
return efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
+ else if (IS_CVSX_PSEUDOREG (tdep, reg_nr))
+ return cvsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
else
internal_error (__FILE__, __LINE__,
_("rs6000_pseudo_register_read: "
@@ -2791,6 +2885,8 @@ rs6000_pseudo_register_write (struct gdbarch *gdbarch,
vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
+ else if (IS_CVSX_PSEUDOREG (tdep, reg_nr))
+ cvsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
else
internal_error (__FILE__, __LINE__,
_("rs6000_pseudo_register_write: "
@@ -2815,17 +2911,34 @@ rs6000_ax_pseudo_register_collect (struct gdbarch *gdbarch,
ax_reg_mask (ax, tdep->ppc_fp0_regnum + 2 * reg_index);
ax_reg_mask (ax, tdep->ppc_fp0_regnum + 2 * reg_index + 1);
}
- else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
+ else if (IS_VSX_PSEUDOREG (tdep, reg_nr)
+ || IS_CVSX_PSEUDOREG (tdep, reg_nr))
{
- int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
+ int reg_index, vr0, fp0, vsr0_upper;
+
+ if (IS_VSX_PSEUDOREG (tdep, reg_nr))
+ {
+ reg_index = reg_nr - tdep->ppc_vsr0_regnum;
+ vr0 = tdep->ppc_vr0_regnum;
+ fp0 = tdep->ppc_fp0_regnum;
+ vsr0_upper = tdep->ppc_vsr0_upper_regnum;
+ }
+ else
+ {
+ reg_index = reg_nr - tdep->ppc_cvsr0_regnum;
+ vr0 = PPC_CVR0_REGNUM;
+ fp0 = PPC_CF0_REGNUM;
+ vsr0_upper = PPC_CVS0H_REGNUM;
+ }
+
if (reg_index > 31)
{
- ax_reg_mask (ax, tdep->ppc_vr0_regnum + reg_index - 32);
+ ax_reg_mask (ax, vr0 + reg_index - 32);
}
else
{
- ax_reg_mask (ax, tdep->ppc_fp0_regnum + reg_index);
- ax_reg_mask (ax, tdep->ppc_vsr0_upper_regnum + reg_index);
+ ax_reg_mask (ax, fp0 + reg_index);
+ ax_reg_mask (ax, vsr0_upper + reg_index);
}
}
else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
@@ -5841,7 +5954,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
enum powerpc_elf_abi elf_abi = POWERPC_ELF_AUTO;
int have_fpu = 0, have_spe = 0, have_mq = 0, have_altivec = 0;
int have_dfp = 0, have_vsx = 0, have_ppr = 0, have_dscr = 0;
- int have_tar = 0;
+ int have_tar = 0, have_htm = 0;
int tdesc_wordsize = -1;
const struct target_desc *tdesc = info.target_desc;
struct tdesc_arch_data *tdesc_data = NULL;
@@ -6181,6 +6294,97 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
}
else
have_tar = 0;
+
+ /* Hardware Transactional Memory Registers. */
+ feature = tdesc_find_feature (tdesc,
+ "org.gnu.gdb.power.htm");
+ if (feature != NULL)
+ {
+
+ /* Make sure that all the checkpointed registers we are
+ about to validate have already been seen in their normal
+ non-checkpointed form. We expect a 64-bit checkpointed
+ FPSCR, which implies have_dfp, which implies
+ have_fpu. */
+
+ if (!(have_dfp && have_altivec && have_vsx &&
+ have_ppr && have_dscr && have_tar))
+ {
+ tdesc_data_cleanup (tdesc_data);
+ return NULL;
+ }
+
+ static const char *const tm_spr_regs[] = {
+ "tfhar", "texasr", "tfiar"
+ };
+
+ static const char *const cgprs[] = {
+ "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
+ "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15",
+ "cr16", "cr17", "cr18", "cr19", "cr20", "cr21", "cr22", "cr23",
+ "cr24", "cr25", "cr26", "cr27", "cr28", "cr29", "cr30", "cr31",
+ "ccr", "cxer", "clr", "cctr"
+ };
+
+ static const char *const cfprs[] = {
+ "cf0", "cf1", "cf2", "cf3", "cf4", "cf5", "cf6", "cf7",
+ "cf8", "cf9", "cf10", "cf11", "cf12", "cf13", "cf14", "cf15",
+ "cf16", "cf17", "cf18", "cf19", "cf20", "cf21", "cf22", "cf23",
+ "cf24", "cf25", "cf26", "cf27", "cf28", "cf29", "cf30", "cf31"
+ };
+ static const char *const cvmx[] = {
+ "cvr0", "cvr1", "cvr2", "cvr3", "cvr4", "cvr5", "cvr6", "cvr7",
+ "cvr8", "cvr9", "cvr10", "cvr11", "cvr12", "cvr13", "cvr14", "cvr15",
+ "cvr16", "cvr17", "cvr18", "cvr19", "cvr20", "cvr21", "cvr22", "cvr23",
+ "cvr24", "cvr25", "cvr26", "cvr27", "cvr28", "cvr29", "cvr30", "cvr31"
+ };
+ static const char *const cvsx[] = {
+ "cvs0h", "cvs1h", "cvs2h", "cvs3h", "cvs4h", "cvs5h",
+ "cvs6h", "cvs7h", "cvs8h", "cvs9h", "cvs10h", "cvs11h",
+ "cvs12h", "cvs13h", "cvs14h", "cvs15h", "cvs16h", "cvs17h",
+ "cvs18h", "cvs19h", "cvs20h", "cvs21h", "cvs22h", "cvs23h",
+ "cvs24h", "cvs25h", "cvs26h", "cvs27h", "cvs28h", "cvs29h",
+ "cvs30h", "cvs31h"
+ };
+
+ valid_p = 1;
+ for (i = 0; i < ARRAY_SIZE (tm_spr_regs); i++)
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ PPC_TFHAR_REGNUM + i,
+ tm_spr_regs[i]);
+ for (i = 0; i < ARRAY_SIZE (cgprs); i++)
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ PPC_CR0_REGNUM + i, cgprs[i]);
+ for (i = 0; i < ARRAY_SIZE (cfprs); i++)
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ PPC_CF0_REGNUM + i, cfprs[i]);
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ PPC_CFPSCR_REGNUM, "cfpscr");
+ for (i = 0; i < ARRAY_SIZE (cvmx); i++)
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ PPC_CVR0_REGNUM + i, cvmx[i]);
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ PPC_CVSCR_REGNUM, "cvscr");
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ PPC_CVRSAVE_REGNUM, "cvrsave");
+ for (i = 0; i < ARRAY_SIZE (cvsx); i++)
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ PPC_CVS0H_REGNUM + i, cvsx[i]);
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ PPC_CPPR_REGNUM, "cppr");
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ PPC_CDSCR_REGNUM, "cdscr");
+ valid_p &= tdesc_numbered_register (feature, tdesc_data,
+ PPC_CTAR_REGNUM, "ctar");
+ if (!valid_p)
+ {
+ tdesc_data_cleanup (tdesc_data);
+ return NULL;
+ }
+ have_htm = 1;
+ }
+ else
+ have_htm = 0;
}
/* If we have a 64-bit binary on a 32-bit target, complain. Also
@@ -6378,6 +6582,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
tdep->ppc_ppr_regnum = have_ppr ? PPC_PPR_REGNUM : -1;
tdep->ppc_dscr_regnum = have_dscr ? PPC_DSCR_REGNUM : -1;
tdep->ppc_tar_regnum = have_tar ? PPC_TAR_REGNUM : -1;
+ tdep->have_htm = have_htm;
set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
@@ -6420,8 +6625,14 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
if (have_dfp)
num_pseudoregs += 16;
if (have_vsx)
- /* Include both VSX and Extended FP registers. */
- num_pseudoregs += 96;
+ {
+ /* Include both VSX and Extended FP registers */
+ num_pseudoregs += 96;
+
+ /* Includes CVSX. */
+ if (have_htm)
+ num_pseudoregs += 64;
+ }
set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs);
@@ -6539,6 +6750,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
tdep->ppc_dl0_regnum = -1;
tdep->ppc_vsr0_regnum = -1;
tdep->ppc_efpr0_regnum = -1;
+ tdep->ppc_cvsr0_regnum = -1;
cur_reg = gdbarch_num_regs (gdbarch);
@@ -6558,6 +6770,11 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cur_reg += 64;
tdep->ppc_efpr0_regnum = cur_reg;
cur_reg += 32;
+ if (have_htm)
+ {
+ tdep->ppc_cvsr0_regnum = cur_reg;
+ cur_reg += ppc_num_vsrs;
+ }
}
gdb_assert (gdbarch_num_regs (gdbarch)
--
2.13.6
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 13/17] [PowerPC] Add support for HTM registers
2018-07-13 13:53 ` [PATCH 13/17] [PowerPC] Add support for HTM registers Pedro Franco de Carvalho
@ 2018-07-13 16:24 ` Ulrich Weigand
2018-07-13 18:16 ` Pedro Franco de Carvalho
0 siblings, 1 reply; 38+ messages in thread
From: Ulrich Weigand @ 2018-07-13 16:24 UTC (permalink / raw)
To: Pedro Franco de Carvalho; +Cc: gdb-patches, edjunior
Pedro Franco de Carvalho wrote:
> The set of checkpointed general-purpose registers is returned by the
> linux kernel in the same format as the regular general-purpose
> registers, defined in struct pt_regs. However, the architecture
> specifies that only some of the registers present in pt_regs are
> checkpointed (GPRs 0-31, CR, XER, LR and CTR). The kernel fills the
> slots for other registers with other info (e.g., nip is filled with
> the contents of TFHAR). GDB doesn't handle these other registers. This
> means that core files generated by GDB will show values of zero for
> these registers, while core files generated by the kernel will have
> other values. Core files generated by the kernel have a note section
> for checkpointed GPRs with the same size for both 32-bit and 64-bit
> threads, and the values for the registers of a 32-bit thread are
> squeezed in the first half, with no useful data in the second
> half. GDB generates a smaller note section for 32-bit threads, but can
> read both sizes.
Well, this is weird. Either the kernel should be fixed to use the
smaller size as well, or else GDB should also generate the large
section (and zero out the second half).
> Access to the checkpointed CR (condition register) can be
> confusing. The architecture only specifies that CR fields 1 to 7 (the
> 24 least significant bits) are checkpointed, but the kernel provides
> all 8 fields (32 bits). The value of field 0 is not masked by ptrace,
> so it will sometimes show the result of some kernel operation,
> probably treclaim., which sets this field.
Huh. We shold report this to the kernel people.
> The checkpointed registers are marked not to be saved and
> restored. Inferior function calls during an active transaction don't
> work well, and it's unclear what should be done in this case. TEXASR
> and TFIAR can be altered asynchronously, during transaction failure
> recording, so they are also not saved and restored. For consistency
> neither is TFHAR.
>
> Record and replay also doesn't work well when transactions are
> involved. This patch doesn't address this, so the values of the HTM
> SPRs will sometimes be innacurate when the record/relay target is
> enabled. For instance, executing a "tbegin." alters TFHAR and TEXASR,
> but these changes are not currently recorded.
>
> Because the checkpointed registers are only available when a
> transaction is active (or suspended), ptrace can return ENODATA when
> gdb tries to read these registers and the inferior is not in a
> transactional state. The registers are set to the unavailable state
> when this happens. When gbd tries to write to one of these registers,
> and it is unavailable, an error is raised. When gdb tries to store to
> all registers in one go (when store_registers called with -1), the
> state of these registers is checked. If they are all unavailable, no
> write is attempted, so that writes to all the other registers are
> unaffected. If all are available, the write is attempted. Otherwise an
> internal_error is raised.
This all makes sense to me.
> Like for the previous patches, configure.srv is updated here to avoid
> breaking the build at this patch.
Same comment as before :-)
> + tdep->wordsize == 4? PPC32_LINUX_SIZEOF_CGPRREGSET
> + : PPC64_LINUX_SIZEOF_CGPRREGSET,
Use parentheses for formatting.
> +/* Get the checkpointed GPR regset that matches the target wordsize
> + and byteorder of GDBARCH. The collect function of the returned
> + regset will clear the buffer passed to it before collecting the
> + registers to 0 if CLEAR_ON_COLLECT is true and the collect function
> + is called with regno == -1 (collect all regs in the regset). This
> + is useful for generating core files without garbage in the register
> + slots that are not seen by gdb. When collecting for storing the
> + registers in the inferior, these slots should not be cleared. */
I'm not sure I like this approach. The problem is only about
generating core files, right? Why don't we instead simply
change linux-tdep.c:linux_collect_regset_section_cb from
buf = (char *) xmalloc (size);
regset->collect_regset (regset, data->regcache, -1, buf, size);
to use xcalloc instead? This seems prudent anyway. (The same applies
to the similar code in fbsd-tdep.c.)
Then we can probably even get rid of ppc_linux_collect_vrregset as well.
> return vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
> else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
> return efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
> + else if (IS_CVSX_PSEUDOREG (tdep, reg_nr))
> + return cvsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
Hmm. The DFP and EFP pseudo registers are simply GDB views onto the
normal FP / VR register set. For completeness, shouldn't we also offer
similar views onto the checkpointed register set?
> + if (IS_VSX_PSEUDOREG (tdep, reg_nr))
> + {
> + reg_index = reg_nr - tdep->ppc_vsr0_regnum;
> + vr0 = tdep->ppc_vr0_regnum;
> + fp0 = tdep->ppc_fp0_regnum;
> + vsr0_upper = tdep->ppc_vsr0_upper_regnum;
> + }
> + else
> + {
> + reg_index = reg_nr - tdep->ppc_cvsr0_regnum;
> + vr0 = PPC_CVR0_REGNUM;
> + fp0 = PPC_CF0_REGNUM;
> + vsr0_upper = PPC_CVS0H_REGNUM;
> + }
It looks a bit odd that we need to use variable numbers for
the vr0 / fp0 / vsr0 registers, but can hard-code the numbers
for the checkpointed register set. Why is this the case?
Bye,
Ulrich
--
Dr. Ulrich Weigand
GNU/Linux compilers and toolchain
Ulrich.Weigand@de.ibm.com
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 13/17] [PowerPC] Add support for HTM registers
2018-07-13 16:24 ` Ulrich Weigand
@ 2018-07-13 18:16 ` Pedro Franco de Carvalho
0 siblings, 0 replies; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 18:16 UTC (permalink / raw)
To: Ulrich Weigand; +Cc: gdb-patches, edjunior
Ulrich Weigand <uweigand@de.ibm.com> writes:
> Pedro Franco de Carvalho wrote:
> Well, this is weird. Either the kernel should be fixed to use the
> smaller size as well, or else GDB should also generate the large
> section (and zero out the second half).
OK.
One more thing about the checkpointed registers: Linux doesn't currently
support AMR, but it is specified by the architecture to be checkpointed
as well. If it is added in the future, its checkpointed version will
either need to be a separate tdesc feature or rs6000_gdbarch_init will
have to accept a org.gnu.gdb.power.htm feature with and without it.
The tdep object might also need a separate field, since it won't be
possible to rely on tdep->have_htm to know if a checkpointed amr is
available in the gdbarch. This is different from the approach I took for
the incomplete pmu registers, where I enumerated all the ones that are
there in the tdep object. Doing this for all the htm registers would add
a lot more fields.
> I'm not sure I like this approach. The problem is only about
> generating core files, right? Why don't we instead simply
> change linux-tdep.c:linux_collect_regset_section_cb from
>
> buf = (char *) xmalloc (size);
> regset->collect_regset (regset, data->regcache, -1, buf, size);
>
> to use xcalloc instead? This seems prudent anyway. (The same applies
> to the similar code in fbsd-tdep.c.)
>
> Then we can probably even get rid of ppc_linux_collect_vrregset as well.
Yes, this seems like a much simpler approach.
> Hmm. The DFP and EFP pseudo registers are simply GDB views onto the
> normal FP / VR register set. For completeness, shouldn't we also offer
> similar views onto the checkpointed register set?
OK. I had removed them thinking they weren't going to be used a lot, but
I'll put them back in for completeness.
> It looks a bit odd that we need to use variable numbers for
> the vr0 / fp0 / vsr0 registers, but can hard-code the numbers
> for the checkpointed register set. Why is this the case?
There isn't a good reason, I probably just didn't change the way it was
done for the regular registers. I will change them to use the hard-coded
numbers for consistency (there is no tdep field for cvsr0_upper, cfp0
and cvr0).
Thank you for the reviews!
--
Pedro Franco de Carvalho
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 07/17] [PowerPC] Add gdbserver support for PPR and DSCR
2018-07-13 13:53 [PATCH 00/17] GDB support for more powerpc registers on linux Pedro Franco de Carvalho
` (10 preceding siblings ...)
2018-07-13 13:53 ` [PATCH 13/17] [PowerPC] Add support for HTM registers Pedro Franco de Carvalho
@ 2018-07-13 13:53 ` Pedro Franco de Carvalho
2018-07-13 15:26 ` Ulrich Weigand
2018-07-13 13:53 ` [PATCH 14/17] [PowerPC] Add gdbserver support for HTM registers Pedro Franco de Carvalho
` (4 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 13:53 UTC (permalink / raw)
To: gdb-patches; +Cc: uweigand, edjunior
From: Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
This patch extends support for the Program Priority Register and the
Data Stream Control Register to the powerpc linux gdbserver stub.
gdb/gdbserver/ChangeLog:
YYYY-MM-DD Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* linux-ppc-tdesc-init.h (enum ppc_linux_tdesc)
<PPC_TDESC_ISA205_PPR_DSCR_VSX>: New enum value.
(init_registers_powerpc_isa205_ppr_dscr_vsx32l)
(init_registers_powerpc_isa205_ppr_dscr_vsx64l): Declare.
* linux-ppc-low.c: Include "elf/common.h" and <sys/uio.h>.
(ppc_hwcap2): New global.
(ppc_check_regset, ppc_fill_pprregset, ppc_store_pprregset)
(ppc_fill_dscrregset, ppc_store_dscrregset): New functions.
(ppc_regsets): Add entries for the DSCR and PPR regsets.
(ppc_arch_setup): Get AT_HWCAP2. Set ppr_dscr in features struct
when needed. Set sizes for the the DSCR and PPR regsets.
(ppc_get_ipa_tdesc_idx): Return PPC_TDESC_ISA205_PPR_DSCR_VSX.
(initialize_low_arch): Call
init_registers_powerpc_isa205_ppr_dscr_vsx32l and
init_registers_powerpc_isa205_ppr_dscr_vsx64l.
* linux-ppc-ipa.c (get_ipa_tdesc): Handle
PPC_TDESC_ISA205_PPR_DSCR_VSX.
(initialize_low_tracepoint): Call
init_registers_powerpc_isa205_ppr_dscr_vsx32l and
init_registers_powerpc_isa205_ppr_dscr_vsx64l.
---
gdb/gdbserver/linux-ppc-ipa.c | 6 +++
gdb/gdbserver/linux-ppc-low.c | 81 ++++++++++++++++++++++++++++++++++++
gdb/gdbserver/linux-ppc-tdesc-init.h | 7 ++++
3 files changed, 94 insertions(+)
diff --git a/gdb/gdbserver/linux-ppc-ipa.c b/gdb/gdbserver/linux-ppc-ipa.c
index f6861f0d98..c8b4c3b2da 100644
--- a/gdb/gdbserver/linux-ppc-ipa.c
+++ b/gdb/gdbserver/linux-ppc-ipa.c
@@ -191,6 +191,8 @@ get_ipa_tdesc (int idx)
return tdesc_powerpc_isa205_altivec64l;
case PPC_TDESC_ISA205_VSX:
return tdesc_powerpc_isa205_vsx64l;
+ case PPC_TDESC_ISA205_PPR_DSCR_VSX:
+ return tdesc_powerpc_isa205_ppr_dscr_vsx64l;
#else
case PPC_TDESC_BASE:
return tdesc_powerpc_32l;
@@ -206,6 +208,8 @@ get_ipa_tdesc (int idx)
return tdesc_powerpc_isa205_altivec32l;
case PPC_TDESC_ISA205_VSX:
return tdesc_powerpc_isa205_vsx32l;
+ case PPC_TDESC_ISA205_PPR_DSCR_VSX:
+ return tdesc_powerpc_isa205_ppr_dscr_vsx32l;
case PPC_TDESC_E500:
return tdesc_powerpc_e500l;
#endif
@@ -234,6 +238,7 @@ initialize_low_tracepoint (void)
init_registers_powerpc_isa205_64l ();
init_registers_powerpc_isa205_altivec64l ();
init_registers_powerpc_isa205_vsx64l ();
+ init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
#else
init_registers_powerpc_32l ();
init_registers_powerpc_altivec32l ();
@@ -242,6 +247,7 @@ initialize_low_tracepoint (void)
init_registers_powerpc_isa205_32l ();
init_registers_powerpc_isa205_altivec32l ();
init_registers_powerpc_isa205_vsx32l ();
+ init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
init_registers_powerpc_e500l ();
#endif
}
diff --git a/gdb/gdbserver/linux-ppc-low.c b/gdb/gdbserver/linux-ppc-low.c
index 47428c1529..502ce674fc 100644
--- a/gdb/gdbserver/linux-ppc-low.c
+++ b/gdb/gdbserver/linux-ppc-low.c
@@ -20,6 +20,8 @@
#include "server.h"
#include "linux-low.h"
+#include "elf/common.h"
+#include <sys/uio.h>
#include <elf.h>
#include <asm/ptrace.h>
@@ -42,6 +44,7 @@
#define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
static unsigned long ppc_hwcap;
+static unsigned long ppc_hwcap2;
#define ppc_num_regs 73
@@ -117,6 +120,21 @@ static int ppc_regmap_e500[] =
#endif
static int
+ppc_check_regset (int tid, int regset_id, int regsetsize)
+{
+ void *buf = alloca (regsetsize);
+ struct iovec iov;
+
+ iov.iov_base = buf;
+ iov.iov_len = regsetsize;
+
+ if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0
+ || errno == ENODATA)
+ return 1;
+ return 0;
+}
+
+static int
ppc_cannot_store_register (int regno)
{
const struct target_desc *tdesc = current_process ()->tdesc;
@@ -460,6 +478,38 @@ static void ppc_fill_gregset (struct regcache *regcache, void *buf)
}
static void
+ppc_fill_pprregset (struct regcache *regcache, void *buf)
+{
+ char *ppr = (char *) buf;
+
+ collect_register_by_name (regcache, "ppr", ppr);
+}
+
+static void
+ppc_store_pprregset (struct regcache *regcache, const void *buf)
+{
+ const char *ppr = (const char *) buf;
+
+ supply_register_by_name (regcache, "ppr", ppr);
+}
+
+static void
+ppc_fill_dscrregset (struct regcache *regcache, void *buf)
+{
+ char *dscr = (char *) buf;
+
+ collect_register_by_name (regcache, "dscr", dscr);
+}
+
+static void
+ppc_store_dscrregset (struct regcache *regcache, const void *buf)
+{
+ const char *dscr = (const char *) buf;
+
+ supply_register_by_name (regcache, "dscr", dscr);
+}
+
+static void
ppc_fill_vsxregset (struct regcache *regcache, void *buf)
{
int i, base;
@@ -572,6 +622,10 @@ static struct regset_info ppc_regsets[] = {
fetch them every time, but still fall back to PTRACE_PEEKUSER for the
general registers. Some kernels support these, but not the newer
PPC_PTRACE_GETREGS. */
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS,
+ ppc_fill_pprregset, ppc_store_pprregset },
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_DSCR, 0, EXTENDED_REGS,
+ ppc_fill_dscrregset, ppc_store_dscrregset },
{ PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, 0, EXTENDED_REGS,
ppc_fill_vsxregset, ppc_store_vsxregset },
{ PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, 0, EXTENDED_REGS,
@@ -629,6 +683,7 @@ ppc_arch_setup (void)
/* The value of current_process ()->tdesc needs to be set for this
call. */
ppc_get_auxv (AT_HWCAP, &ppc_hwcap);
+ ppc_get_auxv (AT_HWCAP2, &ppc_hwcap2);
features.isa205 = ppc_linux_has_isa205 (ppc_hwcap);
@@ -638,6 +693,11 @@ ppc_arch_setup (void)
if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
features.altivec = true;
+ if ((ppc_hwcap2 & PPC_FEATURE2_DSCR)
+ && ppc_check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET)
+ && ppc_check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET))
+ features.ppr_dscr = true;
+
if (ppc_hwcap & PPC_FEATURE_CELL)
features.cell = true;
@@ -682,6 +742,21 @@ ppc_arch_setup (void)
else
regset->size = 0;
break;
+ case PTRACE_GETREGSET:
+ switch (regset->nt_type)
+ {
+ case NT_PPC_PPR:
+ regset->size = (features.ppr_dscr ?
+ PPC_LINUX_SIZEOF_PPRREGSET : 0);
+ break;
+ case NT_PPC_DSCR:
+ regset->size = (features.ppr_dscr ?
+ PPC_LINUX_SIZEOF_DSCRREGSET : 0);
+ break;
+ default:
+ break;
+ }
+ break;
default:
break;
}
@@ -3057,6 +3132,8 @@ ppc_get_ipa_tdesc_idx (void)
return PPC_TDESC_ISA205_ALTIVEC;
if (tdesc == tdesc_powerpc_isa205_vsx64l)
return PPC_TDESC_ISA205_VSX;
+ if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx64l)
+ return PPC_TDESC_ISA205_PPR_DSCR_VSX;
#endif
if (tdesc == tdesc_powerpc_32l)
@@ -3073,6 +3150,8 @@ ppc_get_ipa_tdesc_idx (void)
return PPC_TDESC_ISA205_ALTIVEC;
if (tdesc == tdesc_powerpc_isa205_vsx32l)
return PPC_TDESC_ISA205_VSX;
+ if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx32l)
+ return PPC_TDESC_ISA205_PPR_DSCR_VSX;
if (tdesc == tdesc_powerpc_e500l)
return PPC_TDESC_E500;
@@ -3131,6 +3210,7 @@ initialize_low_arch (void)
init_registers_powerpc_isa205_32l ();
init_registers_powerpc_isa205_altivec32l ();
init_registers_powerpc_isa205_vsx32l ();
+ init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
init_registers_powerpc_e500l ();
#if __powerpc64__
init_registers_powerpc_64l ();
@@ -3140,6 +3220,7 @@ initialize_low_arch (void)
init_registers_powerpc_isa205_64l ();
init_registers_powerpc_isa205_altivec64l ();
init_registers_powerpc_isa205_vsx64l ();
+ init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
#endif
initialize_regsets_info (&ppc_regsets_info);
diff --git a/gdb/gdbserver/linux-ppc-tdesc-init.h b/gdb/gdbserver/linux-ppc-tdesc-init.h
index 422e7bd9c4..c5c10c0670 100644
--- a/gdb/gdbserver/linux-ppc-tdesc-init.h
+++ b/gdb/gdbserver/linux-ppc-tdesc-init.h
@@ -29,6 +29,7 @@ enum ppc_linux_tdesc {
PPC_TDESC_ISA205,
PPC_TDESC_ISA205_ALTIVEC,
PPC_TDESC_ISA205_VSX,
+ PPC_TDESC_ISA205_PPR_DSCR_VSX,
PPC_TDESC_E500,
};
@@ -55,6 +56,9 @@ void init_registers_powerpc_isa205_altivec32l (void);
/* Defined in auto-generated file powerpc-isa205-vsx32l.c. */
void init_registers_powerpc_isa205_vsx32l (void);
+/* Defined in auto-generated file powerpc-isa205-ppr-dscr-vsx32l.c. */
+void init_registers_powerpc_isa205_ppr_dscr_vsx32l (void);
+
/* Defined in auto-generated file powerpc-e500l.c. */
void init_registers_powerpc_e500l (void);
@@ -83,4 +87,7 @@ void init_registers_powerpc_isa205_altivec64l (void);
/* Defined in auto-generated file powerpc-isa205-vsx64l.c. */
void init_registers_powerpc_isa205_vsx64l (void);
+/* Defined in auto-generated file powerpc-isa205-ppr-dscr-vsx64l.c. */
+void init_registers_powerpc_isa205_ppr_dscr_vsx64l (void);
+
#endif
--
2.13.6
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 07/17] [PowerPC] Add gdbserver support for PPR and DSCR
2018-07-13 13:53 ` [PATCH 07/17] [PowerPC] Add gdbserver support for PPR and DSCR Pedro Franco de Carvalho
@ 2018-07-13 15:26 ` Ulrich Weigand
0 siblings, 0 replies; 38+ messages in thread
From: Ulrich Weigand @ 2018-07-13 15:26 UTC (permalink / raw)
To: Pedro Franco de Carvalho; +Cc: gdb-patches, edjunior
Pedro Franco de Carvalho wrote:
> gdb/gdbserver/ChangeLog:
> YYYY-MM-DD Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
> Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
>
> * linux-ppc-tdesc-init.h (enum ppc_linux_tdesc)
> <PPC_TDESC_ISA205_PPR_DSCR_VSX>: New enum value.
> (init_registers_powerpc_isa205_ppr_dscr_vsx32l)
> (init_registers_powerpc_isa205_ppr_dscr_vsx64l): Declare.
> * linux-ppc-low.c: Include "elf/common.h" and <sys/uio.h>.
> (ppc_hwcap2): New global.
> (ppc_check_regset, ppc_fill_pprregset, ppc_store_pprregset)
> (ppc_fill_dscrregset, ppc_store_dscrregset): New functions.
> (ppc_regsets): Add entries for the DSCR and PPR regsets.
> (ppc_arch_setup): Get AT_HWCAP2. Set ppr_dscr in features struct
> when needed. Set sizes for the the DSCR and PPR regsets.
> (ppc_get_ipa_tdesc_idx): Return PPC_TDESC_ISA205_PPR_DSCR_VSX.
> (initialize_low_arch): Call
> init_registers_powerpc_isa205_ppr_dscr_vsx32l and
> init_registers_powerpc_isa205_ppr_dscr_vsx64l.
> * linux-ppc-ipa.c (get_ipa_tdesc): Handle
> PPC_TDESC_ISA205_PPR_DSCR_VSX.
> (initialize_low_tracepoint): Call
> init_registers_powerpc_isa205_ppr_dscr_vsx32l and
> init_registers_powerpc_isa205_ppr_dscr_vsx64l.
This is OK.
Thanks,
Ulrich
--
Dr. Ulrich Weigand
GNU/Linux compilers and toolchain
Ulrich.Weigand@de.ibm.com
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 14/17] [PowerPC] Add gdbserver support for HTM registers
2018-07-13 13:53 [PATCH 00/17] GDB support for more powerpc registers on linux Pedro Franco de Carvalho
` (11 preceding siblings ...)
2018-07-13 13:53 ` [PATCH 07/17] [PowerPC] Add gdbserver support for PPR and DSCR Pedro Franco de Carvalho
@ 2018-07-13 13:53 ` Pedro Franco de Carvalho
2018-07-13 16:26 ` Ulrich Weigand
2018-07-13 13:53 ` [PATCH 06/17] [PowerPC] Add record/replay support for PPR and DSCR Pedro Franco de Carvalho
` (3 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 13:53 UTC (permalink / raw)
To: gdb-patches; +Cc: uweigand, edjunior
This patch extends suport for the HTM registers to the powerpc linux
gdbserver stub.
The "fill" functions for checkpointed register sets are not
implemented, because ptrace can return ENODATA for these regsets
whenever the inferior is not in a transaction.
Since gdbserver writes all registers in one go before resuming the
inferior, this error would not be detected at the time the user tries
to write to one of the registers on the client side, and gdbserver
would print out warnings every time it resumes the inferior when it is
not in a transaction, so there is currently no straightforward way to
handle this case. This means the checkpointed registers in the
client-side regcache can become dirty when the user tries to write to
them, until the inferior is resumed and stopped again.
Another limitation for the checkpointed registers is that traceframes
don't record if registers are available or not, so if these registers
are collected when a tracepoint is hit and the inferior is not in a
transaction, the user will see zero values for all of them, instead of
the usual <unavailable>.
gdb/gdbserver/ChangeLog:
2018-07-05 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* linux-ppc-tdesc-init.h (enum ppc_linux_tdesc)
<PPC_TDESC_ISA207_HTM_VSX>: New enum value.
(init_registers_powerpc_isa207_htm_vsx32l)
(init_registers_powerpc_isa207_htm_vsx64l): Declare.
* linux-ppc-low.c (ppc_fill_tm_sprregset, ppc_store_tm_sprregset)
(ppc_store_tm_cgprregset, ppc_store_tm_cfprregset)
(ppc_store_tm_cvrregset, ppc_store_tm_cvsxregset)
(ppc_store_tm_cpprregset, ppc_store_tm_cdscrregset)
(ppc_store_tm_ctarregset): New functions.
(ppc_regsets): Add entries for HTM regsets.
(ppc_arch_setup): Set htm in features struct when needed. Set
sizes for the HTM regsets.
(ppc_get_ipa_tdesc_idx): Return PPC_TDESC_ISA207_HTM_VSX.
(initialize_low_arch): Call
init_registers_powerpc_isa207_htm_vsx32l and
init_registers_powerpc_isa207_htm_vsx64l.
* linux-ppc-ipa.c (get_ipa_tdesc): Handle
PPC_TDESC_ISA207_HTM_VSX.
(initialize_low_tracepoint): Call
init_registers_powerpc_isa207_htm_vsx32l and
init_registers_powerpc_isa207_htm_vsx64l.
---
gdb/gdbserver/linux-ppc-ipa.c | 6 ++
gdb/gdbserver/linux-ppc-low.c | 187 ++++++++++++++++++++++++++++++++++-
gdb/gdbserver/linux-ppc-tdesc-init.h | 7 ++
3 files changed, 199 insertions(+), 1 deletion(-)
diff --git a/gdb/gdbserver/linux-ppc-ipa.c b/gdb/gdbserver/linux-ppc-ipa.c
index b543dceba5..348d455193 100644
--- a/gdb/gdbserver/linux-ppc-ipa.c
+++ b/gdb/gdbserver/linux-ppc-ipa.c
@@ -195,6 +195,8 @@ get_ipa_tdesc (int idx)
return tdesc_powerpc_isa205_ppr_dscr_vsx64l;
case PPC_TDESC_ISA207_VSX:
return tdesc_powerpc_isa207_vsx64l;
+ case PPC_TDESC_ISA207_HTM_VSX:
+ return tdesc_powerpc_isa207_htm_vsx64l;
#else
case PPC_TDESC_BASE:
return tdesc_powerpc_32l;
@@ -214,6 +216,8 @@ get_ipa_tdesc (int idx)
return tdesc_powerpc_isa205_ppr_dscr_vsx32l;
case PPC_TDESC_ISA207_VSX:
return tdesc_powerpc_isa207_vsx32l;
+ case PPC_TDESC_ISA207_HTM_VSX:
+ return tdesc_powerpc_isa207_htm_vsx32l;
case PPC_TDESC_E500:
return tdesc_powerpc_e500l;
#endif
@@ -244,6 +248,7 @@ initialize_low_tracepoint (void)
init_registers_powerpc_isa205_vsx64l ();
init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
init_registers_powerpc_isa207_vsx64l ();
+ init_registers_powerpc_isa207_htm_vsx64l ();
#else
init_registers_powerpc_32l ();
init_registers_powerpc_altivec32l ();
@@ -254,6 +259,7 @@ initialize_low_tracepoint (void)
init_registers_powerpc_isa205_vsx32l ();
init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
init_registers_powerpc_isa207_vsx32l ();
+ init_registers_powerpc_isa207_htm_vsx32l ();
init_registers_powerpc_e500l ();
#endif
}
diff --git a/gdb/gdbserver/linux-ppc-low.c b/gdb/gdbserver/linux-ppc-low.c
index 6c27368a36..2c830d638a 100644
--- a/gdb/gdbserver/linux-ppc-low.c
+++ b/gdb/gdbserver/linux-ppc-low.c
@@ -526,6 +526,127 @@ ppc_store_tarregset (struct regcache *regcache, const void *buf)
}
static void
+ppc_fill_tm_sprregset (struct regcache *regcache, void *buf)
+{
+ int i, base;
+ char *regset = (char *) buf;
+
+ base = find_regno (regcache->tdesc, "tfhar");
+ for (i = 0; i < 3; i++)
+ collect_register (regcache, base + i, ®set[i*8]);
+}
+
+static void
+ppc_store_tm_sprregset (struct regcache *regcache, const void *buf)
+{
+ int i, base;
+ char *regset = (char *) buf;
+
+ base = find_regno (regcache->tdesc, "tfhar");
+ for (i = 0; i < 3; i++)
+ supply_register (regcache, base + i, ®set[i*8]);
+}
+
+static void
+ppc_store_tm_cgprregset (struct regcache *regcache, const void *buf)
+{
+ int i, base, size, endian_offset;
+ char *regset = (char *) buf;
+
+ base = find_regno (regcache->tdesc, "cr0");
+ size = register_size (regcache->tdesc, base);
+
+ gdb_assert (size == 4 || size == 8);
+
+ for (i = 0; i < 32; i++)
+ supply_register (regcache, base + i, ®set[i*size]);
+
+ endian_offset = 0;
+
+ if ((size == 8) && (__BYTE_ORDER == __BIG_ENDIAN))
+ endian_offset = 4;
+
+ supply_register_by_name (regcache, "ccr",
+ ®set[PT_CCR * size + endian_offset]);
+
+ supply_register_by_name (regcache, "cxer",
+ ®set[PT_XER * size + endian_offset]);
+
+ supply_register_by_name (regcache, "clr", ®set[PT_LNK * size]);
+ supply_register_by_name (regcache, "cctr", ®set[PT_CTR * size]);
+}
+
+static void
+ppc_store_tm_cfprregset (struct regcache *regcache, const void *buf)
+{
+ int i, base;
+ char *regset = (char *) buf;
+
+ base = find_regno (regcache->tdesc, "cf0");
+
+ for (i = 0; i < 32; i++)
+ supply_register (regcache, base + i, ®set[i*8]);
+
+ supply_register_by_name (regcache, "cfpscr", ®set[32*8]);
+}
+
+static void
+ppc_store_tm_cvrregset (struct regcache *regcache, const void *buf)
+{
+ int i, base;
+ char *regset = (char *) buf;
+ int vscr_offset = 0;
+
+ base = find_regno (regcache->tdesc, "cvr0");
+
+ for (i = 0; i < 32; i++)
+ supply_register (regcache, base + i, ®set[i*16]);
+
+ if (__BYTE_ORDER == __BIG_ENDIAN)
+ vscr_offset = 12;
+
+ supply_register_by_name (regcache, "cvscr",
+ ®set[32 * 16 + vscr_offset]);
+
+ supply_register_by_name (regcache, "cvrsave", ®set[33 * 16]);
+}
+
+static void
+ppc_store_tm_cvsxregset (struct regcache *regcache, const void *buf)
+{
+ int i, base;
+ const char *regset = (const char *) buf;
+
+ base = find_regno (regcache->tdesc, "cvs0h");
+ for (i = 0; i < 32; i++)
+ supply_register (regcache, base + i, ®set[i * 8]);
+}
+
+static void
+ppc_store_tm_cpprregset (struct regcache *regcache, const void *buf)
+{
+ const char *cppr = (const char *) buf;
+
+ supply_register_by_name (regcache, "cppr", cppr);
+}
+
+static void
+ppc_store_tm_cdscrregset (struct regcache *regcache, const void *buf)
+{
+ const char *cdscr = (const char *) buf;
+
+ supply_register_by_name (regcache, "cdscr", cdscr);
+}
+
+static void
+ppc_store_tm_ctarregset (struct regcache *regcache, const void *buf)
+{
+ const char *ctar = (const char *) buf;
+
+ supply_register_by_name (regcache, "ctar", ctar);
+}
+
+static void
ppc_fill_vsxregset (struct regcache *regcache, void *buf)
{
int i, base;
@@ -638,6 +759,22 @@ static struct regset_info ppc_regsets[] = {
fetch them every time, but still fall back to PTRACE_PEEKUSER for the
general registers. Some kernels support these, but not the newer
PPC_PTRACE_GETREGS. */
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CTAR, 0, EXTENDED_REGS,
+ NULL, ppc_store_tm_ctarregset },
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CDSCR, 0, EXTENDED_REGS,
+ NULL, ppc_store_tm_cdscrregset },
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CPPR, 0, EXTENDED_REGS,
+ NULL, ppc_store_tm_cpprregset },
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVSX, 0, EXTENDED_REGS,
+ NULL, ppc_store_tm_cvsxregset },
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVMX, 0, EXTENDED_REGS,
+ NULL, ppc_store_tm_cvrregset },
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CFPR, 0, EXTENDED_REGS,
+ NULL, ppc_store_tm_cfprregset },
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CGPR, 0, EXTENDED_REGS,
+ NULL, ppc_store_tm_cgprregset },
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_SPR, 0, EXTENDED_REGS,
+ ppc_fill_tm_sprregset, ppc_store_tm_sprregset },
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TAR, 0, EXTENDED_REGS,
ppc_fill_tarregset, ppc_store_tarregset },
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS,
@@ -720,7 +857,13 @@ ppc_arch_setup (void)
&& (ppc_hwcap2 & PPC_FEATURE2_TAR)
&& ppc_check_regset (tid, NT_PPC_TAR,
PPC_LINUX_SIZEOF_TARREGSET))
- features.isa207 = true;
+ {
+ features.isa207 = true;
+ if ((ppc_hwcap2 & PPC_FEATURE2_HTM)
+ && ppc_check_regset (tid, NT_PPC_TM_SPR,
+ PPC_LINUX_SIZEOF_TM_SPRREGSET))
+ features.htm = true;
+ }
}
if (ppc_hwcap & PPC_FEATURE_CELL)
@@ -782,6 +925,42 @@ ppc_arch_setup (void)
regset->size = (features.isa207 ?
PPC_LINUX_SIZEOF_TARREGSET : 0);
break;
+ case NT_PPC_TM_SPR:
+ regset->size = (features.htm ?
+ PPC_LINUX_SIZEOF_TM_SPRREGSET : 0);
+ break;
+ case NT_PPC_TM_CGPR:
+ if (features.wordsize == 4)
+ regset->size = (features.htm ?
+ PPC32_LINUX_SIZEOF_CGPRREGSET : 0);
+ else
+ regset->size = (features.htm ?
+ PPC64_LINUX_SIZEOF_CGPRREGSET : 0);
+ break;
+ case NT_PPC_TM_CFPR:
+ regset->size = (features.htm ?
+ PPC_LINUX_SIZEOF_CFPRREGSET : 0);
+ break;
+ case NT_PPC_TM_CVMX:
+ regset->size = (features.htm ?
+ PPC_LINUX_SIZEOF_CVMXREGSET : 0);
+ break;
+ case NT_PPC_TM_CVSX:
+ regset->size = (features.htm ?
+ PPC_LINUX_SIZEOF_CVSXREGSET : 0);
+ break;
+ case NT_PPC_TM_CPPR:
+ regset->size = (features.htm ?
+ PPC_LINUX_SIZEOF_CPPRREGSET : 0);
+ break;
+ case NT_PPC_TM_CDSCR:
+ regset->size = (features.htm ?
+ PPC_LINUX_SIZEOF_CDSCRREGSET : 0);
+ break;
+ case NT_PPC_TM_CTAR:
+ regset->size = (features.htm ?
+ PPC_LINUX_SIZEOF_CTARREGSET : 0);
+ break;
default:
break;
}
@@ -3165,6 +3344,8 @@ ppc_get_ipa_tdesc_idx (void)
return PPC_TDESC_ISA205_PPR_DSCR_VSX;
if (tdesc == tdesc_powerpc_isa207_vsx64l)
return PPC_TDESC_ISA207_VSX;
+ if (tdesc == tdesc_powerpc_isa207_htm_vsx64l)
+ return PPC_TDESC_ISA207_HTM_VSX;
#endif
if (tdesc == tdesc_powerpc_32l)
@@ -3185,6 +3366,8 @@ ppc_get_ipa_tdesc_idx (void)
return PPC_TDESC_ISA205_PPR_DSCR_VSX;
if (tdesc == tdesc_powerpc_isa207_vsx32l)
return PPC_TDESC_ISA207_VSX;
+ if (tdesc == tdesc_powerpc_isa207_htm_vsx32l)
+ return PPC_TDESC_ISA207_HTM_VSX;
if (tdesc == tdesc_powerpc_e500l)
return PPC_TDESC_E500;
@@ -3245,6 +3428,7 @@ initialize_low_arch (void)
init_registers_powerpc_isa205_vsx32l ();
init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
init_registers_powerpc_isa207_vsx32l ();
+ init_registers_powerpc_isa207_htm_vsx32l ();
init_registers_powerpc_e500l ();
#if __powerpc64__
init_registers_powerpc_64l ();
@@ -3256,6 +3440,7 @@ initialize_low_arch (void)
init_registers_powerpc_isa205_vsx64l ();
init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
init_registers_powerpc_isa207_vsx64l ();
+ init_registers_powerpc_isa207_htm_vsx64l ();
#endif
initialize_regsets_info (&ppc_regsets_info);
diff --git a/gdb/gdbserver/linux-ppc-tdesc-init.h b/gdb/gdbserver/linux-ppc-tdesc-init.h
index 29b8122886..d1dfdad571 100644
--- a/gdb/gdbserver/linux-ppc-tdesc-init.h
+++ b/gdb/gdbserver/linux-ppc-tdesc-init.h
@@ -31,6 +31,7 @@ enum ppc_linux_tdesc {
PPC_TDESC_ISA205_VSX,
PPC_TDESC_ISA205_PPR_DSCR_VSX,
PPC_TDESC_ISA207_VSX,
+ PPC_TDESC_ISA207_HTM_VSX,
PPC_TDESC_E500,
};
@@ -63,6 +64,9 @@ void init_registers_powerpc_isa205_ppr_dscr_vsx32l (void);
/* Defined in auto-generated file powerpc-isa207-vsx32l.c. */
void init_registers_powerpc_isa207_vsx32l (void);
+/* Defined in auto-generated file powerpc-isa207-htm-vsx32l.c. */
+void init_registers_powerpc_isa207_htm_vsx32l (void);
+
/* Defined in auto-generated file powerpc-e500l.c. */
void init_registers_powerpc_e500l (void);
@@ -97,4 +101,7 @@ void init_registers_powerpc_isa205_ppr_dscr_vsx64l (void);
/* Defined in auto-generated file powerpc-isa207-vsx64l.c. */
void init_registers_powerpc_isa207_vsx64l (void);
+/* Defined in auto-generated file powerpc-isa207-htm-vsx64l.c. */
+void init_registers_powerpc_isa207_htm_vsx64l (void);
+
#endif
--
2.13.6
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 14/17] [PowerPC] Add gdbserver support for HTM registers
2018-07-13 13:53 ` [PATCH 14/17] [PowerPC] Add gdbserver support for HTM registers Pedro Franco de Carvalho
@ 2018-07-13 16:26 ` Ulrich Weigand
0 siblings, 0 replies; 38+ messages in thread
From: Ulrich Weigand @ 2018-07-13 16:26 UTC (permalink / raw)
To: Pedro Franco de Carvalho; +Cc: gdb-patches, edjunior
Pedro Franco de Carvalho wrote:
> The "fill" functions for checkpointed register sets are not
> implemented, because ptrace can return ENODATA for these regsets
> whenever the inferior is not in a transaction.
>
> Since gdbserver writes all registers in one go before resuming the
> inferior, this error would not be detected at the time the user tries
> to write to one of the registers on the client side, and gdbserver
> would print out warnings every time it resumes the inferior when it is
> not in a transaction, so there is currently no straightforward way to
> handle this case. This means the checkpointed registers in the
> client-side regcache can become dirty when the user tries to write to
> them, until the inferior is resumed and stopped again.
>
> Another limitation for the checkpointed registers is that traceframes
> don't record if registers are available or not, so if these registers
> are collected when a tracepoint is hit and the inferior is not in a
> transaction, the user will see zero values for all of them, instead of
> the usual <unavailable>.
Hmm. It's a bit unfortunate to have these differences between native
and gdbserver debugging. But I guess this is unavoidable for now.
> gdb/gdbserver/ChangeLog:
> 2018-07-05 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
>
> * linux-ppc-tdesc-init.h (enum ppc_linux_tdesc)
> <PPC_TDESC_ISA207_HTM_VSX>: New enum value.
> (init_registers_powerpc_isa207_htm_vsx32l)
> (init_registers_powerpc_isa207_htm_vsx64l): Declare.
> * linux-ppc-low.c (ppc_fill_tm_sprregset, ppc_store_tm_sprregset)
> (ppc_store_tm_cgprregset, ppc_store_tm_cfprregset)
> (ppc_store_tm_cvrregset, ppc_store_tm_cvsxregset)
> (ppc_store_tm_cpprregset, ppc_store_tm_cdscrregset)
> (ppc_store_tm_ctarregset): New functions.
> (ppc_regsets): Add entries for HTM regsets.
> (ppc_arch_setup): Set htm in features struct when needed. Set
> sizes for the HTM regsets.
> (ppc_get_ipa_tdesc_idx): Return PPC_TDESC_ISA207_HTM_VSX.
> (initialize_low_arch): Call
> init_registers_powerpc_isa207_htm_vsx32l and
> init_registers_powerpc_isa207_htm_vsx64l.
> * linux-ppc-ipa.c (get_ipa_tdesc): Handle
> PPC_TDESC_ISA207_HTM_VSX.
> (initialize_low_tracepoint): Call
> init_registers_powerpc_isa207_htm_vsx32l and
> init_registers_powerpc_isa207_htm_vsx64l.
This is OK once base support is in.
Thanks,
Ulrich
--
Dr. Ulrich Weigand
GNU/Linux compilers and toolchain
Ulrich.Weigand@de.ibm.com
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 06/17] [PowerPC] Add record/replay support for PPR and DSCR
2018-07-13 13:53 [PATCH 00/17] GDB support for more powerpc registers on linux Pedro Franco de Carvalho
` (12 preceding siblings ...)
2018-07-13 13:53 ` [PATCH 14/17] [PowerPC] Add gdbserver support for HTM registers Pedro Franco de Carvalho
@ 2018-07-13 13:53 ` Pedro Franco de Carvalho
2018-07-13 15:25 ` Ulrich Weigand
2018-07-13 14:23 ` [PATCH 15/17] [PowerPC] Add tests for HTM registers Pedro Franco de Carvalho
` (2 subsequent siblings)
16 siblings, 1 reply; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 13:53 UTC (permalink / raw)
To: gdb-patches; +Cc: uweigand, edjunior
This patch changes ppc_process_record_op31 to handle instructions that
change PPR and DSCR.
gdb/ChangeLog:
YYYY-MM-DD Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* rs6000-tdep.c (ppc_process_record_op31): Record changes to PPR
and DSCR.
---
gdb/rs6000-tdep.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index 294d6ea702..f390370455 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -4428,6 +4428,16 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
case 476: /* NAND */
case 412: /* OR with Complement */
case 444: /* OR */
+ /* Or Rx,Rx,Rx alters PRI in PPR. */
+ if (tdep->ppc_ppr_regnum >= 0
+ && (PPC_RS (insn) == PPC_RA (insn))
+ && (PPC_RA (insn) == PPC_RB (insn))
+ && !PPC_RC (insn))
+ {
+ record_full_arch_list_add_reg (regcache, tdep->ppc_ppr_regnum);
+ return 0;
+ }
+ /* FALL-THROUGH */
case 536: /* Shift Right Word */
case 539: /* Shift Right Doubleword */
case 922: /* Extend Sign Halfword */
@@ -4646,6 +4656,10 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
case 1: /* XER */
record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
return 0;
+ case 3: /* DSCR */
+ if (tdep->ppc_dscr_regnum >= 0)
+ record_full_arch_list_add_reg (regcache, tdep->ppc_dscr_regnum);
+ return 0;
case 8: /* LR */
record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum);
return 0;
@@ -4655,6 +4669,11 @@ ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
case 256: /* VRSAVE */
record_full_arch_list_add_reg (regcache, tdep->ppc_vrsave_regnum);
return 0;
+ case 896:
+ case 898: /* PPR */
+ if (tdep->ppc_ppr_regnum >= 0)
+ record_full_arch_list_add_reg (regcache, tdep->ppc_ppr_regnum);
+ return 0;
}
goto UNKNOWN_OP;
--
2.13.6
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 06/17] [PowerPC] Add record/replay support for PPR and DSCR
2018-07-13 13:53 ` [PATCH 06/17] [PowerPC] Add record/replay support for PPR and DSCR Pedro Franco de Carvalho
@ 2018-07-13 15:25 ` Ulrich Weigand
0 siblings, 0 replies; 38+ messages in thread
From: Ulrich Weigand @ 2018-07-13 15:25 UTC (permalink / raw)
To: Pedro Franco de Carvalho; +Cc: gdb-patches, edjunior
Pedro Franco de Carvalho wrote:
> gdb/ChangeLog:
> YYYY-MM-DD Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
>
> * rs6000-tdep.c (ppc_process_record_op31): Record changes to PPR
> and DSCR.
> case 476: /* NAND */
> case 412: /* OR with Complement */
> case 444: /* OR */
> + /* Or Rx,Rx,Rx alters PRI in PPR. */
> + if (tdep->ppc_ppr_regnum >= 0
> + && (PPC_RS (insn) == PPC_RA (insn))
> + && (PPC_RA (insn) == PPC_RB (insn))
> + && !PPC_RC (insn))
> + {
> + record_full_arch_list_add_reg (regcache, tdep->ppc_ppr_regnum);
> + return 0;
> + }
This should be done *only* for OR, not for any of the others that
fall through to the above code ...
Otherwise, this is OK.
Thanks,
Ulrich
--
Dr. Ulrich Weigand
GNU/Linux compilers and toolchain
Ulrich.Weigand@de.ibm.com
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 15/17] [PowerPC] Add tests for HTM registers
2018-07-13 13:53 [PATCH 00/17] GDB support for more powerpc registers on linux Pedro Franco de Carvalho
` (13 preceding siblings ...)
2018-07-13 13:53 ` [PATCH 06/17] [PowerPC] Add record/replay support for PPR and DSCR Pedro Franco de Carvalho
@ 2018-07-13 14:23 ` Pedro Franco de Carvalho
2018-07-13 16:27 ` Ulrich Weigand
2018-07-13 14:49 ` [PATCH 17/17] [PowerPC] Add gdbserver support for EBB and PMU registers Pedro Franco de Carvalho
2018-07-13 15:33 ` [PATCH 11/17] [PowerPC] Add gdbserver support for TAR Pedro Franco de Carvalho
16 siblings, 1 reply; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 14:23 UTC (permalink / raw)
To: gdb-patches; +Cc: uweigand, edjunior
This patch adds a test for acces to checkpointed HTM registers in
GDB.
The tests records the values of the regular registers before stepping
the inferior through a "tbegin." instruction to start a transaction,
then the checkpointed registers are checked against the recorded
pre-transactional values. New values are written to the checkpointed
registers and recorded, the inferior continues until the transaction
aborts (which is usually immediately when it is resumed), and the
regular registers are checked against the recorded values, because the
abort should have reverted the registers to these values.
gdb/testsuite/ChangeLog:
YYYY-MM-DD Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.arch/powerpc-htm-regs.c: New file.
* gdb.arch/powerpc-htm-regs.exp: New file.
---
gdb/testsuite/gdb.arch/powerpc-htm-regs.c | 34 +++
gdb/testsuite/gdb.arch/powerpc-htm-regs.exp | 311 ++++++++++++++++++++++++++++
2 files changed, 345 insertions(+)
create mode 100644 gdb/testsuite/gdb.arch/powerpc-htm-regs.c
create mode 100644 gdb/testsuite/gdb.arch/powerpc-htm-regs.exp
diff --git a/gdb/testsuite/gdb.arch/powerpc-htm-regs.c b/gdb/testsuite/gdb.arch/powerpc-htm-regs.c
new file mode 100644
index 0000000000..14992039db
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/powerpc-htm-regs.c
@@ -0,0 +1,34 @@
+/* This test is part of GDB, the GNU debugger.
+
+ Copyright 2018 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+int main (void)
+{
+ /* Touch DSCR. Some kernels won't schedule the thread with a DSCR
+ altered by ptrace unless the register was used at some point. */
+ unsigned long dscr = 0x0;
+ asm volatile ("mtdscr %0" : : "r" (dscr));
+
+ asm volatile ("tbegin."); // first marker
+ asm volatile goto ("bc 12,2,%l[end]"
+ :
+ :
+ :
+ : end);
+ asm volatile ("tabort. 0");
+end:
+ asm volatile ("nop"); // second marker
+}
diff --git a/gdb/testsuite/gdb.arch/powerpc-htm-regs.exp b/gdb/testsuite/gdb.arch/powerpc-htm-regs.exp
new file mode 100644
index 0000000000..07db95e71c
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/powerpc-htm-regs.exp
@@ -0,0 +1,311 @@
+# Copyright 2018 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+# This file is part of the gdb testsuite.
+
+# Test access to HTM (hardware transactional memory) registers.
+
+if {![istarget "powerpc*-*-linux*"]} then {
+ verbose "Skipping PowerPC test for HTM registers."
+ return
+}
+
+standard_testfile .c .gen.c
+
+# First check if our processor and kernel support access to
+# the registers we need and to the HTM facility.
+
+set gen_src [standard_output_file $srcfile2]
+
+gdb_produce_source $gen_src {
+ int main() {
+ asm volatile ("tbegin."); // marker
+ asm volatile ("nop");
+ return 0;
+ }
+}
+
+if {[build_executable "compile" $binfile $gen_src {debug}] == -1} {
+ return
+}
+
+clean_restart $binfile
+
+set bp_line [gdb_get_line_number "marker" "$gen_src"]
+
+# Displaced-stepping a tbegin. causes problems,
+# so we make the breakpoint temporary.
+gdb_breakpoint ${gen_src}:${bp_line} {temporary}
+
+gdb_run_cmd
+
+# Wait for the prompt.
+if {[gdb_test "" "Temporary breakpoint.*"] != 0 } {
+ return
+}
+
+# Make sure that we stopped at the right place (just before tbegin. is
+# executed).
+if { [gdb_test "x/i \$pc" "=> $hex.*:.*tbegin\\..*" "disassemble tbegin"] != 0} {
+ return
+}
+
+proc check_register_access { regname } {
+ global gdb_prompt
+
+ set test "$regname register access"
+ gdb_test_multiple "info reg $regname" "$test" {
+ -re "Invalid register.*\r\n$gdb_prompt $" {
+ unsupported "$test"
+ return 0
+ }
+ -re "\r\n$regname.*\r\n$gdb_prompt $" {
+ pass "$test"
+ return 1
+ }
+ }
+ return 0
+}
+
+if {![check_register_access "vs0"]} {
+ return
+}
+
+if {![check_register_access "texasr"]} {
+ return
+}
+
+if {![check_register_access "dscr"]} {
+ return
+}
+
+if {![check_register_access "ppr"]} {
+ return
+}
+
+if {![check_register_access "tar"]} {
+ return
+}
+
+proc check_htm_support {} {
+ global gdb_prompt
+ set test "HTM support"
+
+ gdb_test_multiple "stepi" "$test" {
+ -re "Illegal instruction.*\r\n$gdb_prompt $" {
+ unsupported $test
+ return 0
+ }
+ -re "nop.*\r\n$gdb_prompt $"
+ {
+ pass $test
+ return 1
+ }
+ }
+ return 0;
+}
+
+if {![check_htm_support]} {
+ return
+}
+
+# Now do the actual test.
+if {[build_executable "compile" $binfile $srcfile {debug}] == -1} {
+ return
+}
+
+clean_restart $binfile
+
+set bp_line [gdb_get_line_number "first marker"]
+
+clean_restart $binfile
+
+gdb_breakpoint ${srcfile}:${bp_line} {temporary}
+
+gdb_run_cmd
+
+# Wait for the prompt.
+gdb_test "Temporary breakpoint.*"
+
+if {[gdb_test "x/i \$pc" "=> $hex.*:.*tbegin\\..*" "disassemble tbegin"] != 0} {
+ return
+}
+
+# Now we write non-zero values to some registers, then read the values
+# of various registers, then stepi to start the transaction. The
+# checkpointed register state should correspond to the values we read.
+
+# Write to the GPRs
+for {set i 0} {$i < 32} {incr i 1} {
+ gdb_test_no_output "set \$r$i = $i"
+}
+
+gdb_test_no_output "set \$xer = 0xc0000000"
+
+# FPRs
+gdb_test_no_output "set \$f0 = 0.5"
+for {set i 1} {$i < 32} {incr i 1} {
+ gdb_test_no_output "set \$f$i = \$f[expr $i - 1] + 1.0"
+}
+
+gdb_test_no_output "set \$fpscr = 0x84005000"
+
+# VRs
+for {set i 0} {$i < 32} {incr i 1} {
+ for {set j 0} {$j < 4} {incr j 1} {
+ gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = $i"
+ }
+}
+
+gdb_test_no_output "set \$dscr = 0x2"
+gdb_test_no_output "set \$tar = &main"
+
+# Get the pre-transactional value of the registers.
+for {set i 0} {$i < 32} {incr i 1} {
+ set "r$i" [get_hexadecimal_valueof "\$r$i" "default0"]
+}
+
+set cr [get_hexadecimal_valueof "\$cr" "default0"]
+set xer [get_hexadecimal_valueof "\$xer" "default0"]
+set lr [get_hexadecimal_valueof "\$lr" "default0"]
+set ctr [get_hexadecimal_valueof "\$ctr" "default0"]
+
+for {set i 0} {$i < 32} {incr i 1} {
+ set "f$i" [get_valueof "" "\$f$i" "default0"]
+}
+
+set fpscr [get_hexadecimal_valueof "\$fpscr" "default0"]
+
+for {set i 0} {$i < 32} {incr i 1} {
+ set "vr$i" [get_hexadecimal_valueof "\$vr$i.uint128" "default0"]
+}
+
+set vscr [get_hexadecimal_valueof "\$vscr" "default0"]
+set vrsave [get_hexadecimal_valueof "\$vrsave" "default0"]
+
+for {set i 0} {$i < 64} {incr i 1} {
+ set "vs$i" [get_hexadecimal_valueof "\$vs$i.uint128" "default0"]
+}
+
+set dscr [get_hexadecimal_valueof "\$dscr" "default0"]
+set ppr [get_hexadecimal_valueof "\$ppr" "default0"]
+set tar [get_hexadecimal_valueof "\$tar" "default0"]
+
+gdb_test "stepi" "asm.*bc.*"
+
+proc test_register_match {reg_name reg_var_name hex} {
+ set test "$reg_name matches $reg_var_name"
+
+ upvar $reg_var_name expected_val
+
+ if {$hex} {
+ set actual_val [get_hexadecimal_valueof "\$$reg_name" "default1"]
+ } else {
+ set actual_val [get_valueof "" "\$$reg_name" "default1"]
+ }
+
+ if { "$expected_val" == "$actual_val" } {
+ pass $test
+ } else {
+ fail $test
+ }
+}
+
+for {set i 0} {$i < 32} {incr i 1} {
+ test_register_match "cr$i" "r$i" 1
+}
+
+test_register_match "ccr" "cr" 1
+test_register_match "cxer" "xer" 1
+test_register_match "clr" "lr" 1
+test_register_match "cctr" "ctr" 1
+
+for {set i 0} {$i < 32} {incr i 1} {
+ test_register_match "cf$i" "f$i" 0
+}
+
+test_register_match "cfpscr" "fpscr" 1
+
+for {set i 0} {$i < 32} {incr i 1} {
+ test_register_match "cvr$i.uint128" "vr$i" 1
+}
+
+test_register_match "cvscr" "vscr" 1
+test_register_match "cvrsave" "vrsave" 1
+
+for {set i 0} {$i < 64} {incr i 1} {
+ test_register_match "cvs$i.uint128" "vs$i" 1
+}
+
+test_register_match "cdscr" "dscr" 1
+test_register_match "cppr" "ppr" 1
+test_register_match "ctar" "tar" 1
+
+# Support for writing to the checkpointed registers is not
+# currently available in the gdbserver stub.
+if [target_is_gdbserver] {
+ unsupported "write to checkpointed registers"
+ return
+}
+
+# Now write different values to some of the checkpointed registers and
+# check that the transaction abort reverts the register to these
+# values.
+for {set i 0} {$i < 32} {incr i 1} {
+ gdb_test_no_output "set \$cr$i = $i + 0xC00"
+}
+
+gdb_test_no_output "set \$cf0 = 0.25"
+for {set i 1} {$i < 32} {incr i 1} {
+ gdb_test_no_output "set \$cf$i = \$cf[expr $i - 1] + 1.0"
+}
+
+for {set i 0} {$i < 32} {incr i 1} {
+ for {set j 0} {$j < 4} {incr j 1} {
+ gdb_test_no_output "set \$cvr$i.v4_int32\[$j\] = $i + 0xF00"
+ }
+}
+
+# Read back the values.
+for {set i 0} {$i < 32} {incr i 1} {
+ set "cr$i" [get_hexadecimal_valueof "\$cr$i" "default0"]
+}
+
+for {set i 0} {$i < 32} {incr i 1} {
+ set "cf$i" [get_valueof "" "\$cf$i" "default0"]
+}
+
+for {set i 0} {$i < 64} {incr i 1} {
+ set "cvs$i" [get_hexadecimal_valueof "\$cvs$i.uint128" "default0"]
+}
+
+set bp_line [gdb_get_line_number "second marker"]
+
+gdb_breakpoint ${srcfile}:${bp_line}
+
+gdb_test "continue"
+
+for {set i 0} {$i < 32} {incr i 1} {
+ test_register_match "r$i" "cr$i" 1
+}
+
+for {set i 0} {$i < 32} {incr i 1} {
+ test_register_match "f$i" "cf$i" 0
+}
+
+for {set i 0} {$i < 64} {incr i 1} {
+ test_register_match "vs$i.uint128" "cvs$i" 1
+}
+
--
2.13.6
^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH 17/17] [PowerPC] Add gdbserver support for EBB and PMU registers
2018-07-13 13:53 [PATCH 00/17] GDB support for more powerpc registers on linux Pedro Franco de Carvalho
` (14 preceding siblings ...)
2018-07-13 14:23 ` [PATCH 15/17] [PowerPC] Add tests for HTM registers Pedro Franco de Carvalho
@ 2018-07-13 14:49 ` Pedro Franco de Carvalho
2018-07-13 16:40 ` Ulrich Weigand
2018-07-13 15:33 ` [PATCH 11/17] [PowerPC] Add gdbserver support for TAR Pedro Franco de Carvalho
16 siblings, 1 reply; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 14:49 UTC (permalink / raw)
To: gdb-patches; +Cc: uweigand, edjunior
This patch extends support for EBB and PMU registers to the powerpc
linux gdbserver stub.
gdb/gdbserver/ChangeLog:
YYYY-MM-DD Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* linux-ppc-low.c (ppc_store_ebbregset, ppc_store_pmuregset): New
functions.
(ppc_regsets): Add entries for ebb and pmu regsets.
(ppc_arch_setup): Set isa207 in features struct if the ebb and pmu
regsets are available. Set sizes for these regsets.
---
gdb/gdbserver/linux-ppc-low.c | 50 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/gdb/gdbserver/linux-ppc-low.c b/gdb/gdbserver/linux-ppc-low.c
index 2c830d638a..9d1845088b 100644
--- a/gdb/gdbserver/linux-ppc-low.c
+++ b/gdb/gdbserver/linux-ppc-low.c
@@ -526,6 +526,38 @@ ppc_store_tarregset (struct regcache *regcache, const void *buf)
}
static void
+ppc_store_ebbregset (struct regcache *regcache, const void *buf)
+{
+ int base;
+ char *regset = (char *) buf;
+
+ base = find_regno (regcache->tdesc, "bescr");
+
+ /* The order in the kernel regset is: EBBRR, EBBHR, BESCR, in our
+ .dat file it is BESCR, EBBHR, EBBRR. */
+ supply_register (regcache, base, ®set[16]);
+ supply_register (regcache, base + 1, ®set[8]);
+ supply_register (regcache, base + 2, ®set[0]);
+}
+
+static void
+ppc_store_pmuregset (struct regcache *regcache, const void *buf)
+{
+ int base;
+ char *regset = (char *) buf;
+
+ base = find_regno (regcache->tdesc, "mmcr0");
+
+ /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
+ In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
+ supply_register (regcache, base, ®set[32]);
+ supply_register (regcache, base + 1, ®set[24]);
+ supply_register (regcache, base + 2, ®set[0]);
+ supply_register (regcache, base + 3, ®set[8]);
+ supply_register (regcache, base + 4, ®set[16]);
+}
+
+static void
ppc_fill_tm_sprregset (struct regcache *regcache, void *buf)
{
int i, base;
@@ -775,6 +807,10 @@ static struct regset_info ppc_regsets[] = {
NULL, ppc_store_tm_cgprregset },
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_SPR, 0, EXTENDED_REGS,
ppc_fill_tm_sprregset, ppc_store_tm_sprregset },
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_EBB, 0, EXTENDED_REGS,
+ NULL, ppc_store_ebbregset },
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PMU, 0, EXTENDED_REGS,
+ NULL, ppc_store_pmuregset },
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TAR, 0, EXTENDED_REGS,
ppc_fill_tarregset, ppc_store_tarregset },
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS,
@@ -856,7 +892,11 @@ ppc_arch_setup (void)
if ((ppc_hwcap2 & PPC_FEATURE2_ARCH_2_07)
&& (ppc_hwcap2 & PPC_FEATURE2_TAR)
&& ppc_check_regset (tid, NT_PPC_TAR,
- PPC_LINUX_SIZEOF_TARREGSET))
+ PPC_LINUX_SIZEOF_TARREGSET)
+ && ppc_check_regset (tid, NT_PPC_EBB,
+ PPC_LINUX_SIZEOF_EBBREGSET)
+ && ppc_check_regset (tid, NT_PPC_PMU,
+ PPC_LINUX_SIZEOF_PMUREGSET))
{
features.isa207 = true;
if ((ppc_hwcap2 & PPC_FEATURE2_HTM)
@@ -925,6 +965,14 @@ ppc_arch_setup (void)
regset->size = (features.isa207 ?
PPC_LINUX_SIZEOF_TARREGSET : 0);
break;
+ case NT_PPC_EBB:
+ regset->size = (features.isa207 ?
+ PPC_LINUX_SIZEOF_EBBREGSET : 0);
+ break;
+ case NT_PPC_PMU:
+ regset->size = (features.isa207 ?
+ PPC_LINUX_SIZEOF_PMUREGSET : 0);
+ break;
case NT_PPC_TM_SPR:
regset->size = (features.htm ?
PPC_LINUX_SIZEOF_TM_SPRREGSET : 0);
--
2.13.6
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 17/17] [PowerPC] Add gdbserver support for EBB and PMU registers
2018-07-13 14:49 ` [PATCH 17/17] [PowerPC] Add gdbserver support for EBB and PMU registers Pedro Franco de Carvalho
@ 2018-07-13 16:40 ` Ulrich Weigand
2018-07-13 18:29 ` Pedro Franco de Carvalho
0 siblings, 1 reply; 38+ messages in thread
From: Ulrich Weigand @ 2018-07-13 16:40 UTC (permalink / raw)
To: Pedro Franco de Carvalho; +Cc: gdb-patches, edjunior
Pedro Franco de Carvalho wrote:
> +ppc_store_ebbregset (struct regcache *regcache, const void *buf)
> +{
> + int base;
> + char *regset = (char *) buf;
> +
> + base = find_regno (regcache->tdesc, "bescr");
> +
> + /* The order in the kernel regset is: EBBRR, EBBHR, BESCR, in our
> + .dat file it is BESCR, EBBHR, EBBRR. */
> + supply_register (regcache, base, ®set[16]);
> + supply_register (regcache, base + 1, ®set[8]);
> + supply_register (regcache, base + 2, ®set[0]);
Why do this? Can't we recorder the XML file to make the order
the same, and simplify this routine?
> + /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
> + In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
> + supply_register (regcache, base, ®set[32]);
> + supply_register (regcache, base + 1, ®set[24]);
> + supply_register (regcache, base + 2, ®set[0]);
> + supply_register (regcache, base + 3, ®set[8]);
> + supply_register (regcache, base + 4, ®set[16]);
Same here?
Bye,
Ulrich
--
Dr. Ulrich Weigand
GNU/Linux compilers and toolchain
Ulrich.Weigand@de.ibm.com
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 17/17] [PowerPC] Add gdbserver support for EBB and PMU registers
2018-07-13 16:40 ` Ulrich Weigand
@ 2018-07-13 18:29 ` Pedro Franco de Carvalho
0 siblings, 0 replies; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 18:29 UTC (permalink / raw)
To: Ulrich Weigand; +Cc: gdb-patches, edjunior
Ulrich Weigand <uweigand@de.ibm.com> writes:
> Pedro Franco de Carvalho wrote:
>
>> +ppc_store_ebbregset (struct regcache *regcache, const void *buf)
>> +{
>> + int base;
>> + char *regset = (char *) buf;
>> +
>> + base = find_regno (regcache->tdesc, "bescr");
>> +
>> + /* The order in the kernel regset is: EBBRR, EBBHR, BESCR, in our
>> + .dat file it is BESCR, EBBHR, EBBRR. */
>> + supply_register (regcache, base, ®set[16]);
>> + supply_register (regcache, base + 1, ®set[8]);
>> + supply_register (regcache, base + 2, ®set[0]);
>
> Why do this? Can't we recorder the XML file to make the order
> the same, and simplify this routine?
>
>> + /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
>> + In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
>> + supply_register (regcache, base, ®set[32]);
>> + supply_register (regcache, base + 1, ®set[24]);
>> + supply_register (regcache, base + 2, ®set[0]);
>> + supply_register (regcache, base + 3, ®set[8]);
>> + supply_register (regcache, base + 4, ®set[16]);
>
> Same here?
I wanted to keep the registers in the tdescs in the order they were
defined in the isa, since the tdescs are used in common powerpc code (in
rs6000_gdbarch_init), and so are the fixed register numbers (in
ppc-tdep.h), and the order they appear in the ptrace buffer is specific
to Linux. But if this isn't a big deal I can change that to simplify
this code.
Thanks!
--
Pedro Franco de Carvalho
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH 11/17] [PowerPC] Add gdbserver support for TAR
2018-07-13 13:53 [PATCH 00/17] GDB support for more powerpc registers on linux Pedro Franco de Carvalho
` (15 preceding siblings ...)
2018-07-13 14:49 ` [PATCH 17/17] [PowerPC] Add gdbserver support for EBB and PMU registers Pedro Franco de Carvalho
@ 2018-07-13 15:33 ` Pedro Franco de Carvalho
2018-07-13 15:33 ` Ulrich Weigand
16 siblings, 1 reply; 38+ messages in thread
From: Pedro Franco de Carvalho @ 2018-07-13 15:33 UTC (permalink / raw)
To: gdb-patches; +Cc: uweigand, edjunior
This patch extends suport for the Target Address Register to the
powerpc linux gdbserver stub.
gdb/gdbserver/ChangeLog:
YYYY-MM-DD Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* linux-ppc-tdesc-init.h (enum ppc_linux_tdesc)
<PPC_TDESC_ISA207_VSX>: New enum value.
(init_registers_powerpc_isa207_vsx32l): Declare.
(init_registers_powerpc_isa207_vsx64l): Declare.
* linux-ppc-low.c (ppc_fill_tarregset): New function.
(ppc_store_tarregset): New function.
(ppc_regsets): Add entry for the TAR regset.
(ppc_arch_setup): Set isa207 in features struct when needed. Set
size for the TAR regsets.
(ppc_get_ipa_tdesc_idx): Return PPC_TDESC_ISA207_VSX.
(initialize_low_arch): Call init_registers_powerpc_isa207_vsx32l
and init_registers_powerpc_isa207_vsx64l.
* linux-ppc-ipa.c (get_ipa_tdesc): Handle PPC_TDESC_ISA207_VSX.
(initialize_low_tracepoint): Call
init_registers_powerpc_isa207_vsx32l and
init_registers_powerpc_isa207_vsx64l.
---
gdb/gdbserver/linux-ppc-ipa.c | 6 ++++++
gdb/gdbserver/linux-ppc-low.c | 37 +++++++++++++++++++++++++++++++++++-
gdb/gdbserver/linux-ppc-tdesc-init.h | 7 +++++++
3 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/gdb/gdbserver/linux-ppc-ipa.c b/gdb/gdbserver/linux-ppc-ipa.c
index c8b4c3b2da..b543dceba5 100644
--- a/gdb/gdbserver/linux-ppc-ipa.c
+++ b/gdb/gdbserver/linux-ppc-ipa.c
@@ -193,6 +193,8 @@ get_ipa_tdesc (int idx)
return tdesc_powerpc_isa205_vsx64l;
case PPC_TDESC_ISA205_PPR_DSCR_VSX:
return tdesc_powerpc_isa205_ppr_dscr_vsx64l;
+ case PPC_TDESC_ISA207_VSX:
+ return tdesc_powerpc_isa207_vsx64l;
#else
case PPC_TDESC_BASE:
return tdesc_powerpc_32l;
@@ -210,6 +212,8 @@ get_ipa_tdesc (int idx)
return tdesc_powerpc_isa205_vsx32l;
case PPC_TDESC_ISA205_PPR_DSCR_VSX:
return tdesc_powerpc_isa205_ppr_dscr_vsx32l;
+ case PPC_TDESC_ISA207_VSX:
+ return tdesc_powerpc_isa207_vsx32l;
case PPC_TDESC_E500:
return tdesc_powerpc_e500l;
#endif
@@ -239,6 +243,7 @@ initialize_low_tracepoint (void)
init_registers_powerpc_isa205_altivec64l ();
init_registers_powerpc_isa205_vsx64l ();
init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
+ init_registers_powerpc_isa207_vsx64l ();
#else
init_registers_powerpc_32l ();
init_registers_powerpc_altivec32l ();
@@ -248,6 +253,7 @@ initialize_low_tracepoint (void)
init_registers_powerpc_isa205_altivec32l ();
init_registers_powerpc_isa205_vsx32l ();
init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
+ init_registers_powerpc_isa207_vsx32l ();
init_registers_powerpc_e500l ();
#endif
}
diff --git a/gdb/gdbserver/linux-ppc-low.c b/gdb/gdbserver/linux-ppc-low.c
index 502ce674fc..6c27368a36 100644
--- a/gdb/gdbserver/linux-ppc-low.c
+++ b/gdb/gdbserver/linux-ppc-low.c
@@ -510,6 +510,22 @@ ppc_store_dscrregset (struct regcache *regcache, const void *buf)
}
static void
+ppc_fill_tarregset (struct regcache *regcache, void *buf)
+{
+ char *tar = (char *) buf;
+
+ collect_register_by_name (regcache, "tar", tar);
+}
+
+static void
+ppc_store_tarregset (struct regcache *regcache, const void *buf)
+{
+ const char *tar = (const char *) buf;
+
+ supply_register_by_name (regcache, "tar", tar);
+}
+
+static void
ppc_fill_vsxregset (struct regcache *regcache, void *buf)
{
int i, base;
@@ -622,6 +638,8 @@ static struct regset_info ppc_regsets[] = {
fetch them every time, but still fall back to PTRACE_PEEKUSER for the
general registers. Some kernels support these, but not the newer
PPC_PTRACE_GETREGS. */
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TAR, 0, EXTENDED_REGS,
+ ppc_fill_tarregset, ppc_store_tarregset },
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS,
ppc_fill_pprregset, ppc_store_pprregset },
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_DSCR, 0, EXTENDED_REGS,
@@ -696,7 +714,14 @@ ppc_arch_setup (void)
if ((ppc_hwcap2 & PPC_FEATURE2_DSCR)
&& ppc_check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET)
&& ppc_check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET))
- features.ppr_dscr = true;
+ {
+ features.ppr_dscr = true;
+ if ((ppc_hwcap2 & PPC_FEATURE2_ARCH_2_07)
+ && (ppc_hwcap2 & PPC_FEATURE2_TAR)
+ && ppc_check_regset (tid, NT_PPC_TAR,
+ PPC_LINUX_SIZEOF_TARREGSET))
+ features.isa207 = true;
+ }
if (ppc_hwcap & PPC_FEATURE_CELL)
features.cell = true;
@@ -753,6 +778,10 @@ ppc_arch_setup (void)
regset->size = (features.ppr_dscr ?
PPC_LINUX_SIZEOF_DSCRREGSET : 0);
break;
+ case NT_PPC_TAR:
+ regset->size = (features.isa207 ?
+ PPC_LINUX_SIZEOF_TARREGSET : 0);
+ break;
default:
break;
}
@@ -3134,6 +3163,8 @@ ppc_get_ipa_tdesc_idx (void)
return PPC_TDESC_ISA205_VSX;
if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx64l)
return PPC_TDESC_ISA205_PPR_DSCR_VSX;
+ if (tdesc == tdesc_powerpc_isa207_vsx64l)
+ return PPC_TDESC_ISA207_VSX;
#endif
if (tdesc == tdesc_powerpc_32l)
@@ -3152,6 +3183,8 @@ ppc_get_ipa_tdesc_idx (void)
return PPC_TDESC_ISA205_VSX;
if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx32l)
return PPC_TDESC_ISA205_PPR_DSCR_VSX;
+ if (tdesc == tdesc_powerpc_isa207_vsx32l)
+ return PPC_TDESC_ISA207_VSX;
if (tdesc == tdesc_powerpc_e500l)
return PPC_TDESC_E500;
@@ -3211,6 +3244,7 @@ initialize_low_arch (void)
init_registers_powerpc_isa205_altivec32l ();
init_registers_powerpc_isa205_vsx32l ();
init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
+ init_registers_powerpc_isa207_vsx32l ();
init_registers_powerpc_e500l ();
#if __powerpc64__
init_registers_powerpc_64l ();
@@ -3221,6 +3255,7 @@ initialize_low_arch (void)
init_registers_powerpc_isa205_altivec64l ();
init_registers_powerpc_isa205_vsx64l ();
init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
+ init_registers_powerpc_isa207_vsx64l ();
#endif
initialize_regsets_info (&ppc_regsets_info);
diff --git a/gdb/gdbserver/linux-ppc-tdesc-init.h b/gdb/gdbserver/linux-ppc-tdesc-init.h
index c5c10c0670..29b8122886 100644
--- a/gdb/gdbserver/linux-ppc-tdesc-init.h
+++ b/gdb/gdbserver/linux-ppc-tdesc-init.h
@@ -30,6 +30,7 @@ enum ppc_linux_tdesc {
PPC_TDESC_ISA205_ALTIVEC,
PPC_TDESC_ISA205_VSX,
PPC_TDESC_ISA205_PPR_DSCR_VSX,
+ PPC_TDESC_ISA207_VSX,
PPC_TDESC_E500,
};
@@ -59,6 +60,9 @@ void init_registers_powerpc_isa205_vsx32l (void);
/* Defined in auto-generated file powerpc-isa205-ppr-dscr-vsx32l.c. */
void init_registers_powerpc_isa205_ppr_dscr_vsx32l (void);
+/* Defined in auto-generated file powerpc-isa207-vsx32l.c. */
+void init_registers_powerpc_isa207_vsx32l (void);
+
/* Defined in auto-generated file powerpc-e500l.c. */
void init_registers_powerpc_e500l (void);
@@ -90,4 +94,7 @@ void init_registers_powerpc_isa205_vsx64l (void);
/* Defined in auto-generated file powerpc-isa205-ppr-dscr-vsx64l.c. */
void init_registers_powerpc_isa205_ppr_dscr_vsx64l (void);
+/* Defined in auto-generated file powerpc-isa207-vsx64l.c. */
+void init_registers_powerpc_isa207_vsx64l (void);
+
#endif
--
2.13.6
^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH 11/17] [PowerPC] Add gdbserver support for TAR
2018-07-13 15:33 ` [PATCH 11/17] [PowerPC] Add gdbserver support for TAR Pedro Franco de Carvalho
@ 2018-07-13 15:33 ` Ulrich Weigand
0 siblings, 0 replies; 38+ messages in thread
From: Ulrich Weigand @ 2018-07-13 15:33 UTC (permalink / raw)
To: Pedro Franco de Carvalho; +Cc: edjunior, gdb-patches
Pedro Franco de Carvalho wrote:
> gdb/gdbserver/ChangeLog:
> YYYY-MM-DD Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
>
> * linux-ppc-tdesc-init.h (enum ppc_linux_tdesc)
> <PPC_TDESC_ISA207_VSX>: New enum value.
> (init_registers_powerpc_isa207_vsx32l): Declare.
> (init_registers_powerpc_isa207_vsx64l): Declare.
> * linux-ppc-low.c (ppc_fill_tarregset): New function.
> (ppc_store_tarregset): New function.
> (ppc_regsets): Add entry for the TAR regset.
> (ppc_arch_setup): Set isa207 in features struct when needed. Set
> size for the TAR regsets.
> (ppc_get_ipa_tdesc_idx): Return PPC_TDESC_ISA207_VSX.
> (initialize_low_arch): Call init_registers_powerpc_isa207_vsx32l
> and init_registers_powerpc_isa207_vsx64l.
> * linux-ppc-ipa.c (get_ipa_tdesc): Handle PPC_TDESC_ISA207_VSX.
> (initialize_low_tracepoint): Call
> init_registers_powerpc_isa207_vsx32l and
> init_registers_powerpc_isa207_vsx64l.
This is OK.
Thanks,
Ulrich
^ permalink raw reply [flat|nested] 38+ messages in thread