From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 123114 invoked by alias); 1 Oct 2018 22:08:59 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 123014 invoked by uid 89); 1 Oct 2018 22:08:58 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 spammy=privilege, op2 X-HELO: NAM02-CY1-obe.outbound.protection.outlook.com Received: from mail-cys01nam02on0104.outbound.protection.outlook.com (HELO NAM02-CY1-obe.outbound.protection.outlook.com) (104.47.37.104) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 01 Oct 2018 22:08:57 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=impinj.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4ksY2uWt307ZTRLtXfqMdaTwSVaYSoQP1X2QBuIXKIE=; b=LfCx88dWj/puHgFyTzSLCAhmB71RQPFWce0QYoFkt69ie8sKJxMRkkaOYRBQpH8GeRchQF7WeEQIqqLZIvZLKTFvvu/0DHoJN+lQp5iO0InxbPCQ1XBVHEYNi4YIOMD9SmISpj5KA8bDhoJi2nDj0Yk+TzOuJDsD20EY1qaHBU0= Received: from MWHPR0601MB3708.namprd06.prod.outlook.com (10.167.236.38) by MWHPR0601MB3705.namprd06.prod.outlook.com (10.167.236.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.25; Mon, 1 Oct 2018 22:08:53 +0000 Received: from MWHPR0601MB3708.namprd06.prod.outlook.com ([fe80::f4ee:3633:74c0:ab4]) by MWHPR0601MB3708.namprd06.prod.outlook.com ([fe80::f4ee:3633:74c0:ab4%3]) with mapi id 15.20.1185.024; Mon, 1 Oct 2018 22:08:53 +0000 From: Trent Piepho To: "gdb-patches@sourceware.org" CC: Trent Piepho Subject: [PATCH v2 2/2] Check thumb2 load/store and cache hit addressing mode Date: Mon, 01 Oct 2018 22:08:00 -0000 Message-ID: <20181001220826.10429-2-tpiepho@impinj.com> References: <20181001220826.10429-1-tpiepho@impinj.com> In-Reply-To: <20181001220826.10429-1-tpiepho@impinj.com> authentication-results: spf=none (sender IP is ) smtp.mailfrom=tpiepho@impinj.com; received-spf: None (protection.outlook.com: impinj.com does not designate permitted sender hosts) Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-SW-Source: 2018-10/txt/msg00031.txt.bz2 There are a number of different addressing forms available for these thumb2 instructions. However, not all modes are valid for all instructions, nor is every possible bit pattern a valid mode. PLD/PLI are not that complex so verify that one of the valid modes for those instructions was used. Other instructions are checked for a valid mode encoding, but not necessary that the particular mode is valid for the full instruction. gdb/ChangeLog: 2018-10-01 Trent Piepho * arm-tdep.c (thumb2_ld_mem_hint_mode): Decode addressing mode. (thumb2_record_ld_mem_hints): Check addressing mode. --- gdb/arm-tdep.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 52 insertions(+), 2 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 90936ada8e..2d6c17b5d7 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -12661,6 +12661,51 @@ thumb2_record_str_single_data (insn_decode_record = *thumb2_insn_r) return ARM_RECORD_SUCCESS; } =20 + +/* Decode addressing mode of thumb2 load and store single data item, + and memory hints */ + +static int +thumb2_ld_mem_hint_mode (insn_decode_record *thumb2_insn_r) +{ + /* Check Rn =3D 0b1111 */ + if (bits (thumb2_insn_r->arm_insn, 16, 19) =3D=3D 0xf) + { + if (bit (thumb2_insn_r->arm_insn, 20) =3D=3D 1) + return 1; /* PC +/- imm12 */ + else + return -1; /* reserved */ + } + + /* Check U =3D 1 */ + if (bit (thumb2_insn_r->arm_insn, 23) =3D=3D 1) + return 2; /* Rn + imm2 */ + + /* Check op2[5] =3D 0 */ + if (bit (thumb2_insn_r->arm_insn, 11) =3D=3D 0) + { + if (bits (thumb2_insn_r->arm_insn, 6, 10) =3D=3D 0) + return 7; /* Rn + shifted register */ + return -1; /* reserved */ + } + + switch (bits (thumb2_insn_r->arm_insn, 8, 10)) + { + case 0x4: + return 3; /* Rn - imm8 */ + case 0x6: + return 4; /* Rn + imm8, User privilege */ + case 0x1: + case 0x3: + return 5; /* Rn post-indexed by +/- imm8 */ + case 0x5: + case 0x7: + return 6; /* Rn pre-indexed by +/- imm8 */ + default: + return -1; /* reserved */ + } +} + /* Handler for thumb2 load memory hints instructions. */ =20 static int @@ -12668,11 +12713,15 @@ thumb2_record_ld_mem_hints (insn_decode_record *t= humb2_insn_r) { uint32_t record_buf[8]; uint32_t reg_rt, reg_rn; + uint32_t mode; =20 reg_rt =3D bits (thumb2_insn_r->arm_insn, 12, 15); reg_rn =3D bits (thumb2_insn_r->arm_insn, 16, 19); + mode =3D thumb2_ld_mem_hint_mode(thumb2_insn_r); =20 - if (ARM_PC_REGNUM !=3D reg_rt) + /* This does not check every possible addressing mode + data size + * combination for validity */ + if (ARM_PC_REGNUM !=3D reg_rt && mode !=3D -1) { record_buf[0] =3D reg_rt; record_buf[1] =3D reg_rn; @@ -12688,7 +12737,8 @@ thumb2_record_ld_mem_hints (insn_decode_record *thu= mb2_insn_r) if (bits (thumb2_insn_r->arm_insn, 20, 22) =3D=3D 0x1) { /* Handle PLD, PLI affect only caches, so nothing to record */ - return ARM_RECORD_SUCCESS; + if (mode =3D=3D 1 || mode =3D=3D 2 || mode =3D=3D 3 || mode =3D=3D 7) + return ARM_RECORD_SUCCESS; } } =20 --=20 2.14.4