From: Trent Piepho <tpiepho@impinj.com>
To: "gdb-patches@sourceware.org" <gdb-patches@sourceware.org>
Cc: Trent Piepho <tpiepho@impinj.com>
Subject: [PATCH v3 2/2] Check thumb2 load/store and cache hit addressing mode
Date: Mon, 01 Oct 2018 22:26:00 -0000 [thread overview]
Message-ID: <20181001222544.4307-2-tpiepho@impinj.com> (raw)
In-Reply-To: <20181001222544.4307-1-tpiepho@impinj.com>
There are a number of different addressing forms available for these
thumb2 instructions. However, not all modes are valid for all
instructions, nor is every possible bit pattern a valid mode.
PLD/PLI are not that complex so verify that one of the valid modes for
those instructions was used.
Other instructions are checked for a valid mode encoding, but not
necessary that the particular mode is valid for the full instruction.
gdb/ChangeLog:
2018-10-01 Trent Piepho <tpiepho@impinj.com>
* arm-tdep.c (thumb2_ld_mem_hint_mode): Decode addressing mode.
(thumb2_record_ld_mem_hints): Check addressing mode.
---
Changes from v2:
* Fix logic flaw that allowed invalid non PLI/D instructions to be
considered PLI/D instructions.
gdb/arm-tdep.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++++-------
1 file changed, 61 insertions(+), 8 deletions(-)
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 90936ada8e..f7b51d4805 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -12661,6 +12661,51 @@ thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r)
return ARM_RECORD_SUCCESS;
}
+
+/* Decode addressing mode of thumb2 load and store single data item,
+ and memory hints */
+
+static int
+thumb2_ld_mem_hint_mode (insn_decode_record *thumb2_insn_r)
+{
+ /* Check Rn = 0b1111 */
+ if (bits (thumb2_insn_r->arm_insn, 16, 19) == 0xf)
+ {
+ if (bit (thumb2_insn_r->arm_insn, 20) == 1)
+ return 1; /* PC +/- imm12 */
+ else
+ return -1; /* reserved */
+ }
+
+ /* Check U = 1 */
+ if (bit (thumb2_insn_r->arm_insn, 23) == 1)
+ return 2; /* Rn + imm2 */
+
+ /* Check op2[5] = 0 */
+ if (bit (thumb2_insn_r->arm_insn, 11) == 0)
+ {
+ if (bits (thumb2_insn_r->arm_insn, 6, 10) == 0)
+ return 7; /* Rn + shifted register */
+ return -1; /* reserved */
+ }
+
+ switch (bits (thumb2_insn_r->arm_insn, 8, 10))
+ {
+ case 0x4:
+ return 3; /* Rn - imm8 */
+ case 0x6:
+ return 4; /* Rn + imm8, User privilege */
+ case 0x1:
+ case 0x3:
+ return 5; /* Rn post-indexed by +/- imm8 */
+ case 0x5:
+ case 0x7:
+ return 6; /* Rn pre-indexed by +/- imm8 */
+ default:
+ return -1; /* reserved */
+ }
+}
+
/* Handler for thumb2 load memory hints instructions. */
static int
@@ -12668,27 +12713,35 @@ thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r)
{
uint32_t record_buf[8];
uint32_t reg_rt, reg_rn;
+ uint32_t mode;
reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15);
reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
+ mode = thumb2_ld_mem_hint_mode(thumb2_insn_r);
+ /* This does not check every possible addressing mode + data size
+ * combination for validity */
if (ARM_PC_REGNUM != reg_rt)
{
- record_buf[0] = reg_rt;
- record_buf[1] = reg_rn;
- record_buf[2] = ARM_PS_REGNUM;
- thumb2_insn_r->reg_rec_count = 3;
+ if (mode != -1)
+ {
+ record_buf[0] = reg_rt;
+ record_buf[1] = reg_rn;
+ record_buf[2] = ARM_PS_REGNUM;
+ thumb2_insn_r->reg_rec_count = 3;
- REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
- record_buf);
- return ARM_RECORD_SUCCESS;
+ REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+ record_buf);
+ return ARM_RECORD_SUCCESS;
+ }
}
else
{
if (bits (thumb2_insn_r->arm_insn, 20, 22) == 0x1)
{
/* Handle PLD, PLI affect only caches, so nothing to record */
- return ARM_RECORD_SUCCESS;
+ if (mode == 1 || mode == 2 || mode == 3 || mode == 7)
+ return ARM_RECORD_SUCCESS;
}
}
--
2.14.4
next prev parent reply other threads:[~2018-10-01 22:26 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-01 22:26 [PATCH v3 1/2] Record ARM THUMB2 PLD/PLI cache instructions Trent Piepho
2018-10-01 22:26 ` Trent Piepho [this message]
2018-10-02 17:40 ` [PATCH v3 2/2] Check thumb2 load/store and cache hit addressing mode Simon Marchi
2018-10-03 1:01 ` Trent Piepho
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