From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 83348 invoked by alias); 3 Oct 2018 00:05:30 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 83339 invoked by uid 89); 3 Oct 2018 00:05:29 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 spammy=accumulating, non-compacted, noncompacted, compacted X-HELO: smtp.lse.epita.fr Received: from lse.epita.fr (HELO smtp.lse.epita.fr) (163.5.55.17) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 03 Oct 2018 00:05:27 +0000 Received: from trigger (unknown [37.228.243.5]) by smtp.lse.epita.fr (Postfix) with ESMTPSA id EA7CC60E66; Wed, 3 Oct 2018 02:05:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=lse.epita.fr; s=smtp; t=1538525125; bh=gNBdKRCor/Aj8pznU2kZxG84xJa9efT13OIj88TNT5I=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=diKA+WngMsDIJdyUbb0uVtoO+R7jy+AdetPa7BwOmJU5H8shEO2TGeLkdnucQg7G0 I55CPSJ86m527dxgTBK92oMefKTS6A9eyWnOFI5GSq7l3OraRV/1grMgVa1ae6YRaH 6WzphbOI60n0BOGMya68jmnaUr/jHJP131WVrmOg= Date: Wed, 03 Oct 2018 00:05:00 -0000 From: Pierre Marsais To: "Metzger, Markus T" Cc: "gdb-patches@sourceware.org" Subject: Re: [PATCH] Add support for recording xsave x86 instruction Message-ID: <20181003000523.GA16158@trigger> References: <20180921003827.1525-1-pierre.marsais@lse.epita.fr> <20181001002516.GA31390@trigger> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-SW-Source: 2018-10/txt/msg00059.txt.bz2 Hi, Thanks for the quick reply. On Mon, Oct 01, 2018 at 06:58:32AM +0000, Metzger, Markus T wrote: > > > Also I think that we would need to check the inferior architecture to > > > handle 32-bit compatibility mode. > > > > I'm not sure to follow you. In which cases 32-bit behaves differently than 64-bit ? > > Fewer registers. XSAVE is not writing the upper registers area. > > >> + if (record_full_arch_list_add_mem (tmpu64 + offset, size)) > > >> + return -1; > > > > > > Looks like this assumes the standard (non-compacted) XSAVE format. > > > > > > For the compacted format, the offset must be computed by accumulating > > > the sizes of preceding components. > > > > If I'm not mistaken, the compact format is only used by XSAVEC instruction, which > > doesn't have the same opcode. The XSAVE instruction seems unrelated to this > > format. > > You're right. It doesn't write the full header ,though. And there's a special case > with XCR0[1]. Once again, thank you for finding this. I think I've addressed all your concerns in the v3 of the patch. Regards, -- Pierre "Pimzero" MARSAIS, EPITA 2018; GISTRE | ACU | LSE