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From: Jim Wilson <jimw@sifive.com>
To: gdb-patches@sourceware.org
Cc: Andrew Burgess <andrew.burgess@embecosm.com>,
	Jim Wilson <jimw@sifive.com>
Subject: [PATCH 1/2] RISC-V: Print FP regs as union of float types.
Date: Fri, 19 Oct 2018 21:49:00 -0000	[thread overview]
Message-ID: <20181019214907.8939-1-jimw@sifive.com> (raw)
In-Reply-To: <CAFyWVabswzH+cwN6aBgPbP-ccUjUC2iya+HUyLjYzxLgUaM_Zg@mail.gmail.com>

A 64-bit FP register can hold either a single or double float value, so
print it as both types by using a union type for FP registers.  Likewise
for 128-bit regs which can also hold long double.

	gdb/
	* riscv-tdep.c (riscv_fpreg_d_type, riscv_fpreg_q_type): New.
	(riscv_register_type): Use them.
	(riscv_print_one_register_info): Handle union of floats same as float.
	* riscv-tdep.h (struct gdbarch_tdep): Add riscv_fpreg_d_type and
	riscv_fpreg_q_type fields.
---
 gdb/riscv-tdep.c | 85 ++++++++++++++++++++++++++++++++++++++++++++++--
 gdb/riscv-tdep.h |  4 +++
 2 files changed, 86 insertions(+), 3 deletions(-)

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 3402241b97..a4d732f6f9 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -495,6 +495,76 @@ riscv_register_name (struct gdbarch *gdbarch, int regnum)
   return NULL;
 }
 
+/* Construct a type for 64-bit FP registers.  */
+
+static struct type *
+riscv_fpreg_d_type (struct gdbarch *gdbarch)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+  if (!tdep->riscv_fpreg_d_type)
+    {
+      const struct builtin_type *bt = builtin_type (gdbarch);
+
+      /* The type we're building is this: */
+#if 0
+      union __gdb_builtin_type_fpreg_d
+      {
+	float f;
+	double d;
+      };
+#endif
+
+      struct type *t;
+
+      t = arch_composite_type (gdbarch,
+			       "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION);
+      append_composite_type_field (t, "float", bt->builtin_float);
+      append_composite_type_field (t, "double", bt->builtin_double);
+      TYPE_VECTOR (t) = 1;
+      TYPE_NAME (t) = "builtin_type_fpreg_d";
+      tdep->riscv_fpreg_d_type = t;
+    }
+
+  return tdep->riscv_fpreg_d_type;
+}
+
+/* Construct a type for 128-bit FP registers.  */
+
+static struct type *
+riscv_fpreg_q_type (struct gdbarch *gdbarch)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+  if (!tdep->riscv_fpreg_q_type)
+    {
+      const struct builtin_type *bt = builtin_type (gdbarch);
+
+      /* The type we're building is this: */
+#if 0
+      union __gdb_builtin_type_fpreg_d
+      {
+	float f;
+	double d;
+	long double ld;
+      };
+#endif
+
+      struct type *t;
+
+      t = arch_composite_type (gdbarch,
+			       "__gdb_builtin_type_fpreg_q", TYPE_CODE_UNION);
+      append_composite_type_field (t, "float", bt->builtin_float);
+      append_composite_type_field (t, "double", bt->builtin_double);
+      append_composite_type_field (t, "long double", bt->builtin_long_double);
+      TYPE_VECTOR (t) = 1;
+      TYPE_NAME (t) = "builtin_type_fpreg_q";
+      tdep->riscv_fpreg_q_type = t;
+    }
+
+  return tdep->riscv_fpreg_q_type;
+}
+
 /* Implement the register_type gdbarch method.  */
 
 static struct type *
@@ -537,9 +607,9 @@ riscv_register_type (struct gdbarch *gdbarch, int regnum)
 	case 4:
 	  return builtin_type (gdbarch)->builtin_float;
 	case 8:
-	  return builtin_type (gdbarch)->builtin_double;
+	  return riscv_fpreg_d_type (gdbarch);
 	case 16:
-	  return builtin_type (gdbarch)->builtin_long_double;
+	  return riscv_fpreg_q_type (gdbarch);
 	default:
 	  internal_error (__FILE__, __LINE__,
 			  _("unknown isa regsize %i"), regsize);
@@ -591,7 +661,16 @@ riscv_print_one_register_info (struct gdbarch *gdbarch,
   print_raw_format = (value_entirely_available (val)
 		      && !value_optimized_out (val));
 
-  if (TYPE_CODE (regtype) == TYPE_CODE_FLT)
+  if (TYPE_CODE (regtype) == TYPE_CODE_FLT
+      || (TYPE_CODE (regtype) == TYPE_CODE_UNION
+	  && TYPE_NFIELDS (regtype) == 2
+	  && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
+	  && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT)
+      || (TYPE_CODE (regtype) == TYPE_CODE_UNION
+	  && TYPE_NFIELDS (regtype) == 3
+	  && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
+	  && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT
+	  && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 2)) == TYPE_CODE_FLT))
     {
       struct value_print_options opts;
       const gdb_byte *valaddr = value_contents_for_printing (val);
diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index 8a2454eb66..e04e728f32 100644
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -78,6 +78,10 @@ struct gdbarch_tdep
      features that are supported on the target.  These could be cached from
      the target, or read from the executable when available.  */
   unsigned core_features;
+
+  /* ISA-specific data types.  */
+  struct type *riscv_fpreg_d_type;
+  struct type *riscv_fpreg_q_type;
 };
 
 /* Return the width in bytes of the general purpose registers for GDBARCH.  */
-- 
2.17.1

  reply	other threads:[~2018-10-19 21:49 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-19 21:46 [PATCH 0/2] RISC-V: Improve FP register support Jim Wilson
2018-10-19 21:49 ` Jim Wilson [this message]
2018-10-20 21:38   ` [PATCH 1/2] RISC-V: Print FP regs as union of float types Kevin Buettner
2018-10-22 21:22     ` Jim Wilson
2018-10-19 21:50 ` [PATCH 2/2] RISC-V: NaN-box FP values smaller than an FP register Jim Wilson
2018-10-20 21:39   ` Kevin Buettner
2018-10-22 21:21     ` Jim Wilson
2018-10-23 11:18 ` [PATCH 0/2] RISC-V: Improve FP register support Pedro Alves
2018-10-25 23:49   ` Jim Wilson

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