From: Kevin Buettner <kevinb@redhat.com>
To: gdb-patches@sourceware.org
Cc: Jim Wilson <jimw@sifive.com>
Subject: Re: [PATCH 1/2] RISC-V: Print FP regs as union of float types.
Date: Sat, 20 Oct 2018 21:38:00 -0000 [thread overview]
Message-ID: <20181020143808.3f66c381@pinnacle.lan> (raw)
In-Reply-To: <20181019214907.8939-1-jimw@sifive.com>
On Fri, 19 Oct 2018 14:49:07 -0700
Jim Wilson <jimw@sifive.com> wrote:
> A 64-bit FP register can hold either a single or double float value, so
> print it as both types by using a union type for FP registers. Likewise
> for 128-bit regs which can also hold long double.
>
> gdb/
> * riscv-tdep.c (riscv_fpreg_d_type, riscv_fpreg_q_type): New.
> (riscv_register_type): Use them.
> (riscv_print_one_register_info): Handle union of floats same as float.
> * riscv-tdep.h (struct gdbarch_tdep): Add riscv_fpreg_d_type and
> riscv_fpreg_q_type fields.
This is okay, except for the following nits...
> +static struct type *
> +riscv_fpreg_d_type (struct gdbarch *gdbarch)
> +{
> + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
> +
> + if (!tdep->riscv_fpreg_d_type)
The GDB coding standard say that this must be coded as:
if (tdep->riscv_fpreg_d_type == NULL)
Though I think we prefer nullptr over NULL these days.
(I realize that there's code in GDB which does not conform to this
standard.)
Likewise, here:
> +static struct type *
> +riscv_fpreg_q_type (struct gdbarch *gdbarch)
> +{
> + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
> +
> + if (!tdep->riscv_fpreg_q_type)
Kevin
next prev parent reply other threads:[~2018-10-20 21:38 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-19 21:46 [PATCH 0/2] RISC-V: Improve FP register support Jim Wilson
2018-10-19 21:49 ` [PATCH 1/2] RISC-V: Print FP regs as union of float types Jim Wilson
2018-10-20 21:38 ` Kevin Buettner [this message]
2018-10-22 21:22 ` Jim Wilson
2018-10-19 21:50 ` [PATCH 2/2] RISC-V: NaN-box FP values smaller than an FP register Jim Wilson
2018-10-20 21:39 ` Kevin Buettner
2018-10-22 21:21 ` Jim Wilson
2018-10-23 11:18 ` [PATCH 0/2] RISC-V: Improve FP register support Pedro Alves
2018-10-25 23:49 ` Jim Wilson
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