From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 100803 invoked by alias); 26 Feb 2019 11:55:23 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 100695 invoked by uid 89); 26 Feb 2019 11:55:21 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=frm X-HELO: rock.gnat.com Received: from rock.gnat.com (HELO rock.gnat.com) (205.232.38.15) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 26 Feb 2019 11:55:19 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by filtered-rock.gnat.com (Postfix) with ESMTP id DC6E856070; Tue, 26 Feb 2019 06:55:17 -0500 (EST) Received: from rock.gnat.com ([127.0.0.1]) by localhost (rock.gnat.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id vFRTBx4RhEgT; Tue, 26 Feb 2019 06:55:17 -0500 (EST) Received: from joel.gnat.com (localhost.localdomain [127.0.0.1]) by rock.gnat.com (Postfix) with ESMTP id 28A995606F; Tue, 26 Feb 2019 06:55:17 -0500 (EST) Received: by joel.gnat.com (Postfix, from userid 1000) id B4EA7849D1; Tue, 26 Feb 2019 15:55:10 +0400 (+04) Date: Tue, 26 Feb 2019 11:55:00 -0000 From: Joel Brobecker To: Andrew Burgess Cc: Tom Tromey , gdb-patches@sourceware.org, jimw@sifive.com, palmer@sifive.com, jhb@FreeBSD.org Subject: Re: [PATCH] gdb/riscv: Add target description support Message-ID: <20190226115510.GA22983@adacore.com> References: <20181108160745.24600-1-andrew.burgess@embecosm.com> <20181114145756.GM16539@embecosm.com> <87r2bz67ol.fsf@tromey.com> <20190223203958.GA15942@embecosm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190223203958.GA15942@embecosm.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-SW-Source: 2019-02/txt/msg00427.txt.bz2 Hi Andrew, > [PATCH] gdb/riscv: Use legacy register numbers in default target description > > When the target description support was added to RISC-V, the register > numbers assigned to the fflags, frm, and fcsr control registers in the > default target descriptions didn't match the register numbers used by > GDB before the target description support was added. > > What this means is that if a tools exists in the wild that is using > hard-coded register number, setup to match GDB's old behaviour, then > this will have been broken (for fflags, frm, and fcsr) by the move to > target descriptions. QEMU is such a tool. > > There are a couple of solutions that could be used to work around this > issue: > > - The user can create their own xml description file with the > register numbers setup to match their old tool, then load this by > telling GDB 'set tdesc filename FILENAME'. > > - Update their old tool to use the newer default numbering scheme, or > better yet add proper target description support to their tool. > > - We could have RISC-V GDB change to maintain the old defaults. > > This patch implements the last of these ideas, changing the default > numbering to match the old behaviour. > > This change is only visible to targets that don't supply their own xml > description file and instead rely on GDB's default numbering. > > gdb/ChangeLog: > > * features/riscv/32bit-cpu.xml: Add register numbers. > * features/riscv/32bit-fpu.c: Regenerate. > * features/riscv/32bit-fpu.xml: Add register numbers. > * features/riscv/64bit-cpu.xml: Add register numbers. > * features/riscv/64bit-fpu.c: Regenerate. > * features/riscv/64bit-fpu.xml: Add register numbers. I've had a chance to look at the patch, and fwiw, it looks good to me. If others agree that it is OK, I think it would be nice if we pushed the patch before I create the gdb-8.3-branch, and then create the first pre-release (8.2.90). -- Joel