* [PATCH] AArch64: Add half float view to V registers
@ 2019-04-12 10:45 Alan Hayward
2019-05-13 14:57 ` [PING] " Alan Hayward
2019-05-14 8:15 ` Andrew Burgess
0 siblings, 2 replies; 4+ messages in thread
From: Alan Hayward @ 2019-04-12 10:45 UTC (permalink / raw)
To: gdb-patches; +Cc: nd, Alan Hayward
AArch64 can fill the vector registers with half precision floats.
Add a view for this.
Add builtin type ieee half and connect this to the existing
floatformats_ieee_half.
gdb/ChangeLog:
2019-04-12 Alan Hayward <alan.hayward@arm.com>
* aarch64-tdep.c (aarch64_vnh_type): Add half view.
(aarch64_vnv_type): Likewise.
* target-descriptions.c (make_gdb_type): Add TDESC_TYPE_IEEE_HALF.
* common/tdesc.c: Likewise.
* common/tdesc.h (enum tdesc_type_kind): Likewise.
* features/aarch64-fpu.c (create_feature_aarch64_fpu): Regenerate.
* features/aarch64-fpu.xml: Add ieee half view.
* features/aarch64-sve.c (create_feature_aarch64_fpu): Likewise.
* gdbtypes.c (gdbtypes_post_init): Add builtin_half
* gdbtypes.h (struct builtin_type): Likewise.
(struct objfile_type): Likewise.
---
gdb/aarch64-tdep.c | 5 +++++
gdb/common/tdesc.c | 1 +
gdb/common/tdesc.h | 1 +
gdb/features/aarch64-fpu.c | 5 +++++
gdb/features/aarch64-fpu.xml | 2 ++
gdb/features/aarch64-sve.c | 5 +++++
gdb/gdbtypes.c | 3 +++
gdb/gdbtypes.h | 2 ++
gdb/target-descriptions.c | 5 +++++
9 files changed, 29 insertions(+)
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 1b3977bfaf..8a5e7b9570 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -1928,6 +1928,9 @@ aarch64_vnh_type (struct gdbarch *gdbarch)
t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
TYPE_CODE_UNION);
+ elem = builtin_type (gdbarch)->builtin_half;
+ append_composite_type_field (t, "f", elem);
+
elem = builtin_type (gdbarch)->builtin_uint16;
append_composite_type_field (t, "u", elem);
@@ -2006,6 +2009,8 @@ aarch64_vnv_type (struct gdbarch *gdbarch)
sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
TYPE_CODE_UNION);
+ append_composite_type_field (sub, "f",
+ init_vector_type (bt->builtin_half, 8));
append_composite_type_field (sub, "u",
init_vector_type (bt->builtin_uint16, 8));
append_composite_type_field (sub, "s",
diff --git a/gdb/common/tdesc.c b/gdb/common/tdesc.c
index fe63a36c33..f946a53c7f 100644
--- a/gdb/common/tdesc.c
+++ b/gdb/common/tdesc.c
@@ -50,6 +50,7 @@ static tdesc_type_builtin tdesc_predefined_types[] =
{ "uint128", TDESC_TYPE_UINT128 },
{ "code_ptr", TDESC_TYPE_CODE_PTR },
{ "data_ptr", TDESC_TYPE_DATA_PTR },
+ { "ieee_half", TDESC_TYPE_IEEE_HALF },
{ "ieee_single", TDESC_TYPE_IEEE_SINGLE },
{ "ieee_double", TDESC_TYPE_IEEE_DOUBLE },
{ "arm_fpa_ext", TDESC_TYPE_ARM_FPA_EXT },
diff --git a/gdb/common/tdesc.h b/gdb/common/tdesc.h
index a0bc6339e2..9eb3d5ea31 100644
--- a/gdb/common/tdesc.h
+++ b/gdb/common/tdesc.h
@@ -147,6 +147,7 @@ enum tdesc_type_kind
TDESC_TYPE_UINT128,
TDESC_TYPE_CODE_PTR,
TDESC_TYPE_DATA_PTR,
+ TDESC_TYPE_IEEE_HALF,
TDESC_TYPE_IEEE_SINGLE,
TDESC_TYPE_IEEE_DOUBLE,
TDESC_TYPE_ARM_FPA_EXT,
diff --git a/gdb/features/aarch64-fpu.c b/gdb/features/aarch64-fpu.c
index 47962d1f24..b73d12ebe4 100644
--- a/gdb/features/aarch64-fpu.c
+++ b/gdb/features/aarch64-fpu.c
@@ -28,6 +28,9 @@ create_feature_aarch64_fpu (struct target_desc *result, long regnum)
element_type = tdesc_named_type (feature, "int32");
tdesc_create_vector (feature, "v4i", element_type, 4);
+ element_type = tdesc_named_type (feature, "ieee_half");
+ tdesc_create_vector (feature, "v8f", element_type, 8);
+
element_type = tdesc_named_type (feature, "uint16");
tdesc_create_vector (feature, "v8u", element_type, 8);
@@ -65,6 +68,8 @@ create_feature_aarch64_fpu (struct target_desc *result, long regnum)
tdesc_add_field (type_with_fields, "s", field_type);
type_with_fields = tdesc_create_union (feature, "vnh");
+ field_type = tdesc_named_type (feature, "v8f");
+ tdesc_add_field (type_with_fields, "f", field_type);
field_type = tdesc_named_type (feature, "v8u");
tdesc_add_field (type_with_fields, "u", field_type);
field_type = tdesc_named_type (feature, "v8i");
diff --git a/gdb/features/aarch64-fpu.xml b/gdb/features/aarch64-fpu.xml
index 141c996ead..1eba8faea7 100644
--- a/gdb/features/aarch64-fpu.xml
+++ b/gdb/features/aarch64-fpu.xml
@@ -14,6 +14,7 @@
<vector id="v4f" type="ieee_single" count="4"/>
<vector id="v4u" type="uint32" count="4"/>
<vector id="v4i" type="int32" count="4"/>
+ <vector id="v8f" type="ieee_half" count="8"/>
<vector id="v8u" type="uint16" count="8"/>
<vector id="v8i" type="int16" count="8"/>
<vector id="v16u" type="uint8" count="16"/>
@@ -31,6 +32,7 @@
<field name="s" type="v4i"/>
</union>
<union id="vnh">
+ <field name="f" type="v8f"/>
<field name="u" type="v8u"/>
<field name="s" type="v8i"/>
</union>
diff --git a/gdb/features/aarch64-sve.c b/gdb/features/aarch64-sve.c
index 2166b4bb07..ae292d2f3d 100644
--- a/gdb/features/aarch64-sve.c
+++ b/gdb/features/aarch64-sve.c
@@ -55,6 +55,9 @@ create_feature_aarch64_sve (struct target_desc *result, long regnum,
element_type = tdesc_named_type (feature, "int32");
tdesc_create_vector (feature, "svevss", element_type, 4 * scale);
+ element_type = tdesc_named_type (feature, "ieee_half");
+ tdesc_create_vector (feature, "svevhf", element_type, 8 * scale);
+
element_type = tdesc_named_type (feature, "uint16");
tdesc_create_vector (feature, "svevhu", element_type, 8 * scale);
@@ -90,6 +93,8 @@ create_feature_aarch64_sve (struct target_desc *result, long regnum,
tdesc_add_field (type_with_fields, "s", field_type);
type_with_fields = tdesc_create_union (feature, "svevnh");
+ field_type = tdesc_named_type (feature, "svevhf");
+ tdesc_add_field (type_with_fields, "f", field_type);
field_type = tdesc_named_type (feature, "svevhu");
tdesc_add_field (type_with_fields, "u", field_type);
field_type = tdesc_named_type (feature, "svevhs");
diff --git a/gdb/gdbtypes.c b/gdb/gdbtypes.c
index 683238d03d..58d1573b1a 100644
--- a/gdb/gdbtypes.c
+++ b/gdb/gdbtypes.c
@@ -5358,6 +5358,9 @@ gdbtypes_post_init (struct gdbarch *gdbarch)
builtin_type->builtin_unsigned_long_long
= arch_integer_type (gdbarch, gdbarch_long_long_bit (gdbarch),
1, "unsigned long long");
+ builtin_type->builtin_half
+ = arch_float_type (gdbarch, gdbarch_half_bit (gdbarch),
+ "half", gdbarch_half_format (gdbarch));
builtin_type->builtin_float
= arch_float_type (gdbarch, gdbarch_float_bit (gdbarch),
"float", gdbarch_float_format (gdbarch));
diff --git a/gdb/gdbtypes.h b/gdb/gdbtypes.h
index 2125ed991d..e6f41e2265 100644
--- a/gdb/gdbtypes.h
+++ b/gdb/gdbtypes.h
@@ -1581,6 +1581,7 @@ struct builtin_type
struct type *builtin_unsigned_short;
struct type *builtin_unsigned_int;
struct type *builtin_unsigned_long;
+ struct type *builtin_half;
struct type *builtin_float;
struct type *builtin_double;
struct type *builtin_long_double;
@@ -1676,6 +1677,7 @@ struct objfile_type
struct type *builtin_unsigned_int;
struct type *builtin_unsigned_long;
struct type *builtin_unsigned_long_long;
+ struct type *builtin_half;
struct type *builtin_float;
struct type *builtin_double;
struct type *builtin_long_double;
diff --git a/gdb/target-descriptions.c b/gdb/target-descriptions.c
index 96d453527c..bd33091ba9 100644
--- a/gdb/target-descriptions.c
+++ b/gdb/target-descriptions.c
@@ -119,6 +119,11 @@ make_gdb_type (struct gdbarch *gdbarch, struct tdesc_type *ttype)
switch (e->kind)
{
+ case TDESC_TYPE_IEEE_HALF:
+ m_type = arch_float_type (m_gdbarch, -1, "builtin_type_ieee_half",
+ floatformats_ieee_half);
+ return;
+
case TDESC_TYPE_IEEE_SINGLE:
m_type = arch_float_type (m_gdbarch, -1, "builtin_type_ieee_single",
floatformats_ieee_single);
--
2.20.1 (Apple Git-117)
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PING] Re: [PATCH] AArch64: Add half float view to V registers
2019-04-12 10:45 [PATCH] AArch64: Add half float view to V registers Alan Hayward
@ 2019-05-13 14:57 ` Alan Hayward
2019-05-14 8:15 ` Andrew Burgess
1 sibling, 0 replies; 4+ messages in thread
From: Alan Hayward @ 2019-05-13 14:57 UTC (permalink / raw)
To: gdb-patches; +Cc: nd
Ping for this.
Common changes should hopefully be obvious enough.
Alan.
> On 12 Apr 2019, at 11:45, Alan Hayward <Alan.Hayward@arm.com> wrote:
>
> AArch64 can fill the vector registers with half precision floats.
> Add a view for this.
>
> Add builtin type ieee half and connect this to the existing
> floatformats_ieee_half.
>
> gdb/ChangeLog:
>
> 2019-04-12 Alan Hayward <alan.hayward@arm.com>
>
> * aarch64-tdep.c (aarch64_vnh_type): Add half view.
> (aarch64_vnv_type): Likewise.
> * target-descriptions.c (make_gdb_type): Add TDESC_TYPE_IEEE_HALF.
> * common/tdesc.c: Likewise.
> * common/tdesc.h (enum tdesc_type_kind): Likewise.
> * features/aarch64-fpu.c (create_feature_aarch64_fpu): Regenerate.
> * features/aarch64-fpu.xml: Add ieee half view.
> * features/aarch64-sve.c (create_feature_aarch64_fpu): Likewise.
> * gdbtypes.c (gdbtypes_post_init): Add builtin_half
> * gdbtypes.h (struct builtin_type): Likewise.
> (struct objfile_type): Likewise.
> ---
> gdb/aarch64-tdep.c | 5 +++++
> gdb/common/tdesc.c | 1 +
> gdb/common/tdesc.h | 1 +
> gdb/features/aarch64-fpu.c | 5 +++++
> gdb/features/aarch64-fpu.xml | 2 ++
> gdb/features/aarch64-sve.c | 5 +++++
> gdb/gdbtypes.c | 3 +++
> gdb/gdbtypes.h | 2 ++
> gdb/target-descriptions.c | 5 +++++
> 9 files changed, 29 insertions(+)
>
> diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
> index 1b3977bfaf..8a5e7b9570 100644
> --- a/gdb/aarch64-tdep.c
> +++ b/gdb/aarch64-tdep.c
> @@ -1928,6 +1928,9 @@ aarch64_vnh_type (struct gdbarch *gdbarch)
> t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
> TYPE_CODE_UNION);
>
> + elem = builtin_type (gdbarch)->builtin_half;
> + append_composite_type_field (t, "f", elem);
> +
> elem = builtin_type (gdbarch)->builtin_uint16;
> append_composite_type_field (t, "u", elem);
>
> @@ -2006,6 +2009,8 @@ aarch64_vnv_type (struct gdbarch *gdbarch)
>
> sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
> TYPE_CODE_UNION);
> + append_composite_type_field (sub, "f",
> + init_vector_type (bt->builtin_half, 8));
> append_composite_type_field (sub, "u",
> init_vector_type (bt->builtin_uint16, 8));
> append_composite_type_field (sub, "s",
> diff --git a/gdb/common/tdesc.c b/gdb/common/tdesc.c
> index fe63a36c33..f946a53c7f 100644
> --- a/gdb/common/tdesc.c
> +++ b/gdb/common/tdesc.c
> @@ -50,6 +50,7 @@ static tdesc_type_builtin tdesc_predefined_types[] =
> { "uint128", TDESC_TYPE_UINT128 },
> { "code_ptr", TDESC_TYPE_CODE_PTR },
> { "data_ptr", TDESC_TYPE_DATA_PTR },
> + { "ieee_half", TDESC_TYPE_IEEE_HALF },
> { "ieee_single", TDESC_TYPE_IEEE_SINGLE },
> { "ieee_double", TDESC_TYPE_IEEE_DOUBLE },
> { "arm_fpa_ext", TDESC_TYPE_ARM_FPA_EXT },
> diff --git a/gdb/common/tdesc.h b/gdb/common/tdesc.h
> index a0bc6339e2..9eb3d5ea31 100644
> --- a/gdb/common/tdesc.h
> +++ b/gdb/common/tdesc.h
> @@ -147,6 +147,7 @@ enum tdesc_type_kind
> TDESC_TYPE_UINT128,
> TDESC_TYPE_CODE_PTR,
> TDESC_TYPE_DATA_PTR,
> + TDESC_TYPE_IEEE_HALF,
> TDESC_TYPE_IEEE_SINGLE,
> TDESC_TYPE_IEEE_DOUBLE,
> TDESC_TYPE_ARM_FPA_EXT,
> diff --git a/gdb/features/aarch64-fpu.c b/gdb/features/aarch64-fpu.c
> index 47962d1f24..b73d12ebe4 100644
> --- a/gdb/features/aarch64-fpu.c
> +++ b/gdb/features/aarch64-fpu.c
> @@ -28,6 +28,9 @@ create_feature_aarch64_fpu (struct target_desc *result, long regnum)
> element_type = tdesc_named_type (feature, "int32");
> tdesc_create_vector (feature, "v4i", element_type, 4);
>
> + element_type = tdesc_named_type (feature, "ieee_half");
> + tdesc_create_vector (feature, "v8f", element_type, 8);
> +
> element_type = tdesc_named_type (feature, "uint16");
> tdesc_create_vector (feature, "v8u", element_type, 8);
>
> @@ -65,6 +68,8 @@ create_feature_aarch64_fpu (struct target_desc *result, long regnum)
> tdesc_add_field (type_with_fields, "s", field_type);
>
> type_with_fields = tdesc_create_union (feature, "vnh");
> + field_type = tdesc_named_type (feature, "v8f");
> + tdesc_add_field (type_with_fields, "f", field_type);
> field_type = tdesc_named_type (feature, "v8u");
> tdesc_add_field (type_with_fields, "u", field_type);
> field_type = tdesc_named_type (feature, "v8i");
> diff --git a/gdb/features/aarch64-fpu.xml b/gdb/features/aarch64-fpu.xml
> index 141c996ead..1eba8faea7 100644
> --- a/gdb/features/aarch64-fpu.xml
> +++ b/gdb/features/aarch64-fpu.xml
> @@ -14,6 +14,7 @@
> <vector id="v4f" type="ieee_single" count="4"/>
> <vector id="v4u" type="uint32" count="4"/>
> <vector id="v4i" type="int32" count="4"/>
> + <vector id="v8f" type="ieee_half" count="8"/>
> <vector id="v8u" type="uint16" count="8"/>
> <vector id="v8i" type="int16" count="8"/>
> <vector id="v16u" type="uint8" count="16"/>
> @@ -31,6 +32,7 @@
> <field name="s" type="v4i"/>
> </union>
> <union id="vnh">
> + <field name="f" type="v8f"/>
> <field name="u" type="v8u"/>
> <field name="s" type="v8i"/>
> </union>
> diff --git a/gdb/features/aarch64-sve.c b/gdb/features/aarch64-sve.c
> index 2166b4bb07..ae292d2f3d 100644
> --- a/gdb/features/aarch64-sve.c
> +++ b/gdb/features/aarch64-sve.c
> @@ -55,6 +55,9 @@ create_feature_aarch64_sve (struct target_desc *result, long regnum,
> element_type = tdesc_named_type (feature, "int32");
> tdesc_create_vector (feature, "svevss", element_type, 4 * scale);
>
> + element_type = tdesc_named_type (feature, "ieee_half");
> + tdesc_create_vector (feature, "svevhf", element_type, 8 * scale);
> +
> element_type = tdesc_named_type (feature, "uint16");
> tdesc_create_vector (feature, "svevhu", element_type, 8 * scale);
>
> @@ -90,6 +93,8 @@ create_feature_aarch64_sve (struct target_desc *result, long regnum,
> tdesc_add_field (type_with_fields, "s", field_type);
>
> type_with_fields = tdesc_create_union (feature, "svevnh");
> + field_type = tdesc_named_type (feature, "svevhf");
> + tdesc_add_field (type_with_fields, "f", field_type);
> field_type = tdesc_named_type (feature, "svevhu");
> tdesc_add_field (type_with_fields, "u", field_type);
> field_type = tdesc_named_type (feature, "svevhs");
> diff --git a/gdb/gdbtypes.c b/gdb/gdbtypes.c
> index 683238d03d..58d1573b1a 100644
> --- a/gdb/gdbtypes.c
> +++ b/gdb/gdbtypes.c
> @@ -5358,6 +5358,9 @@ gdbtypes_post_init (struct gdbarch *gdbarch)
> builtin_type->builtin_unsigned_long_long
> = arch_integer_type (gdbarch, gdbarch_long_long_bit (gdbarch),
> 1, "unsigned long long");
> + builtin_type->builtin_half
> + = arch_float_type (gdbarch, gdbarch_half_bit (gdbarch),
> + "half", gdbarch_half_format (gdbarch));
> builtin_type->builtin_float
> = arch_float_type (gdbarch, gdbarch_float_bit (gdbarch),
> "float", gdbarch_float_format (gdbarch));
> diff --git a/gdb/gdbtypes.h b/gdb/gdbtypes.h
> index 2125ed991d..e6f41e2265 100644
> --- a/gdb/gdbtypes.h
> +++ b/gdb/gdbtypes.h
> @@ -1581,6 +1581,7 @@ struct builtin_type
> struct type *builtin_unsigned_short;
> struct type *builtin_unsigned_int;
> struct type *builtin_unsigned_long;
> + struct type *builtin_half;
> struct type *builtin_float;
> struct type *builtin_double;
> struct type *builtin_long_double;
> @@ -1676,6 +1677,7 @@ struct objfile_type
> struct type *builtin_unsigned_int;
> struct type *builtin_unsigned_long;
> struct type *builtin_unsigned_long_long;
> + struct type *builtin_half;
> struct type *builtin_float;
> struct type *builtin_double;
> struct type *builtin_long_double;
> diff --git a/gdb/target-descriptions.c b/gdb/target-descriptions.c
> index 96d453527c..bd33091ba9 100644
> --- a/gdb/target-descriptions.c
> +++ b/gdb/target-descriptions.c
> @@ -119,6 +119,11 @@ make_gdb_type (struct gdbarch *gdbarch, struct tdesc_type *ttype)
>
> switch (e->kind)
> {
> + case TDESC_TYPE_IEEE_HALF:
> + m_type = arch_float_type (m_gdbarch, -1, "builtin_type_ieee_half",
> + floatformats_ieee_half);
> + return;
> +
> case TDESC_TYPE_IEEE_SINGLE:
> m_type = arch_float_type (m_gdbarch, -1, "builtin_type_ieee_single",
> floatformats_ieee_single);
> --
> 2.20.1 (Apple Git-117)
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] AArch64: Add half float view to V registers
2019-04-12 10:45 [PATCH] AArch64: Add half float view to V registers Alan Hayward
2019-05-13 14:57 ` [PING] " Alan Hayward
@ 2019-05-14 8:15 ` Andrew Burgess
2019-05-14 9:38 ` Alan Hayward
1 sibling, 1 reply; 4+ messages in thread
From: Andrew Burgess @ 2019-05-14 8:15 UTC (permalink / raw)
To: Alan Hayward; +Cc: gdb-patches, nd
* Alan Hayward <Alan.Hayward@arm.com> [2019-04-12 10:45:07 +0000]:
> AArch64 can fill the vector registers with half precision floats.
> Add a view for this.
>
> Add builtin type ieee half and connect this to the existing
> floatformats_ieee_half.
>
> gdb/ChangeLog:
>
> 2019-04-12 Alan Hayward <alan.hayward@arm.com>
>
> * aarch64-tdep.c (aarch64_vnh_type): Add half view.
> (aarch64_vnv_type): Likewise.
> * target-descriptions.c (make_gdb_type): Add TDESC_TYPE_IEEE_HALF.
> * common/tdesc.c: Likewise.
> * common/tdesc.h (enum tdesc_type_kind): Likewise.
> * features/aarch64-fpu.c (create_feature_aarch64_fpu): Regenerate.
> * features/aarch64-fpu.xml: Add ieee half view.
> * features/aarch64-sve.c (create_feature_aarch64_fpu): Likewise.
> * gdbtypes.c (gdbtypes_post_init): Add builtin_half
> * gdbtypes.h (struct builtin_type): Likewise.
> (struct objfile_type): Likewise.
This patch looks fine to apply. I was a little surprised that this
didn't require any test updates, but I guess if there's already not
tests for this stuff then that's fine.
Thanks,
Andrew
> ---
> gdb/aarch64-tdep.c | 5 +++++
> gdb/common/tdesc.c | 1 +
> gdb/common/tdesc.h | 1 +
> gdb/features/aarch64-fpu.c | 5 +++++
> gdb/features/aarch64-fpu.xml | 2 ++
> gdb/features/aarch64-sve.c | 5 +++++
> gdb/gdbtypes.c | 3 +++
> gdb/gdbtypes.h | 2 ++
> gdb/target-descriptions.c | 5 +++++
> 9 files changed, 29 insertions(+)
>
> diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
> index 1b3977bfaf..8a5e7b9570 100644
> --- a/gdb/aarch64-tdep.c
> +++ b/gdb/aarch64-tdep.c
> @@ -1928,6 +1928,9 @@ aarch64_vnh_type (struct gdbarch *gdbarch)
> t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
> TYPE_CODE_UNION);
>
> + elem = builtin_type (gdbarch)->builtin_half;
> + append_composite_type_field (t, "f", elem);
> +
> elem = builtin_type (gdbarch)->builtin_uint16;
> append_composite_type_field (t, "u", elem);
>
> @@ -2006,6 +2009,8 @@ aarch64_vnv_type (struct gdbarch *gdbarch)
>
> sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh",
> TYPE_CODE_UNION);
> + append_composite_type_field (sub, "f",
> + init_vector_type (bt->builtin_half, 8));
> append_composite_type_field (sub, "u",
> init_vector_type (bt->builtin_uint16, 8));
> append_composite_type_field (sub, "s",
> diff --git a/gdb/common/tdesc.c b/gdb/common/tdesc.c
> index fe63a36c33..f946a53c7f 100644
> --- a/gdb/common/tdesc.c
> +++ b/gdb/common/tdesc.c
> @@ -50,6 +50,7 @@ static tdesc_type_builtin tdesc_predefined_types[] =
> { "uint128", TDESC_TYPE_UINT128 },
> { "code_ptr", TDESC_TYPE_CODE_PTR },
> { "data_ptr", TDESC_TYPE_DATA_PTR },
> + { "ieee_half", TDESC_TYPE_IEEE_HALF },
> { "ieee_single", TDESC_TYPE_IEEE_SINGLE },
> { "ieee_double", TDESC_TYPE_IEEE_DOUBLE },
> { "arm_fpa_ext", TDESC_TYPE_ARM_FPA_EXT },
> diff --git a/gdb/common/tdesc.h b/gdb/common/tdesc.h
> index a0bc6339e2..9eb3d5ea31 100644
> --- a/gdb/common/tdesc.h
> +++ b/gdb/common/tdesc.h
> @@ -147,6 +147,7 @@ enum tdesc_type_kind
> TDESC_TYPE_UINT128,
> TDESC_TYPE_CODE_PTR,
> TDESC_TYPE_DATA_PTR,
> + TDESC_TYPE_IEEE_HALF,
> TDESC_TYPE_IEEE_SINGLE,
> TDESC_TYPE_IEEE_DOUBLE,
> TDESC_TYPE_ARM_FPA_EXT,
> diff --git a/gdb/features/aarch64-fpu.c b/gdb/features/aarch64-fpu.c
> index 47962d1f24..b73d12ebe4 100644
> --- a/gdb/features/aarch64-fpu.c
> +++ b/gdb/features/aarch64-fpu.c
> @@ -28,6 +28,9 @@ create_feature_aarch64_fpu (struct target_desc *result, long regnum)
> element_type = tdesc_named_type (feature, "int32");
> tdesc_create_vector (feature, "v4i", element_type, 4);
>
> + element_type = tdesc_named_type (feature, "ieee_half");
> + tdesc_create_vector (feature, "v8f", element_type, 8);
> +
> element_type = tdesc_named_type (feature, "uint16");
> tdesc_create_vector (feature, "v8u", element_type, 8);
>
> @@ -65,6 +68,8 @@ create_feature_aarch64_fpu (struct target_desc *result, long regnum)
> tdesc_add_field (type_with_fields, "s", field_type);
>
> type_with_fields = tdesc_create_union (feature, "vnh");
> + field_type = tdesc_named_type (feature, "v8f");
> + tdesc_add_field (type_with_fields, "f", field_type);
> field_type = tdesc_named_type (feature, "v8u");
> tdesc_add_field (type_with_fields, "u", field_type);
> field_type = tdesc_named_type (feature, "v8i");
> diff --git a/gdb/features/aarch64-fpu.xml b/gdb/features/aarch64-fpu.xml
> index 141c996ead..1eba8faea7 100644
> --- a/gdb/features/aarch64-fpu.xml
> +++ b/gdb/features/aarch64-fpu.xml
> @@ -14,6 +14,7 @@
> <vector id="v4f" type="ieee_single" count="4"/>
> <vector id="v4u" type="uint32" count="4"/>
> <vector id="v4i" type="int32" count="4"/>
> + <vector id="v8f" type="ieee_half" count="8"/>
> <vector id="v8u" type="uint16" count="8"/>
> <vector id="v8i" type="int16" count="8"/>
> <vector id="v16u" type="uint8" count="16"/>
> @@ -31,6 +32,7 @@
> <field name="s" type="v4i"/>
> </union>
> <union id="vnh">
> + <field name="f" type="v8f"/>
> <field name="u" type="v8u"/>
> <field name="s" type="v8i"/>
> </union>
> diff --git a/gdb/features/aarch64-sve.c b/gdb/features/aarch64-sve.c
> index 2166b4bb07..ae292d2f3d 100644
> --- a/gdb/features/aarch64-sve.c
> +++ b/gdb/features/aarch64-sve.c
> @@ -55,6 +55,9 @@ create_feature_aarch64_sve (struct target_desc *result, long regnum,
> element_type = tdesc_named_type (feature, "int32");
> tdesc_create_vector (feature, "svevss", element_type, 4 * scale);
>
> + element_type = tdesc_named_type (feature, "ieee_half");
> + tdesc_create_vector (feature, "svevhf", element_type, 8 * scale);
> +
> element_type = tdesc_named_type (feature, "uint16");
> tdesc_create_vector (feature, "svevhu", element_type, 8 * scale);
>
> @@ -90,6 +93,8 @@ create_feature_aarch64_sve (struct target_desc *result, long regnum,
> tdesc_add_field (type_with_fields, "s", field_type);
>
> type_with_fields = tdesc_create_union (feature, "svevnh");
> + field_type = tdesc_named_type (feature, "svevhf");
> + tdesc_add_field (type_with_fields, "f", field_type);
> field_type = tdesc_named_type (feature, "svevhu");
> tdesc_add_field (type_with_fields, "u", field_type);
> field_type = tdesc_named_type (feature, "svevhs");
> diff --git a/gdb/gdbtypes.c b/gdb/gdbtypes.c
> index 683238d03d..58d1573b1a 100644
> --- a/gdb/gdbtypes.c
> +++ b/gdb/gdbtypes.c
> @@ -5358,6 +5358,9 @@ gdbtypes_post_init (struct gdbarch *gdbarch)
> builtin_type->builtin_unsigned_long_long
> = arch_integer_type (gdbarch, gdbarch_long_long_bit (gdbarch),
> 1, "unsigned long long");
> + builtin_type->builtin_half
> + = arch_float_type (gdbarch, gdbarch_half_bit (gdbarch),
> + "half", gdbarch_half_format (gdbarch));
> builtin_type->builtin_float
> = arch_float_type (gdbarch, gdbarch_float_bit (gdbarch),
> "float", gdbarch_float_format (gdbarch));
> diff --git a/gdb/gdbtypes.h b/gdb/gdbtypes.h
> index 2125ed991d..e6f41e2265 100644
> --- a/gdb/gdbtypes.h
> +++ b/gdb/gdbtypes.h
> @@ -1581,6 +1581,7 @@ struct builtin_type
> struct type *builtin_unsigned_short;
> struct type *builtin_unsigned_int;
> struct type *builtin_unsigned_long;
> + struct type *builtin_half;
> struct type *builtin_float;
> struct type *builtin_double;
> struct type *builtin_long_double;
> @@ -1676,6 +1677,7 @@ struct objfile_type
> struct type *builtin_unsigned_int;
> struct type *builtin_unsigned_long;
> struct type *builtin_unsigned_long_long;
> + struct type *builtin_half;
> struct type *builtin_float;
> struct type *builtin_double;
> struct type *builtin_long_double;
> diff --git a/gdb/target-descriptions.c b/gdb/target-descriptions.c
> index 96d453527c..bd33091ba9 100644
> --- a/gdb/target-descriptions.c
> +++ b/gdb/target-descriptions.c
> @@ -119,6 +119,11 @@ make_gdb_type (struct gdbarch *gdbarch, struct tdesc_type *ttype)
>
> switch (e->kind)
> {
> + case TDESC_TYPE_IEEE_HALF:
> + m_type = arch_float_type (m_gdbarch, -1, "builtin_type_ieee_half",
> + floatformats_ieee_half);
> + return;
> +
> case TDESC_TYPE_IEEE_SINGLE:
> m_type = arch_float_type (m_gdbarch, -1, "builtin_type_ieee_single",
> floatformats_ieee_single);
> --
> 2.20.1 (Apple Git-117)
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] AArch64: Add half float view to V registers
2019-05-14 8:15 ` Andrew Burgess
@ 2019-05-14 9:38 ` Alan Hayward
0 siblings, 0 replies; 4+ messages in thread
From: Alan Hayward @ 2019-05-14 9:38 UTC (permalink / raw)
To: Andrew Burgess; +Cc: gdb-patches, nd
> On 14 May 2019, at 09:15, Andrew Burgess <andrew.burgess@embecosm.com> wrote:
>
> * Alan Hayward <Alan.Hayward@arm.com> [2019-04-12 10:45:07 +0000]:
>
>> AArch64 can fill the vector registers with half precision floats.
>> Add a view for this.
>>
>> Add builtin type ieee half and connect this to the existing
>> floatformats_ieee_half.
>>
>> gdb/ChangeLog:
>>
>> 2019-04-12 Alan Hayward <alan.hayward@arm.com>
>>
>> * aarch64-tdep.c (aarch64_vnh_type): Add half view.
>> (aarch64_vnv_type): Likewise.
>> * target-descriptions.c (make_gdb_type): Add TDESC_TYPE_IEEE_HALF.
>> * common/tdesc.c: Likewise.
>> * common/tdesc.h (enum tdesc_type_kind): Likewise.
>> * features/aarch64-fpu.c (create_feature_aarch64_fpu): Regenerate.
>> * features/aarch64-fpu.xml: Add ieee half view.
>> * features/aarch64-sve.c (create_feature_aarch64_fpu): Likewise.
>> * gdbtypes.c (gdbtypes_post_init): Add builtin_half
>> * gdbtypes.h (struct builtin_type): Likewise.
>> (struct objfile_type): Likewise.
>
> This patch looks fine to apply. I was a little surprised that this
> didn't require any test updates, but I guess if there's already not
> tests for this stuff then that's fine.
I’ve just doubled checked, and there’s no new fails. Looks like that’s due to
the small number of aarch64 specific tests. Might be worth me adding something
at a later date.
Either way, I’ve pushed this.
Thanks!
Alan.
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-05-14 9:38 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2019-04-12 10:45 [PATCH] AArch64: Add half float view to V registers Alan Hayward
2019-05-13 14:57 ` [PING] " Alan Hayward
2019-05-14 8:15 ` Andrew Burgess
2019-05-14 9:38 ` Alan Hayward
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