* [PATCH 2/3] Arm: Prefix register sizes with ARM_
2019-06-26 13:19 [PATCH 1/3] Arm/AArch64: Split DISPLACED_MODIFIED_INSNS name clash Alan Hayward
2019-06-26 13:19 ` [PATCH 3/3] Arm/AArch64: Use a single set of Arm register set size defines Alan Hayward
@ 2019-06-26 13:19 ` Alan Hayward
2019-06-27 15:53 ` Alan Hayward
2019-07-04 11:54 ` [PATCH 1/3] Arm/AArch64: Split DISPLACED_MODIFIED_INSNS name clash Alan Hayward
2 siblings, 1 reply; 5+ messages in thread
From: Alan Hayward @ 2019-06-26 13:19 UTC (permalink / raw)
To: gdb-patches; +Cc: nd, Alan Hayward
Add ARM_ to the front of INT_REGISTER_SIZE, FP_REGISTER_SIZE and
ARM_VFP_REGISTER_SIZE to make it obvious they are for the Arm target.
Move the defines to arch/arm.h
No functionality changes.
gdb/ChangeLog:
2019-06-26 Alan Hayward <alan.hayward@arm.com>
* arch/arm-get-next-pcs.c (thumb_get_next_pcs_raw): Use ARM_
defines.
* arch/arm-linux.c (arm_linux_sigreturn_next_pc_offset): Likewise.
* arch/arm.h (INT_REGISTER_SIZE) Rename from...
(ARM_INT_REGISTER_SIZE): ...to this.
(ARM_FP_REGISTER_SIZE) (ARM_VFP_REGISTER_SIZE): Add define.
* arm-linux-tdep.c (ARM_LINUX_JB_ELEMENT_SIZE)
(ARM_LINUX_SIZEOF_GREGSET, arm_linux_supply_gregset)
(arm_linux_collect_gregset, supply_nwfpe_register)
(collect_nwfpe_register, arm_linux_collect_nwfpe): Use ARM_
defines.
* arm-linux-tdep.h (ARM_LINUX_SIZEOF_NWFPE, NWFPE_FPSR_OFFSET)
(NWFPE_FPCR_OFFSET, NWFPE_TAGS_OFFSET): Likewise
* arm-tdep.c (arm_push_dummy_call, arm_extract_return_value)
(arm_return_in_memory, arm_store_return_value)
(arm_get_longjmp_target, arm_register_g_packet_guesses)
(arm_record_ld_st_multiple): Likewise.
* arm-tdep.h (FP_REGISTER_SIZE, VFP_REGISTER_SIZE): Remove.
---
gdb/arch/arm-get-next-pcs.c | 3 +-
gdb/arch/arm-linux.c | 2 +-
gdb/arch/arm.h | 8 ++-
gdb/arm-linux-tdep.c | 41 +++++++-------
gdb/arm-linux-tdep.h | 12 ++--
gdb/arm-tdep.c | 108 +++++++++++++++++++-----------------
gdb/arm-tdep.h | 9 ---
7 files changed, 92 insertions(+), 91 deletions(-)
diff --git a/gdb/arch/arm-get-next-pcs.c b/gdb/arch/arm-get-next-pcs.c
index 06b3f2c992..00c7064d8b 100644
--- a/gdb/arch/arm-get-next-pcs.c
+++ b/gdb/arch/arm-get-next-pcs.c
@@ -408,7 +408,8 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
/* Fetch the saved PC from the stack. It's stored above
all of the other registers. */
- unsigned long offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
+ unsigned long offset = bitcount (bits (inst1, 0, 7))
+ * ARM_INT_REGISTER_SIZE;
sp = regcache_raw_get_unsigned (regcache, ARM_SP_REGNUM);
nextpc = self->ops->read_mem_uint (sp + offset, 4, byte_order);
}
diff --git a/gdb/arch/arm-linux.c b/gdb/arch/arm-linux.c
index a399f3e71c..180228fe89 100644
--- a/gdb/arch/arm-linux.c
+++ b/gdb/arch/arm-linux.c
@@ -53,7 +53,7 @@ arm_linux_sigreturn_next_pc_offset (unsigned long sp,
r0_offset += ARM_UCONTEXT_SIGCONTEXT + ARM_SIGCONTEXT_R0;
}
- pc_offset = r0_offset + INT_REGISTER_SIZE * ARM_PC_REGNUM;
+ pc_offset = r0_offset + ARM_INT_REGISTER_SIZE * ARM_PC_REGNUM;
return pc_offset;
}
diff --git a/gdb/arch/arm.h b/gdb/arch/arm.h
index c1785425e8..0ebbf89a9c 100644
--- a/gdb/arch/arm.h
+++ b/gdb/arch/arm.h
@@ -93,8 +93,12 @@ enum arm_breakpoint_kinds
#define XPSR_T 0x01000000
-/* Size of integer registers. */
-#define INT_REGISTER_SIZE 4
+/* Size of registers. */
+
+#define ARM_INT_REGISTER_SIZE 4
+/* IEEE extended doubles are 80 bits. DWORD aligned they use 96 bits. */
+#define ARM_FP_REGISTER_SIZE 12
+#define ARM_VFP_REGISTER_SIZE 8
/* Addresses for calling Thumb functions have the bit 0 set.
Here are some macros to test, set, or clear bit 0 of addresses. */
diff --git a/gdb/arm-linux-tdep.c b/gdb/arm-linux-tdep.c
index 8c0c0585d7..d846749e0b 100644
--- a/gdb/arm-linux-tdep.c
+++ b/gdb/arm-linux-tdep.c
@@ -103,7 +103,7 @@ static const gdb_byte arm_linux_thumb2_le_breakpoint[] = { 0xf0, 0xf7, 0x00, 0xa
SoftVFP or VFP (which implies EABI) then the PC is at offset 9 in the
buffer. This is also true for the SoftFPA model. However, for the FPA
model the PC is at offset 21 in the buffer. */
-#define ARM_LINUX_JB_ELEMENT_SIZE INT_REGISTER_SIZE
+#define ARM_LINUX_JB_ELEMENT_SIZE ARM_INT_REGISTER_SIZE
#define ARM_LINUX_JB_PC_FPA 21
#define ARM_LINUX_JB_PC_EABI 9
@@ -471,7 +471,7 @@ static struct tramp_frame arm_kernel_linux_restart_syscall_tramp_frame = {
/* Core file and register set support. */
-#define ARM_LINUX_SIZEOF_GREGSET (18 * INT_REGISTER_SIZE)
+#define ARM_LINUX_SIZEOF_GREGSET (18 * ARM_INT_REGISTER_SIZE)
void
arm_linux_supply_gregset (const struct regset *regset,
@@ -483,29 +483,30 @@ arm_linux_supply_gregset (const struct regset *regset,
const gdb_byte *gregs = (const gdb_byte *) gregs_buf;
int regno;
CORE_ADDR reg_pc;
- gdb_byte pc_buf[INT_REGISTER_SIZE];
+ gdb_byte pc_buf[ARM_INT_REGISTER_SIZE];
for (regno = ARM_A1_REGNUM; regno < ARM_PC_REGNUM; regno++)
if (regnum == -1 || regnum == regno)
- regcache->raw_supply (regno, gregs + INT_REGISTER_SIZE * regno);
+ regcache->raw_supply (regno, gregs + ARM_INT_REGISTER_SIZE * regno);
if (regnum == ARM_PS_REGNUM || regnum == -1)
{
if (arm_apcs_32)
regcache->raw_supply (ARM_PS_REGNUM,
- gregs + INT_REGISTER_SIZE * ARM_CPSR_GREGNUM);
+ gregs + ARM_INT_REGISTER_SIZE * ARM_CPSR_GREGNUM);
else
regcache->raw_supply (ARM_PS_REGNUM,
- gregs + INT_REGISTER_SIZE * ARM_PC_REGNUM);
+ gregs + ARM_INT_REGISTER_SIZE * ARM_PC_REGNUM);
}
if (regnum == ARM_PC_REGNUM || regnum == -1)
{
- reg_pc = extract_unsigned_integer (gregs
- + INT_REGISTER_SIZE * ARM_PC_REGNUM,
- INT_REGISTER_SIZE, byte_order);
+ reg_pc = extract_unsigned_integer (
+ gregs + ARM_INT_REGISTER_SIZE * ARM_PC_REGNUM,
+ ARM_INT_REGISTER_SIZE, byte_order);
reg_pc = gdbarch_addr_bits_remove (gdbarch, reg_pc);
- store_unsigned_integer (pc_buf, INT_REGISTER_SIZE, byte_order, reg_pc);
+ store_unsigned_integer (pc_buf, ARM_INT_REGISTER_SIZE, byte_order,
+ reg_pc);
regcache->raw_supply (ARM_PC_REGNUM, pc_buf);
}
}
@@ -521,21 +522,21 @@ arm_linux_collect_gregset (const struct regset *regset,
for (regno = ARM_A1_REGNUM; regno < ARM_PC_REGNUM; regno++)
if (regnum == -1 || regnum == regno)
regcache->raw_collect (regno,
- gregs + INT_REGISTER_SIZE * regno);
+ gregs + ARM_INT_REGISTER_SIZE * regno);
if (regnum == ARM_PS_REGNUM || regnum == -1)
{
if (arm_apcs_32)
regcache->raw_collect (ARM_PS_REGNUM,
- gregs + INT_REGISTER_SIZE * ARM_CPSR_GREGNUM);
+ gregs + ARM_INT_REGISTER_SIZE * ARM_CPSR_GREGNUM);
else
regcache->raw_collect (ARM_PS_REGNUM,
- gregs + INT_REGISTER_SIZE * ARM_PC_REGNUM);
+ gregs + ARM_INT_REGISTER_SIZE * ARM_PC_REGNUM);
}
if (regnum == ARM_PC_REGNUM || regnum == -1)
regcache->raw_collect (ARM_PC_REGNUM,
- gregs + INT_REGISTER_SIZE * ARM_PC_REGNUM);
+ gregs + ARM_INT_REGISTER_SIZE * ARM_PC_REGNUM);
}
/* Support for register format used by the NWFPE FPA emulator. */
@@ -551,11 +552,11 @@ supply_nwfpe_register (struct regcache *regcache, int regno,
{
const gdb_byte *reg_data;
gdb_byte reg_tag;
- gdb_byte buf[FP_REGISTER_SIZE];
+ gdb_byte buf[ARM_FP_REGISTER_SIZE];
- reg_data = regs + (regno - ARM_F0_REGNUM) * FP_REGISTER_SIZE;
+ reg_data = regs + (regno - ARM_F0_REGNUM) * ARM_FP_REGISTER_SIZE;
reg_tag = regs[(regno - ARM_F0_REGNUM) + NWFPE_TAGS_OFFSET];
- memset (buf, 0, FP_REGISTER_SIZE);
+ memset (buf, 0, ARM_FP_REGISTER_SIZE);
switch (reg_tag)
{
@@ -586,7 +587,7 @@ collect_nwfpe_register (const struct regcache *regcache, int regno,
{
gdb_byte *reg_data;
gdb_byte reg_tag;
- gdb_byte buf[FP_REGISTER_SIZE];
+ gdb_byte buf[ARM_FP_REGISTER_SIZE];
regcache->raw_collect (regno, buf);
@@ -595,7 +596,7 @@ collect_nwfpe_register (const struct regcache *regcache, int regno,
from the native file to the target file. But this doesn't
always make sense. */
- reg_data = regs + (regno - ARM_F0_REGNUM) * FP_REGISTER_SIZE;
+ reg_data = regs + (regno - ARM_F0_REGNUM) * ARM_FP_REGISTER_SIZE;
reg_tag = regs[(regno - ARM_F0_REGNUM) + NWFPE_TAGS_OFFSET];
switch (reg_tag)
@@ -648,7 +649,7 @@ arm_linux_collect_nwfpe (const struct regset *regset,
if (regnum == ARM_FPS_REGNUM || regnum == -1)
regcache->raw_collect (ARM_FPS_REGNUM,
- regs + INT_REGISTER_SIZE * ARM_FPS_REGNUM);
+ regs + ARM_INT_REGISTER_SIZE * ARM_FPS_REGNUM);
}
/* Support VFP register format. */
diff --git a/gdb/arm-linux-tdep.h b/gdb/arm-linux-tdep.h
index 8f43048148..a17bf4e3e4 100644
--- a/gdb/arm-linux-tdep.h
+++ b/gdb/arm-linux-tdep.h
@@ -23,9 +23,9 @@
struct regset;
struct regcache;
-#define ARM_LINUX_SIZEOF_NWFPE (8 * FP_REGISTER_SIZE \
- + 2 * INT_REGISTER_SIZE \
- + 8 + INT_REGISTER_SIZE)
+#define ARM_LINUX_SIZEOF_NWFPE (8 * ARM_FP_REGISTER_SIZE \
+ + 2 * ARM_INT_REGISTER_SIZE \
+ + 8 + ARM_INT_REGISTER_SIZE)
/* Support for register format used by the NWFPE FPA emulator. Each
register takes three words, where either the first one, two, or
@@ -35,9 +35,9 @@ struct regcache;
final word flag which indicates whether NWFPE has been
initialized. */
-#define NWFPE_FPSR_OFFSET (8 * FP_REGISTER_SIZE)
-#define NWFPE_FPCR_OFFSET (NWFPE_FPSR_OFFSET + INT_REGISTER_SIZE)
-#define NWFPE_TAGS_OFFSET (NWFPE_FPCR_OFFSET + INT_REGISTER_SIZE)
+#define NWFPE_FPSR_OFFSET (8 * ARM_FP_REGISTER_SIZE)
+#define NWFPE_FPCR_OFFSET (NWFPE_FPSR_OFFSET + ARM_INT_REGISTER_SIZE)
+#define NWFPE_TAGS_OFFSET (NWFPE_FPCR_OFFSET + ARM_INT_REGISTER_SIZE)
#define NWFPE_INITFLAG_OFFSET (NWFPE_TAGS_OFFSET + 8)
void arm_linux_supply_gregset (const struct regset *regset,
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 5b1f360f9f..529dd68801 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -3696,18 +3696,19 @@ arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
align = type_align (arg_type);
/* Round alignment up to a whole number of words. */
- align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
+ align = (align + ARM_INT_REGISTER_SIZE - 1)
+ & ~(ARM_INT_REGISTER_SIZE - 1);
/* Different ABIs have different maximum alignments. */
if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
{
/* The APCS ABI only requires word alignment. */
- align = INT_REGISTER_SIZE;
+ align = ARM_INT_REGISTER_SIZE;
}
else
{
/* The AAPCS requires at most doubleword alignment. */
- if (align > INT_REGISTER_SIZE * 2)
- align = INT_REGISTER_SIZE * 2;
+ if (align > ARM_INT_REGISTER_SIZE * 2)
+ align = ARM_INT_REGISTER_SIZE * 2;
}
if (use_vfp_abi
@@ -3772,14 +3773,14 @@ arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
/* Push stack padding for dowubleword alignment. */
if (nstack & (align - 1))
{
- si = push_stack_item (si, val, INT_REGISTER_SIZE);
- nstack += INT_REGISTER_SIZE;
+ si = push_stack_item (si, val, ARM_INT_REGISTER_SIZE);
+ nstack += ARM_INT_REGISTER_SIZE;
}
/* Doubleword aligned quantities must go in even register pairs. */
if (may_use_core_reg
&& argreg <= ARM_LAST_ARG_REGNUM
- && align > INT_REGISTER_SIZE
+ && align > ARM_INT_REGISTER_SIZE
&& argreg & 1)
argreg++;
@@ -3805,7 +3806,8 @@ arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
registers and stack. */
while (len > 0)
{
- int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
+ int partial_len = len < ARM_INT_REGISTER_SIZE
+ ? len : ARM_INT_REGISTER_SIZE;
CORE_ADDR regval
= extract_unsigned_integer (val, partial_len, byte_order);
@@ -3814,19 +3816,19 @@ arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
/* The argument is being passed in a general purpose
register. */
if (byte_order == BFD_ENDIAN_BIG)
- regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
+ regval <<= (ARM_INT_REGISTER_SIZE - partial_len) * 8;
if (arm_debug)
fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
argnum,
gdbarch_register_name
(gdbarch, argreg),
- phex (regval, INT_REGISTER_SIZE));
+ phex (regval, ARM_INT_REGISTER_SIZE));
regcache_cooked_write_unsigned (regcache, argreg, regval);
argreg++;
}
else
{
- gdb_byte buf[INT_REGISTER_SIZE];
+ gdb_byte buf[ARM_INT_REGISTER_SIZE];
memset (buf, 0, sizeof (buf));
store_unsigned_integer (buf, partial_len, byte_order, regval);
@@ -3835,8 +3837,8 @@ arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
if (arm_debug)
fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
argnum, nstack);
- si = push_stack_item (si, buf, INT_REGISTER_SIZE);
- nstack += INT_REGISTER_SIZE;
+ si = push_stack_item (si, buf, ARM_INT_REGISTER_SIZE);
+ nstack += ARM_INT_REGISTER_SIZE;
}
len -= partial_len;
@@ -7842,7 +7844,7 @@ arm_extract_return_value (struct type *type, struct regcache *regs,
/* The value is in register F0 in internal format. We need to
extract the raw value and then convert it to the desired
internal type. */
- bfd_byte tmpbuf[FP_REGISTER_SIZE];
+ bfd_byte tmpbuf[ARM_FP_REGISTER_SIZE];
regs->cooked_read (ARM_F0_REGNUM, tmpbuf);
target_float_convert (tmpbuf, arm_ext_type (gdbarch),
@@ -7857,7 +7859,8 @@ arm_extract_return_value (struct type *type, struct regcache *regs,
case ARM_FLOAT_VFP:
regs->cooked_read (ARM_A1_REGNUM, valbuf);
if (TYPE_LENGTH (type) > 4)
- regs->cooked_read (ARM_A1_REGNUM + 1, valbuf + INT_REGISTER_SIZE);
+ regs->cooked_read (ARM_A1_REGNUM + 1,
+ valbuf + ARM_INT_REGISTER_SIZE);
break;
default:
@@ -7887,11 +7890,11 @@ arm_extract_return_value (struct type *type, struct regcache *regs,
anything special for small big-endian values. */
regcache_cooked_read_unsigned (regs, regno++, &tmp);
store_unsigned_integer (valbuf,
- (len > INT_REGISTER_SIZE
- ? INT_REGISTER_SIZE : len),
+ (len > ARM_INT_REGISTER_SIZE
+ ? ARM_INT_REGISTER_SIZE : len),
byte_order, tmp);
- len -= INT_REGISTER_SIZE;
- valbuf += INT_REGISTER_SIZE;
+ len -= ARM_INT_REGISTER_SIZE;
+ valbuf += ARM_INT_REGISTER_SIZE;
}
}
else
@@ -7901,15 +7904,15 @@ arm_extract_return_value (struct type *type, struct regcache *regs,
registers with 32-bit load instruction(s). */
int len = TYPE_LENGTH (type);
int regno = ARM_A1_REGNUM;
- bfd_byte tmpbuf[INT_REGISTER_SIZE];
+ bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE];
while (len > 0)
{
regs->cooked_read (regno++, tmpbuf);
memcpy (valbuf, tmpbuf,
- len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
- len -= INT_REGISTER_SIZE;
- valbuf += INT_REGISTER_SIZE;
+ len > ARM_INT_REGISTER_SIZE ? ARM_INT_REGISTER_SIZE : len);
+ len -= ARM_INT_REGISTER_SIZE;
+ valbuf += ARM_INT_REGISTER_SIZE;
}
}
}
@@ -7944,7 +7947,7 @@ arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
{
/* The AAPCS says all aggregates not larger than a word are returned
in a register. */
- if (TYPE_LENGTH (type) <= INT_REGISTER_SIZE)
+ if (TYPE_LENGTH (type) <= ARM_INT_REGISTER_SIZE)
return 0;
return 1;
@@ -7955,12 +7958,12 @@ arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
/* All aggregate types that won't fit in a register must be returned
in memory. */
- if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
+ if (TYPE_LENGTH (type) > ARM_INT_REGISTER_SIZE)
return 1;
/* In the ARM ABI, "integer" like aggregate types are returned in
registers. For an aggregate type to be integer like, its size
- must be less than or equal to INT_REGISTER_SIZE and the
+ must be less than or equal to ARM_INT_REGISTER_SIZE and the
offset of each addressable subfield must be zero. Note that bit
fields are not addressable, and all addressable subfields of
unions always start at offset zero.
@@ -7984,7 +7987,7 @@ arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
int i;
/* Need to check if this struct/union is "integer" like. For
this to be true, its size must be less than or equal to
- INT_REGISTER_SIZE and the offset of each addressable
+ ARM_INT_REGISTER_SIZE and the offset of each addressable
subfield must be zero. Note that bit fields are not
addressable, and unions always start at offset zero. If any
of the subfields is a floating point type, the struct/union
@@ -8043,7 +8046,7 @@ arm_store_return_value (struct type *type, struct regcache *regs,
if (TYPE_CODE (type) == TYPE_CODE_FLT)
{
- gdb_byte buf[FP_REGISTER_SIZE];
+ gdb_byte buf[ARM_FP_REGISTER_SIZE];
switch (gdbarch_tdep (gdbarch)->fp_model)
{
@@ -8060,7 +8063,8 @@ arm_store_return_value (struct type *type, struct regcache *regs,
case ARM_FLOAT_VFP:
regs->cooked_write (ARM_A1_REGNUM, valbuf);
if (TYPE_LENGTH (type) > 4)
- regs->cooked_write (ARM_A1_REGNUM + 1, valbuf + INT_REGISTER_SIZE);
+ regs->cooked_write (ARM_A1_REGNUM + 1,
+ valbuf + ARM_INT_REGISTER_SIZE);
break;
default:
@@ -8081,10 +8085,10 @@ arm_store_return_value (struct type *type, struct regcache *regs,
{
/* Values of one word or less are zero/sign-extended and
returned in r0. */
- bfd_byte tmpbuf[INT_REGISTER_SIZE];
+ bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE];
LONGEST val = unpack_long (type, valbuf);
- store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
+ store_signed_integer (tmpbuf, ARM_INT_REGISTER_SIZE, byte_order, val);
regs->cooked_write (ARM_A1_REGNUM, tmpbuf);
}
else
@@ -8098,8 +8102,8 @@ arm_store_return_value (struct type *type, struct regcache *regs,
while (len > 0)
{
regs->cooked_write (regno++, valbuf);
- len -= INT_REGISTER_SIZE;
- valbuf += INT_REGISTER_SIZE;
+ len -= ARM_INT_REGISTER_SIZE;
+ valbuf += ARM_INT_REGISTER_SIZE;
}
}
}
@@ -8110,15 +8114,15 @@ arm_store_return_value (struct type *type, struct regcache *regs,
registers with 32-bit load instruction(s). */
int len = TYPE_LENGTH (type);
int regno = ARM_A1_REGNUM;
- bfd_byte tmpbuf[INT_REGISTER_SIZE];
+ bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE];
while (len > 0)
{
memcpy (tmpbuf, valbuf,
- len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
+ len > ARM_INT_REGISTER_SIZE ? ARM_INT_REGISTER_SIZE : len);
regs->cooked_write (regno++, tmpbuf);
- len -= INT_REGISTER_SIZE;
- valbuf += INT_REGISTER_SIZE;
+ len -= ARM_INT_REGISTER_SIZE;
+ valbuf += ARM_INT_REGISTER_SIZE;
}
}
}
@@ -8202,15 +8206,15 @@ arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR jb_addr;
- gdb_byte buf[INT_REGISTER_SIZE];
+ gdb_byte buf[ARM_INT_REGISTER_SIZE];
jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
- INT_REGISTER_SIZE))
+ ARM_INT_REGISTER_SIZE))
return 0;
- *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order);
+ *pc = extract_unsigned_integer (buf, ARM_INT_REGISTER_SIZE, byte_order);
return 1;
}
@@ -8791,24 +8795,24 @@ arm_register_g_packet_guesses (struct gdbarch *gdbarch)
same as the FPA layout. */
register_remote_g_packet_guess (gdbarch,
/* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
- (16 * INT_REGISTER_SIZE)
- + (8 * FP_REGISTER_SIZE)
- + (2 * INT_REGISTER_SIZE),
+ (16 * ARM_INT_REGISTER_SIZE)
+ + (8 * ARM_FP_REGISTER_SIZE)
+ + (2 * ARM_INT_REGISTER_SIZE),
tdesc_arm_with_m_fpa_layout);
/* The regular M-profile layout. */
register_remote_g_packet_guess (gdbarch,
/* r0-r12,sp,lr,pc; xpsr */
- (16 * INT_REGISTER_SIZE)
- + INT_REGISTER_SIZE,
+ (16 * ARM_INT_REGISTER_SIZE)
+ + ARM_INT_REGISTER_SIZE,
tdesc_arm_with_m);
/* M-profile plus M4F VFP. */
register_remote_g_packet_guess (gdbarch,
/* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
- (16 * INT_REGISTER_SIZE)
- + (16 * VFP_REGISTER_SIZE)
- + (2 * INT_REGISTER_SIZE),
+ (16 * ARM_INT_REGISTER_SIZE)
+ + (16 * ARM_VFP_REGISTER_SIZE)
+ + (2 * ARM_INT_REGISTER_SIZE),
tdesc_arm_with_m_vfp_d16);
}
@@ -10980,7 +10984,7 @@ arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
/* STMDA (STMED): Decrement after. */
case 0:
record_buf_mem[1] = (uint32_t) u_regval
- - register_count * INT_REGISTER_SIZE + 4;
+ - register_count * ARM_INT_REGISTER_SIZE + 4;
break;
/* STM (STMIA, STMEA): Increment after. */
case 1:
@@ -10989,18 +10993,18 @@ arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
/* STMDB (STMFD): Decrement before. */
case 2:
record_buf_mem[1] = (uint32_t) u_regval
- - register_count * INT_REGISTER_SIZE;
+ - register_count * ARM_INT_REGISTER_SIZE;
break;
/* STMIB (STMFA): Increment before. */
case 3:
- record_buf_mem[1] = (uint32_t) u_regval + INT_REGISTER_SIZE;
+ record_buf_mem[1] = (uint32_t) u_regval + ARM_INT_REGISTER_SIZE;
break;
default:
gdb_assert_not_reached ("no decoding pattern found");
break;
}
- record_buf_mem[0] = register_count * INT_REGISTER_SIZE;
+ record_buf_mem[0] = register_count * ARM_INT_REGISTER_SIZE;
arm_insn_r->mem_rec_count = 1;
/* If wback is true, also save the base register, which is going to be
diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h
index 7da11656c2..807849a5ff 100644
--- a/gdb/arm-tdep.h
+++ b/gdb/arm-tdep.h
@@ -32,15 +32,6 @@ struct gdb_get_next_pcs;
#include <vector>
-/* Say how long FP registers are. Used for documentation purposes and
- code readability in this header. IEEE extended doubles are 80
- bits. DWORD aligned they use 96 bits. */
-#define FP_REGISTER_SIZE 12
-
-/* Say how long VFP double precision registers are. Used for documentation
- purposes and code readability. These are fixed at 64 bits. */
-#define VFP_REGISTER_SIZE 8
-
/* Number of machine registers. The only define actually required
is gdbarch_num_regs. The other definitions are used for documentation
purposes and code readability. */
--
2.20.1 (Apple Git-117)
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 3/3] Arm/AArch64: Use a single set of Arm register set size defines
2019-06-26 13:19 [PATCH 1/3] Arm/AArch64: Split DISPLACED_MODIFIED_INSNS name clash Alan Hayward
@ 2019-06-26 13:19 ` Alan Hayward
2019-06-26 13:19 ` [PATCH 2/3] Arm: Prefix register sizes with ARM_ Alan Hayward
2019-07-04 11:54 ` [PATCH 1/3] Arm/AArch64: Split DISPLACED_MODIFIED_INSNS name clash Alan Hayward
2 siblings, 0 replies; 5+ messages in thread
From: Alan Hayward @ 2019-06-26 13:19 UTC (permalink / raw)
To: gdb-patches; +Cc: nd, Alan Hayward
Both targets were using a mixture of defines and hardcoded values.
Add a standard set in arch/arm.h and use throughout, ensuring that
none of the existing sizes change.
No functionality changes.
gdb/ChangeLog:
2019-06-26 Alan Hayward <alan.hayward@arm.com>
* aarch32-linux-nat.h (VFP_REGS_SIZE): Remove define.
* aarch64-linux-nat.c (fetch_fpregs_from_thread)
(store_fpregs_to_thread)
(aarch64_linux_nat_target::read_description): Use ARM_VFP3_REGS_SIZE.
* arch/arm.h (IWMMXT_VEC_REGISTER_SIZE, ARM_CORE_REGS_SIZE)
(ARM_FP_REGS_SIZE, ARM_VFP2_REGS_SIZE, ARM_VFP3_REGS_SIZE)
(IWMMXT_REGS_SIZE): Add define.
* arm-linux-nat.c (IWMMXT_REGS_SIZE): Remove define.
(fetch_vfp_regs, store_vfp_regs)
(arm_linux_nat_target::read_description): Use ARM_VFP3_REGS_SIZE.
* arm-tdep.c (arm_register_g_packet_guesses): Use new defines.
gdb/gdbserver/ChangeLog:
2019-06-26 Alan Hayward <alan.hayward@arm.com>
* linux-aarch32-low.c (arm_read_description, arm_regsets): Use new
defines.
* linux-arm-low.c (arm_read_description, arm_regsets): Likewise.
---
gdb/aarch32-linux-nat.h | 5 -----
gdb/aarch64-linux-nat.c | 13 +++++++------
gdb/arch/arm.h | 15 +++++++++++++++
gdb/arm-linux-nat.c | 14 ++++++--------
gdb/arm-tdep.c | 15 +++------------
gdb/gdbserver/linux-aarch32-low.c | 6 +++---
gdb/gdbserver/linux-arm-low.c | 12 +++++-------
7 files changed, 39 insertions(+), 41 deletions(-)
diff --git a/gdb/aarch32-linux-nat.h b/gdb/aarch32-linux-nat.h
index 093211c812..e86593a8ad 100644
--- a/gdb/aarch32-linux-nat.h
+++ b/gdb/aarch32-linux-nat.h
@@ -18,11 +18,6 @@
#ifndef AARCH32_LINUX_NAT_H
#define AARCH32_LINUX_NAT_H
-/* Fetch and store VFP Registers. The kernel object has space for 32
- 64-bit registers, and the FPSCR. This is even when on a VFPv2 or
- VFPv3D16 target. */
-#define VFP_REGS_SIZE (32 * 8 + 4)
-
void aarch32_gp_regcache_supply (struct regcache *regcache, uint32_t *regs,
int arm_apcs_32);
diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c
index 8ca9614301..7b60a9a0c3 100644
--- a/gdb/aarch64-linux-nat.c
+++ b/gdb/aarch64-linux-nat.c
@@ -30,6 +30,7 @@
#include "aarch64-tdep.h"
#include "aarch64-linux-tdep.h"
#include "aarch32-linux-nat.h"
+#include "arch/arm.h"
#include "nat/aarch64-linux.h"
#include "nat/aarch64-linux-hw-point.h"
#include "nat/aarch64-sve-linux-ptrace.h"
@@ -294,7 +295,7 @@ fetch_fpregs_from_thread (struct regcache *regcache)
/* Make sure REGS can hold all VFP registers contents on both aarch64
and arm. */
- gdb_static_assert (sizeof regs >= VFP_REGS_SIZE);
+ gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE);
tid = regcache->ptid ().lwp ();
@@ -302,7 +303,7 @@ fetch_fpregs_from_thread (struct regcache *regcache)
if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
{
- iovec.iov_len = VFP_REGS_SIZE;
+ iovec.iov_len = ARM_VFP3_REGS_SIZE;
ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
if (ret < 0)
@@ -341,14 +342,14 @@ store_fpregs_to_thread (const struct regcache *regcache)
/* Make sure REGS can hold all VFP registers contents on both aarch64
and arm. */
- gdb_static_assert (sizeof regs >= VFP_REGS_SIZE);
+ gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE);
tid = regcache->ptid ().lwp ();
iovec.iov_base = ®s;
if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
{
- iovec.iov_len = VFP_REGS_SIZE;
+ iovec.iov_len = ARM_VFP3_REGS_SIZE;
ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
if (ret < 0)
@@ -638,13 +639,13 @@ const struct target_desc *
aarch64_linux_nat_target::read_description ()
{
int ret, tid;
- gdb_byte regbuf[VFP_REGS_SIZE];
+ gdb_byte regbuf[ARM_VFP3_REGS_SIZE];
struct iovec iovec;
tid = inferior_ptid.lwp ();
iovec.iov_base = regbuf;
- iovec.iov_len = VFP_REGS_SIZE;
+ iovec.iov_len = ARM_VFP3_REGS_SIZE;
ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
if (ret == 0)
diff --git a/gdb/arch/arm.h b/gdb/arch/arm.h
index 0ebbf89a9c..dfbbd56d28 100644
--- a/gdb/arch/arm.h
+++ b/gdb/arch/arm.h
@@ -99,6 +99,21 @@ enum arm_breakpoint_kinds
/* IEEE extended doubles are 80 bits. DWORD aligned they use 96 bits. */
#define ARM_FP_REGISTER_SIZE 12
#define ARM_VFP_REGISTER_SIZE 8
+#define IWMMXT_VEC_REGISTER_SIZE 8
+
+/* Size of register sets. */
+
+/* r0-r12,sp,lr,pc,cpsr. */
+#define ARM_CORE_REGS_SIZE (17 * ARM_INT_REGISTER_SIZE)
+/* f0-f8,fps. */
+#define ARM_FP_REGS_SIZE (8 * ARM_FP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE)
+/* d0-d15,fpscr. */
+#define ARM_VFP2_REGS_SIZE (16 * ARM_VFP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE)
+/* d0-d31,fpscr. */
+#define ARM_VFP3_REGS_SIZE (32 * ARM_VFP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE)
+/* wR0-wR15,fpscr. */
+#define IWMMXT_REGS_SIZE (16 * IWMMXT_VEC_REGISTER_SIZE \
+ + 6 * ARM_INT_REGISTER_SIZE)
/* Addresses for calling Thumb functions have the bit 0 set.
Here are some macros to test, set, or clear bit 0 of addresses. */
diff --git a/gdb/arm-linux-nat.c b/gdb/arm-linux-nat.c
index c86c97d895..a1ad6fe01e 100644
--- a/gdb/arm-linux-nat.c
+++ b/gdb/arm-linux-nat.c
@@ -276,8 +276,6 @@ store_regs (const struct regcache *regcache)
/* Fetch all WMMX registers of the process and store into
regcache. */
-#define IWMMXT_REGS_SIZE (16 * 8 + 6 * 4)
-
static void
fetch_wmmx_regs (struct regcache *regcache)
{
@@ -339,7 +337,7 @@ store_wmmx_regs (const struct regcache *regcache)
static void
fetch_vfp_regs (struct regcache *regcache)
{
- gdb_byte regbuf[VFP_REGS_SIZE];
+ gdb_byte regbuf[ARM_VFP3_REGS_SIZE];
int ret, tid;
struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
@@ -352,7 +350,7 @@ fetch_vfp_regs (struct regcache *regcache)
struct iovec iov;
iov.iov_base = regbuf;
- iov.iov_len = VFP_REGS_SIZE;
+ iov.iov_len = ARM_VFP3_REGS_SIZE;
ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov);
}
else
@@ -368,7 +366,7 @@ fetch_vfp_regs (struct regcache *regcache)
static void
store_vfp_regs (const struct regcache *regcache)
{
- gdb_byte regbuf[VFP_REGS_SIZE];
+ gdb_byte regbuf[ARM_VFP3_REGS_SIZE];
int ret, tid;
struct gdbarch *gdbarch = regcache->arch ();
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
@@ -381,7 +379,7 @@ store_vfp_regs (const struct regcache *regcache)
struct iovec iov;
iov.iov_base = regbuf;
- iov.iov_len = VFP_REGS_SIZE;
+ iov.iov_len = ARM_VFP3_REGS_SIZE;
ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov);
}
else
@@ -398,7 +396,7 @@ store_vfp_regs (const struct regcache *regcache)
struct iovec iov;
iov.iov_base = regbuf;
- iov.iov_len = VFP_REGS_SIZE;
+ iov.iov_len = ARM_VFP3_REGS_SIZE;
ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iov);
}
else
@@ -574,7 +572,7 @@ arm_linux_nat_target::read_description ()
registers. Support was added in 2.6.30. */
pid = inferior_ptid.lwp ();
errno = 0;
- buf = (char *) alloca (VFP_REGS_SIZE);
+ buf = (char *) alloca (ARM_VFP3_REGS_SIZE);
if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0
&& errno == EIO)
result = NULL;
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 529dd68801..fd831e4ad2 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -8794,25 +8794,16 @@ arm_register_g_packet_guesses (struct gdbarch *gdbarch)
cater for remote targets whose register set layout is the
same as the FPA layout. */
register_remote_g_packet_guess (gdbarch,
- /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
- (16 * ARM_INT_REGISTER_SIZE)
- + (8 * ARM_FP_REGISTER_SIZE)
- + (2 * ARM_INT_REGISTER_SIZE),
+ ARM_CORE_REGS_SIZE + ARM_FP_REGS_SIZE,
tdesc_arm_with_m_fpa_layout);
/* The regular M-profile layout. */
- register_remote_g_packet_guess (gdbarch,
- /* r0-r12,sp,lr,pc; xpsr */
- (16 * ARM_INT_REGISTER_SIZE)
- + ARM_INT_REGISTER_SIZE,
+ register_remote_g_packet_guess (gdbarch, ARM_CORE_REGS_SIZE,
tdesc_arm_with_m);
/* M-profile plus M4F VFP. */
register_remote_g_packet_guess (gdbarch,
- /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
- (16 * ARM_INT_REGISTER_SIZE)
- + (16 * ARM_VFP_REGISTER_SIZE)
- + (2 * ARM_INT_REGISTER_SIZE),
+ ARM_CORE_REGS_SIZE + ARM_VFP2_REGS_SIZE,
tdesc_arm_with_m_vfp_d16);
}
diff --git a/gdb/gdbserver/linux-aarch32-low.c b/gdb/gdbserver/linux-aarch32-low.c
index 051e614c65..a932373518 100644
--- a/gdb/gdbserver/linux-aarch32-low.c
+++ b/gdb/gdbserver/linux-aarch32-low.c
@@ -143,10 +143,10 @@ arm_store_vfpregset (struct regcache *regcache, const void *buf)
/* Register sets with using PTRACE_GETREGSET. */
static struct regset_info aarch32_regsets[] = {
- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, 18 * 4,
- GENERAL_REGS,
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
+ ARM_CORE_REGS_SIZE + ARM_INT_REGISTER_SIZE, GENERAL_REGS,
arm_fill_gregset, arm_store_gregset },
- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_VFP, 32 * 8 + 4,
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_VFP, ARM_VFP3_REGS_SIZE,
EXTENDED_REGS,
arm_fill_vfpregset, arm_store_vfpregset },
NULL_REGSET
diff --git a/gdb/gdbserver/linux-arm-low.c b/gdb/gdbserver/linux-arm-low.c
index ff72a489cb..b323b19078 100644
--- a/gdb/gdbserver/linux-arm-low.c
+++ b/gdb/gdbserver/linux-arm-low.c
@@ -876,7 +876,7 @@ arm_read_description (void)
/* Now make sure that the kernel supports reading these
registers. Support was added in 2.6.30. */
errno = 0;
- buf = (char *) xmalloc (32 * 8 + 4);
+ buf = (char *) xmalloc (ARM_VFP3_REGS_SIZE);
if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0
&& errno == EIO)
result = tdesc_arm;
@@ -973,14 +973,12 @@ arm_get_syscall_trapinfo (struct regcache *regcache, int *sysno)
/* Register sets without using PTRACE_GETREGSET. */
static struct regset_info arm_regsets[] = {
- { PTRACE_GETREGS, PTRACE_SETREGS, 0, 18 * 4,
- GENERAL_REGS,
+ { PTRACE_GETREGS, PTRACE_SETREGS, 0,
+ ARM_CORE_REGS_SIZE + ARM_INT_REGISTER_SIZE, GENERAL_REGS,
arm_fill_gregset, arm_store_gregset },
- { PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, 16 * 8 + 6 * 4,
- EXTENDED_REGS,
+ { PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, IWMMXT_REGS_SIZE, EXTENDED_REGS,
arm_fill_wmmxregset, arm_store_wmmxregset },
- { PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, 32 * 8 + 4,
- EXTENDED_REGS,
+ { PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, ARM_VFP3_REGS_SIZE, EXTENDED_REGS,
arm_fill_vfpregset, arm_store_vfpregset },
NULL_REGSET
};
--
2.20.1 (Apple Git-117)
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/3] Arm/AArch64: Split DISPLACED_MODIFIED_INSNS name clash
@ 2019-06-26 13:19 Alan Hayward
2019-06-26 13:19 ` [PATCH 3/3] Arm/AArch64: Use a single set of Arm register set size defines Alan Hayward
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Alan Hayward @ 2019-06-26 13:19 UTC (permalink / raw)
To: gdb-patches; +Cc: nd, Alan Hayward
Both targets define DISPLACED_MODIFIED_INSNS, each with different values.
Add ARM_ and AARCH64_ to the start of the name to prevent confusion.
No functionality changes.
gdb/ChangeLog:
2019-06-26 Alan Hayward <alan.hayward@arm.com>
* aarch64-linux-tdep.c (aarch64_linux_init_abi): Use
AARCH64_DISPLACED_MODIFIED_INSNS.
* aarch64-tdep.c (struct aarch64_displaced_step_data)
(aarch64_displaced_step_copy_insn): Likewise.
* aarch64-tdep.h (DISPLACED_MODIFIED_INSNS): Rename from..
(AARCH64_DISPLACED_MODIFIED_INSNS): ...to this.
* arm-linux-tdep.c (arm_linux_cleanup_svc): Use
ARM_DISPLACED_MODIFIED_INSNS.
* arm-tdep.c (arm_gdbarch_init): Likewise.
* arm-tdep.h (DISPLACED_MODIFIED_INSNS): Rename from..
(ARM_DISPLACED_MODIFIED_INSNS): ...to this.
(struct arm_displaced_step_closure): Use
ARM_DISPLACED_MODIFIED_INSNS.
---
gdb/aarch64-linux-tdep.c | 2 +-
gdb/aarch64-tdep.c | 4 ++--
gdb/aarch64-tdep.h | 2 +-
gdb/arm-linux-tdep.c | 2 +-
gdb/arm-tdep.c | 2 +-
gdb/arm-tdep.h | 4 ++--
6 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c
index 7f2193f2fa..831e62fb86 100644
--- a/gdb/aarch64-linux-tdep.c
+++ b/gdb/aarch64-linux-tdep.c
@@ -1658,7 +1658,7 @@ aarch64_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
set_gdbarch_get_syscall_number (gdbarch, aarch64_linux_get_syscall_number);
/* Displaced stepping. */
- set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
+ set_gdbarch_max_insn_length (gdbarch, 4 * AARCH64_DISPLACED_MODIFIED_INSNS);
set_gdbarch_displaced_step_copy_insn (gdbarch,
aarch64_displaced_step_copy_insn);
set_gdbarch_displaced_step_fixup (gdbarch, aarch64_displaced_step_fixup);
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 96ebce4c35..f33cee6622 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -2756,7 +2756,7 @@ struct aarch64_displaced_step_data
/* The address where the instruction will be executed at. */
CORE_ADDR new_addr;
/* Buffer of instructions to be copied to NEW_ADDR to execute. */
- uint32_t insn_buf[DISPLACED_MODIFIED_INSNS];
+ uint32_t insn_buf[AARCH64_DISPLACED_MODIFIED_INSNS];
/* Number of instructions in INSN_BUF. */
unsigned insn_count;
/* Registers when doing displaced stepping. */
@@ -3000,7 +3000,7 @@ aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
dsd.insn_count = 0;
aarch64_relocate_instruction (insn, &visitor,
(struct aarch64_insn_data *) &dsd);
- gdb_assert (dsd.insn_count <= DISPLACED_MODIFIED_INSNS);
+ gdb_assert (dsd.insn_count <= AARCH64_DISPLACED_MODIFIED_INSNS);
if (dsd.insn_count != 0)
{
diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h
index f73392d59b..e4b045b599 100644
--- a/gdb/aarch64-tdep.h
+++ b/gdb/aarch64-tdep.h
@@ -56,7 +56,7 @@ struct regset;
/* The maximum number of modified instructions generated for one
single-stepped instruction. */
-#define DISPLACED_MODIFIED_INSNS 1
+#define AARCH64_DISPLACED_MODIFIED_INSNS 1
/* Target-dependent structure in gdbarch. */
struct gdbarch_tdep
diff --git a/gdb/arm-linux-tdep.c b/gdb/arm-linux-tdep.c
index a5ad06434c..8c0c0585d7 100644
--- a/gdb/arm-linux-tdep.c
+++ b/gdb/arm-linux-tdep.c
@@ -954,7 +954,7 @@ arm_linux_cleanup_svc (struct gdbarch *gdbarch,
within_scratch = (apparent_pc >= dsc->scratch_base
&& apparent_pc < (dsc->scratch_base
- + DISPLACED_MODIFIED_INSNS * 4 + 4));
+ + ARM_DISPLACED_MODIFIED_INSNS * 4 + 4));
if (debug_displaced)
{
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 2ba77e207d..5b1f360f9f 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -9271,7 +9271,7 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
/* Note: for displaced stepping, this includes the breakpoint, and one word
of additional scratch space. This setting isn't used for anything beside
displaced stepping at present. */
- set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
+ set_gdbarch_max_insn_length (gdbarch, 4 * ARM_DISPLACED_MODIFIED_INSNS);
/* This should be low enough for everything. */
tdep->lowest_pc = 0x20;
diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h
index 23dd40ea8b..7da11656c2 100644
--- a/gdb/arm-tdep.h
+++ b/gdb/arm-tdep.h
@@ -152,7 +152,7 @@ struct gdbarch_tdep
/* The maximum number of modified instructions generated for one single-stepped
instruction, including the breakpoint (usually at the end of the instruction
sequence) and any scratch words, etc. */
-#define DISPLACED_MODIFIED_INSNS 8
+#define ARM_DISPLACED_MODIFIED_INSNS 8
struct arm_displaced_step_closure : public displaced_step_closure
{
@@ -215,7 +215,7 @@ struct arm_displaced_step_closure : public displaced_step_closure
- ARM instruction occupies one slot,
- Thumb 16 bit instruction occupies one slot,
- Thumb 32-bit instruction occupies *two* slots, one part for each. */
- unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
+ unsigned long modinsn[ARM_DISPLACED_MODIFIED_INSNS];
int numinsns;
CORE_ADDR insn_addr;
CORE_ADDR scratch_base;
--
2.20.1 (Apple Git-117)
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/3] Arm: Prefix register sizes with ARM_
2019-06-26 13:19 ` [PATCH 2/3] Arm: Prefix register sizes with ARM_ Alan Hayward
@ 2019-06-27 15:53 ` Alan Hayward
0 siblings, 0 replies; 5+ messages in thread
From: Alan Hayward @ 2019-06-27 15:53 UTC (permalink / raw)
To: gdb-patches; +Cc: nd
> On 26 Jun 2019, at 14:19, Alan Hayward <Alan.Hayward@arm.com> wrote:
>
> Add ARM_ to the front of INT_REGISTER_SIZE, FP_REGISTER_SIZE and
> ARM_VFP_REGISTER_SIZE to make it obvious they are for the Arm target.
> Move the defines to arch/arm.h
>
> No functionality changes.
>
The above patch missed out changes for arm-nbsp-tdep and arm-wince-tdep.
The patch below is adds them in. Identical otherwise.
Parts 1/3 and 3/3 are still good.
Alan.
Arm: Prefix register sizes with ARM_
Add ARM_ to the front of INT_REGISTER_SIZE, FP_REGISTER_SIZE and
ARM_VFP_REGISTER_SIZE to make it obvious they are for the Arm target.
Move the defines to arch/arm.h
No functionality changes.
gdb/ChangeLog:
2019-06-26 Alan Hayward <alan.hayward@arm.com>
* arch/arm-get-next-pcs.c (thumb_get_next_pcs_raw): Use ARM_
defines.
* arch/arm-linux.c (arm_linux_sigreturn_next_pc_offset): Likewise.
* arch/arm.h (INT_REGISTER_SIZE) Rename from...
(ARM_INT_REGISTER_SIZE): ...to this.
(ARM_FP_REGISTER_SIZE) (ARM_VFP_REGISTER_SIZE): Add define.
* arm-linux-tdep.c (ARM_LINUX_JB_ELEMENT_SIZE)
(ARM_LINUX_SIZEOF_GREGSET, arm_linux_supply_gregset)
(arm_linux_collect_gregset, supply_nwfpe_register)
(collect_nwfpe_register, arm_linux_collect_nwfpe): Use ARM_
defines.
* arm-linux-tdep.h (ARM_LINUX_SIZEOF_NWFPE, NWFPE_FPSR_OFFSET)
(NWFPE_FPCR_OFFSET, NWFPE_TAGS_OFFSET): Likewise
* arm-nbsd-tdep.c (ARM_NBSD_JB_ELEMENT_SIZE): Likewise.
* arm-tdep.c (arm_push_dummy_call, arm_extract_return_value)
(arm_return_in_memory, arm_store_return_value)
(arm_get_longjmp_target, arm_register_g_packet_guesses)
(arm_record_ld_st_multiple): Likewise.
* arm-tdep.h (FP_REGISTER_SIZE, VFP_REGISTER_SIZE): Remove.
* arm-wince-tdep.c (ARM_WINCE_JB_ELEMENT_SIZE): Use ARM_ defines.
diff --git a/gdb/arch/arm-get-next-pcs.c b/gdb/arch/arm-get-next-pcs.c
index 06b3f2c992..00c7064d8b 100644
--- a/gdb/arch/arm-get-next-pcs.c
+++ b/gdb/arch/arm-get-next-pcs.c
@@ -408,7 +408,8 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
/* Fetch the saved PC from the stack. It's stored above
all of the other registers. */
- unsigned long offset = bitcount (bits (inst1, 0, 7)) * INT_REGISTER_SIZE;
+ unsigned long offset = bitcount (bits (inst1, 0, 7))
+ * ARM_INT_REGISTER_SIZE;
sp = regcache_raw_get_unsigned (regcache, ARM_SP_REGNUM);
nextpc = self->ops->read_mem_uint (sp + offset, 4, byte_order);
}
diff --git a/gdb/arch/arm-linux.c b/gdb/arch/arm-linux.c
index a399f3e71c..180228fe89 100644
--- a/gdb/arch/arm-linux.c
+++ b/gdb/arch/arm-linux.c
@@ -53,7 +53,7 @@ arm_linux_sigreturn_next_pc_offset (unsigned long sp,
r0_offset += ARM_UCONTEXT_SIGCONTEXT + ARM_SIGCONTEXT_R0;
}
- pc_offset = r0_offset + INT_REGISTER_SIZE * ARM_PC_REGNUM;
+ pc_offset = r0_offset + ARM_INT_REGISTER_SIZE * ARM_PC_REGNUM;
return pc_offset;
}
diff --git a/gdb/arch/arm.h b/gdb/arch/arm.h
index c1785425e8..0ebbf89a9c 100644
--- a/gdb/arch/arm.h
+++ b/gdb/arch/arm.h
@@ -93,8 +93,12 @@ enum arm_breakpoint_kinds
#define XPSR_T 0x01000000
-/* Size of integer registers. */
-#define INT_REGISTER_SIZE 4
+/* Size of registers. */
+
+#define ARM_INT_REGISTER_SIZE 4
+/* IEEE extended doubles are 80 bits. DWORD aligned they use 96 bits. */
+#define ARM_FP_REGISTER_SIZE 12
+#define ARM_VFP_REGISTER_SIZE 8
/* Addresses for calling Thumb functions have the bit 0 set.
Here are some macros to test, set, or clear bit 0 of addresses. */
diff --git a/gdb/arm-linux-tdep.c b/gdb/arm-linux-tdep.c
index 8c0c0585d7..d846749e0b 100644
--- a/gdb/arm-linux-tdep.c
+++ b/gdb/arm-linux-tdep.c
@@ -103,7 +103,7 @@ static const gdb_byte arm_linux_thumb2_le_breakpoint[] = { 0xf0, 0xf7, 0x00, 0xa
SoftVFP or VFP (which implies EABI) then the PC is at offset 9 in the
buffer. This is also true for the SoftFPA model. However, for the FPA
model the PC is at offset 21 in the buffer. */
-#define ARM_LINUX_JB_ELEMENT_SIZE INT_REGISTER_SIZE
+#define ARM_LINUX_JB_ELEMENT_SIZE ARM_INT_REGISTER_SIZE
#define ARM_LINUX_JB_PC_FPA 21
#define ARM_LINUX_JB_PC_EABI 9
@@ -471,7 +471,7 @@ static struct tramp_frame arm_kernel_linux_restart_syscall_tramp_frame = {
/* Core file and register set support. */
-#define ARM_LINUX_SIZEOF_GREGSET (18 * INT_REGISTER_SIZE)
+#define ARM_LINUX_SIZEOF_GREGSET (18 * ARM_INT_REGISTER_SIZE)
void
arm_linux_supply_gregset (const struct regset *regset,
@@ -483,29 +483,30 @@ arm_linux_supply_gregset (const struct regset *regset,
const gdb_byte *gregs = (const gdb_byte *) gregs_buf;
int regno;
CORE_ADDR reg_pc;
- gdb_byte pc_buf[INT_REGISTER_SIZE];
+ gdb_byte pc_buf[ARM_INT_REGISTER_SIZE];
for (regno = ARM_A1_REGNUM; regno < ARM_PC_REGNUM; regno++)
if (regnum == -1 || regnum == regno)
- regcache->raw_supply (regno, gregs + INT_REGISTER_SIZE * regno);
+ regcache->raw_supply (regno, gregs + ARM_INT_REGISTER_SIZE * regno);
if (regnum == ARM_PS_REGNUM || regnum == -1)
{
if (arm_apcs_32)
regcache->raw_supply (ARM_PS_REGNUM,
- gregs + INT_REGISTER_SIZE * ARM_CPSR_GREGNUM);
+ gregs + ARM_INT_REGISTER_SIZE * ARM_CPSR_GREGNUM);
else
regcache->raw_supply (ARM_PS_REGNUM,
- gregs + INT_REGISTER_SIZE * ARM_PC_REGNUM);
+ gregs + ARM_INT_REGISTER_SIZE * ARM_PC_REGNUM);
}
if (regnum == ARM_PC_REGNUM || regnum == -1)
{
- reg_pc = extract_unsigned_integer (gregs
- + INT_REGISTER_SIZE * ARM_PC_REGNUM,
- INT_REGISTER_SIZE, byte_order);
+ reg_pc = extract_unsigned_integer (
+ gregs + ARM_INT_REGISTER_SIZE * ARM_PC_REGNUM,
+ ARM_INT_REGISTER_SIZE, byte_order);
reg_pc = gdbarch_addr_bits_remove (gdbarch, reg_pc);
- store_unsigned_integer (pc_buf, INT_REGISTER_SIZE, byte_order, reg_pc);
+ store_unsigned_integer (pc_buf, ARM_INT_REGISTER_SIZE, byte_order,
+ reg_pc);
regcache->raw_supply (ARM_PC_REGNUM, pc_buf);
}
}
@@ -521,21 +522,21 @@ arm_linux_collect_gregset (const struct regset *regset,
for (regno = ARM_A1_REGNUM; regno < ARM_PC_REGNUM; regno++)
if (regnum == -1 || regnum == regno)
regcache->raw_collect (regno,
- gregs + INT_REGISTER_SIZE * regno);
+ gregs + ARM_INT_REGISTER_SIZE * regno);
if (regnum == ARM_PS_REGNUM || regnum == -1)
{
if (arm_apcs_32)
regcache->raw_collect (ARM_PS_REGNUM,
- gregs + INT_REGISTER_SIZE * ARM_CPSR_GREGNUM);
+ gregs + ARM_INT_REGISTER_SIZE * ARM_CPSR_GREGNUM);
else
regcache->raw_collect (ARM_PS_REGNUM,
- gregs + INT_REGISTER_SIZE * ARM_PC_REGNUM);
+ gregs + ARM_INT_REGISTER_SIZE * ARM_PC_REGNUM);
}
if (regnum == ARM_PC_REGNUM || regnum == -1)
regcache->raw_collect (ARM_PC_REGNUM,
- gregs + INT_REGISTER_SIZE * ARM_PC_REGNUM);
+ gregs + ARM_INT_REGISTER_SIZE * ARM_PC_REGNUM);
}
/* Support for register format used by the NWFPE FPA emulator. */
@@ -551,11 +552,11 @@ supply_nwfpe_register (struct regcache *regcache, int regno,
{
const gdb_byte *reg_data;
gdb_byte reg_tag;
- gdb_byte buf[FP_REGISTER_SIZE];
+ gdb_byte buf[ARM_FP_REGISTER_SIZE];
- reg_data = regs + (regno - ARM_F0_REGNUM) * FP_REGISTER_SIZE;
+ reg_data = regs + (regno - ARM_F0_REGNUM) * ARM_FP_REGISTER_SIZE;
reg_tag = regs[(regno - ARM_F0_REGNUM) + NWFPE_TAGS_OFFSET];
- memset (buf, 0, FP_REGISTER_SIZE);
+ memset (buf, 0, ARM_FP_REGISTER_SIZE);
switch (reg_tag)
{
@@ -586,7 +587,7 @@ collect_nwfpe_register (const struct regcache *regcache, int regno,
{
gdb_byte *reg_data;
gdb_byte reg_tag;
- gdb_byte buf[FP_REGISTER_SIZE];
+ gdb_byte buf[ARM_FP_REGISTER_SIZE];
regcache->raw_collect (regno, buf);
@@ -595,7 +596,7 @@ collect_nwfpe_register (const struct regcache *regcache, int regno,
from the native file to the target file. But this doesn't
always make sense. */
- reg_data = regs + (regno - ARM_F0_REGNUM) * FP_REGISTER_SIZE;
+ reg_data = regs + (regno - ARM_F0_REGNUM) * ARM_FP_REGISTER_SIZE;
reg_tag = regs[(regno - ARM_F0_REGNUM) + NWFPE_TAGS_OFFSET];
switch (reg_tag)
@@ -648,7 +649,7 @@ arm_linux_collect_nwfpe (const struct regset *regset,
if (regnum == ARM_FPS_REGNUM || regnum == -1)
regcache->raw_collect (ARM_FPS_REGNUM,
- regs + INT_REGISTER_SIZE * ARM_FPS_REGNUM);
+ regs + ARM_INT_REGISTER_SIZE * ARM_FPS_REGNUM);
}
/* Support VFP register format. */
diff --git a/gdb/arm-linux-tdep.h b/gdb/arm-linux-tdep.h
index 8f43048148..a17bf4e3e4 100644
--- a/gdb/arm-linux-tdep.h
+++ b/gdb/arm-linux-tdep.h
@@ -23,9 +23,9 @@
struct regset;
struct regcache;
-#define ARM_LINUX_SIZEOF_NWFPE (8 * FP_REGISTER_SIZE \
- + 2 * INT_REGISTER_SIZE \
- + 8 + INT_REGISTER_SIZE)
+#define ARM_LINUX_SIZEOF_NWFPE (8 * ARM_FP_REGISTER_SIZE \
+ + 2 * ARM_INT_REGISTER_SIZE \
+ + 8 + ARM_INT_REGISTER_SIZE)
/* Support for register format used by the NWFPE FPA emulator. Each
register takes three words, where either the first one, two, or
@@ -35,9 +35,9 @@ struct regcache;
final word flag which indicates whether NWFPE has been
initialized. */
-#define NWFPE_FPSR_OFFSET (8 * FP_REGISTER_SIZE)
-#define NWFPE_FPCR_OFFSET (NWFPE_FPSR_OFFSET + INT_REGISTER_SIZE)
-#define NWFPE_TAGS_OFFSET (NWFPE_FPCR_OFFSET + INT_REGISTER_SIZE)
+#define NWFPE_FPSR_OFFSET (8 * ARM_FP_REGISTER_SIZE)
+#define NWFPE_FPCR_OFFSET (NWFPE_FPSR_OFFSET + ARM_INT_REGISTER_SIZE)
+#define NWFPE_TAGS_OFFSET (NWFPE_FPCR_OFFSET + ARM_INT_REGISTER_SIZE)
#define NWFPE_INITFLAG_OFFSET (NWFPE_TAGS_OFFSET + 8)
void arm_linux_supply_gregset (const struct regset *regset,
diff --git a/gdb/arm-nbsd-tdep.c b/gdb/arm-nbsd-tdep.c
index 6b78230092..804d02aa9a 100644
--- a/gdb/arm-nbsd-tdep.c
+++ b/gdb/arm-nbsd-tdep.c
@@ -26,7 +26,7 @@
/* Description of the longjmp buffer. */
#define ARM_NBSD_JB_PC 24
-#define ARM_NBSD_JB_ELEMENT_SIZE INT_REGISTER_SIZE
+#define ARM_NBSD_JB_ELEMENT_SIZE ARM_INT_REGISTER_SIZE
/* For compatibility with previous implemenations of GDB on arm/NetBSD,
override the default little-endian breakpoint. */
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 5b1f360f9f..529dd68801 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -3696,18 +3696,19 @@ arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
align = type_align (arg_type);
/* Round alignment up to a whole number of words. */
- align = (align + INT_REGISTER_SIZE - 1) & ~(INT_REGISTER_SIZE - 1);
+ align = (align + ARM_INT_REGISTER_SIZE - 1)
+ & ~(ARM_INT_REGISTER_SIZE - 1);
/* Different ABIs have different maximum alignments. */
if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_APCS)
{
/* The APCS ABI only requires word alignment. */
- align = INT_REGISTER_SIZE;
+ align = ARM_INT_REGISTER_SIZE;
}
else
{
/* The AAPCS requires at most doubleword alignment. */
- if (align > INT_REGISTER_SIZE * 2)
- align = INT_REGISTER_SIZE * 2;
+ if (align > ARM_INT_REGISTER_SIZE * 2)
+ align = ARM_INT_REGISTER_SIZE * 2;
}
if (use_vfp_abi
@@ -3772,14 +3773,14 @@ arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
/* Push stack padding for dowubleword alignment. */
if (nstack & (align - 1))
{
- si = push_stack_item (si, val, INT_REGISTER_SIZE);
- nstack += INT_REGISTER_SIZE;
+ si = push_stack_item (si, val, ARM_INT_REGISTER_SIZE);
+ nstack += ARM_INT_REGISTER_SIZE;
}
/* Doubleword aligned quantities must go in even register pairs. */
if (may_use_core_reg
&& argreg <= ARM_LAST_ARG_REGNUM
- && align > INT_REGISTER_SIZE
+ && align > ARM_INT_REGISTER_SIZE
&& argreg & 1)
argreg++;
@@ -3805,7 +3806,8 @@ arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
registers and stack. */
while (len > 0)
{
- int partial_len = len < INT_REGISTER_SIZE ? len : INT_REGISTER_SIZE;
+ int partial_len = len < ARM_INT_REGISTER_SIZE
+ ? len : ARM_INT_REGISTER_SIZE;
CORE_ADDR regval
= extract_unsigned_integer (val, partial_len, byte_order);
@@ -3814,19 +3816,19 @@ arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
/* The argument is being passed in a general purpose
register. */
if (byte_order == BFD_ENDIAN_BIG)
- regval <<= (INT_REGISTER_SIZE - partial_len) * 8;
+ regval <<= (ARM_INT_REGISTER_SIZE - partial_len) * 8;
if (arm_debug)
fprintf_unfiltered (gdb_stdlog, "arg %d in %s = 0x%s\n",
argnum,
gdbarch_register_name
(gdbarch, argreg),
- phex (regval, INT_REGISTER_SIZE));
+ phex (regval, ARM_INT_REGISTER_SIZE));
regcache_cooked_write_unsigned (regcache, argreg, regval);
argreg++;
}
else
{
- gdb_byte buf[INT_REGISTER_SIZE];
+ gdb_byte buf[ARM_INT_REGISTER_SIZE];
memset (buf, 0, sizeof (buf));
store_unsigned_integer (buf, partial_len, byte_order, regval);
@@ -3835,8 +3837,8 @@ arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
if (arm_debug)
fprintf_unfiltered (gdb_stdlog, "arg %d @ sp + %d\n",
argnum, nstack);
- si = push_stack_item (si, buf, INT_REGISTER_SIZE);
- nstack += INT_REGISTER_SIZE;
+ si = push_stack_item (si, buf, ARM_INT_REGISTER_SIZE);
+ nstack += ARM_INT_REGISTER_SIZE;
}
len -= partial_len;
@@ -7842,7 +7844,7 @@ arm_extract_return_value (struct type *type, struct regcache *regs,
/* The value is in register F0 in internal format. We need to
extract the raw value and then convert it to the desired
internal type. */
- bfd_byte tmpbuf[FP_REGISTER_SIZE];
+ bfd_byte tmpbuf[ARM_FP_REGISTER_SIZE];
regs->cooked_read (ARM_F0_REGNUM, tmpbuf);
target_float_convert (tmpbuf, arm_ext_type (gdbarch),
@@ -7857,7 +7859,8 @@ arm_extract_return_value (struct type *type, struct regcache *regs,
case ARM_FLOAT_VFP:
regs->cooked_read (ARM_A1_REGNUM, valbuf);
if (TYPE_LENGTH (type) > 4)
- regs->cooked_read (ARM_A1_REGNUM + 1, valbuf + INT_REGISTER_SIZE);
+ regs->cooked_read (ARM_A1_REGNUM + 1,
+ valbuf + ARM_INT_REGISTER_SIZE);
break;
default:
@@ -7887,11 +7890,11 @@ arm_extract_return_value (struct type *type, struct regcache *regs,
anything special for small big-endian values. */
regcache_cooked_read_unsigned (regs, regno++, &tmp);
store_unsigned_integer (valbuf,
- (len > INT_REGISTER_SIZE
- ? INT_REGISTER_SIZE : len),
+ (len > ARM_INT_REGISTER_SIZE
+ ? ARM_INT_REGISTER_SIZE : len),
byte_order, tmp);
- len -= INT_REGISTER_SIZE;
- valbuf += INT_REGISTER_SIZE;
+ len -= ARM_INT_REGISTER_SIZE;
+ valbuf += ARM_INT_REGISTER_SIZE;
}
}
else
@@ -7901,15 +7904,15 @@ arm_extract_return_value (struct type *type, struct regcache *regs,
registers with 32-bit load instruction(s). */
int len = TYPE_LENGTH (type);
int regno = ARM_A1_REGNUM;
- bfd_byte tmpbuf[INT_REGISTER_SIZE];
+ bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE];
while (len > 0)
{
regs->cooked_read (regno++, tmpbuf);
memcpy (valbuf, tmpbuf,
- len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
- len -= INT_REGISTER_SIZE;
- valbuf += INT_REGISTER_SIZE;
+ len > ARM_INT_REGISTER_SIZE ? ARM_INT_REGISTER_SIZE : len);
+ len -= ARM_INT_REGISTER_SIZE;
+ valbuf += ARM_INT_REGISTER_SIZE;
}
}
}
@@ -7944,7 +7947,7 @@ arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
{
/* The AAPCS says all aggregates not larger than a word are returned
in a register. */
- if (TYPE_LENGTH (type) <= INT_REGISTER_SIZE)
+ if (TYPE_LENGTH (type) <= ARM_INT_REGISTER_SIZE)
return 0;
return 1;
@@ -7955,12 +7958,12 @@ arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
/* All aggregate types that won't fit in a register must be returned
in memory. */
- if (TYPE_LENGTH (type) > INT_REGISTER_SIZE)
+ if (TYPE_LENGTH (type) > ARM_INT_REGISTER_SIZE)
return 1;
/* In the ARM ABI, "integer" like aggregate types are returned in
registers. For an aggregate type to be integer like, its size
- must be less than or equal to INT_REGISTER_SIZE and the
+ must be less than or equal to ARM_INT_REGISTER_SIZE and the
offset of each addressable subfield must be zero. Note that bit
fields are not addressable, and all addressable subfields of
unions always start at offset zero.
@@ -7984,7 +7987,7 @@ arm_return_in_memory (struct gdbarch *gdbarch, struct type *type)
int i;
/* Need to check if this struct/union is "integer" like. For
this to be true, its size must be less than or equal to
- INT_REGISTER_SIZE and the offset of each addressable
+ ARM_INT_REGISTER_SIZE and the offset of each addressable
subfield must be zero. Note that bit fields are not
addressable, and unions always start at offset zero. If any
of the subfields is a floating point type, the struct/union
@@ -8043,7 +8046,7 @@ arm_store_return_value (struct type *type, struct regcache *regs,
if (TYPE_CODE (type) == TYPE_CODE_FLT)
{
- gdb_byte buf[FP_REGISTER_SIZE];
+ gdb_byte buf[ARM_FP_REGISTER_SIZE];
switch (gdbarch_tdep (gdbarch)->fp_model)
{
@@ -8060,7 +8063,8 @@ arm_store_return_value (struct type *type, struct regcache *regs,
case ARM_FLOAT_VFP:
regs->cooked_write (ARM_A1_REGNUM, valbuf);
if (TYPE_LENGTH (type) > 4)
- regs->cooked_write (ARM_A1_REGNUM + 1, valbuf + INT_REGISTER_SIZE);
+ regs->cooked_write (ARM_A1_REGNUM + 1,
+ valbuf + ARM_INT_REGISTER_SIZE);
break;
default:
@@ -8081,10 +8085,10 @@ arm_store_return_value (struct type *type, struct regcache *regs,
{
/* Values of one word or less are zero/sign-extended and
returned in r0. */
- bfd_byte tmpbuf[INT_REGISTER_SIZE];
+ bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE];
LONGEST val = unpack_long (type, valbuf);
- store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
+ store_signed_integer (tmpbuf, ARM_INT_REGISTER_SIZE, byte_order, val);
regs->cooked_write (ARM_A1_REGNUM, tmpbuf);
}
else
@@ -8098,8 +8102,8 @@ arm_store_return_value (struct type *type, struct regcache *regs,
while (len > 0)
{
regs->cooked_write (regno++, valbuf);
- len -= INT_REGISTER_SIZE;
- valbuf += INT_REGISTER_SIZE;
+ len -= ARM_INT_REGISTER_SIZE;
+ valbuf += ARM_INT_REGISTER_SIZE;
}
}
}
@@ -8110,15 +8114,15 @@ arm_store_return_value (struct type *type, struct regcache *regs,
registers with 32-bit load instruction(s). */
int len = TYPE_LENGTH (type);
int regno = ARM_A1_REGNUM;
- bfd_byte tmpbuf[INT_REGISTER_SIZE];
+ bfd_byte tmpbuf[ARM_INT_REGISTER_SIZE];
while (len > 0)
{
memcpy (tmpbuf, valbuf,
- len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
+ len > ARM_INT_REGISTER_SIZE ? ARM_INT_REGISTER_SIZE : len);
regs->cooked_write (regno++, tmpbuf);
- len -= INT_REGISTER_SIZE;
- valbuf += INT_REGISTER_SIZE;
+ len -= ARM_INT_REGISTER_SIZE;
+ valbuf += ARM_INT_REGISTER_SIZE;
}
}
}
@@ -8202,15 +8206,15 @@ arm_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR jb_addr;
- gdb_byte buf[INT_REGISTER_SIZE];
+ gdb_byte buf[ARM_INT_REGISTER_SIZE];
jb_addr = get_frame_register_unsigned (frame, ARM_A1_REGNUM);
if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf,
- INT_REGISTER_SIZE))
+ ARM_INT_REGISTER_SIZE))
return 0;
- *pc = extract_unsigned_integer (buf, INT_REGISTER_SIZE, byte_order);
+ *pc = extract_unsigned_integer (buf, ARM_INT_REGISTER_SIZE, byte_order);
return 1;
}
@@ -8791,24 +8795,24 @@ arm_register_g_packet_guesses (struct gdbarch *gdbarch)
same as the FPA layout. */
register_remote_g_packet_guess (gdbarch,
/* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */
- (16 * INT_REGISTER_SIZE)
- + (8 * FP_REGISTER_SIZE)
- + (2 * INT_REGISTER_SIZE),
+ (16 * ARM_INT_REGISTER_SIZE)
+ + (8 * ARM_FP_REGISTER_SIZE)
+ + (2 * ARM_INT_REGISTER_SIZE),
tdesc_arm_with_m_fpa_layout);
/* The regular M-profile layout. */
register_remote_g_packet_guess (gdbarch,
/* r0-r12,sp,lr,pc; xpsr */
- (16 * INT_REGISTER_SIZE)
- + INT_REGISTER_SIZE,
+ (16 * ARM_INT_REGISTER_SIZE)
+ + ARM_INT_REGISTER_SIZE,
tdesc_arm_with_m);
/* M-profile plus M4F VFP. */
register_remote_g_packet_guess (gdbarch,
/* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */
- (16 * INT_REGISTER_SIZE)
- + (16 * VFP_REGISTER_SIZE)
- + (2 * INT_REGISTER_SIZE),
+ (16 * ARM_INT_REGISTER_SIZE)
+ + (16 * ARM_VFP_REGISTER_SIZE)
+ + (2 * ARM_INT_REGISTER_SIZE),
tdesc_arm_with_m_vfp_d16);
}
@@ -10980,7 +10984,7 @@ arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
/* STMDA (STMED): Decrement after. */
case 0:
record_buf_mem[1] = (uint32_t) u_regval
- - register_count * INT_REGISTER_SIZE + 4;
+ - register_count * ARM_INT_REGISTER_SIZE + 4;
break;
/* STM (STMIA, STMEA): Increment after. */
case 1:
@@ -10989,18 +10993,18 @@ arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
/* STMDB (STMFD): Decrement before. */
case 2:
record_buf_mem[1] = (uint32_t) u_regval
- - register_count * INT_REGISTER_SIZE;
+ - register_count * ARM_INT_REGISTER_SIZE;
break;
/* STMIB (STMFA): Increment before. */
case 3:
- record_buf_mem[1] = (uint32_t) u_regval + INT_REGISTER_SIZE;
+ record_buf_mem[1] = (uint32_t) u_regval + ARM_INT_REGISTER_SIZE;
break;
default:
gdb_assert_not_reached ("no decoding pattern found");
break;
}
- record_buf_mem[0] = register_count * INT_REGISTER_SIZE;
+ record_buf_mem[0] = register_count * ARM_INT_REGISTER_SIZE;
arm_insn_r->mem_rec_count = 1;
/* If wback is true, also save the base register, which is going to be
diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h
index 7da11656c2..807849a5ff 100644
--- a/gdb/arm-tdep.h
+++ b/gdb/arm-tdep.h
@@ -32,15 +32,6 @@ struct gdb_get_next_pcs;
#include <vector>
-/* Say how long FP registers are. Used for documentation purposes and
- code readability in this header. IEEE extended doubles are 80
- bits. DWORD aligned they use 96 bits. */
-#define FP_REGISTER_SIZE 12
-
-/* Say how long VFP double precision registers are. Used for documentation
- purposes and code readability. These are fixed at 64 bits. */
-#define VFP_REGISTER_SIZE 8
-
/* Number of machine registers. The only define actually required
is gdbarch_num_regs. The other definitions are used for documentation
purposes and code readability. */
diff --git a/gdb/arm-wince-tdep.c b/gdb/arm-wince-tdep.c
index 6eae60e8a7..584eef9fed 100644
--- a/gdb/arm-wince-tdep.c
+++ b/gdb/arm-wince-tdep.c
@@ -32,7 +32,7 @@ static const gdb_byte arm_wince_le_breakpoint[] = { 0x10, 0x00, 0x00, 0xe6 };
static const gdb_byte arm_wince_thumb_le_breakpoint[] = { 0xfe, 0xdf };
/* Description of the longjmp buffer. */
-#define ARM_WINCE_JB_ELEMENT_SIZE INT_REGISTER_SIZE
+#define ARM_WINCE_JB_ELEMENT_SIZE ARM_INT_REGISTER_SIZE
#define ARM_WINCE_JB_PC 10
static CORE_ADDR
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/3] Arm/AArch64: Split DISPLACED_MODIFIED_INSNS name clash
2019-06-26 13:19 [PATCH 1/3] Arm/AArch64: Split DISPLACED_MODIFIED_INSNS name clash Alan Hayward
2019-06-26 13:19 ` [PATCH 3/3] Arm/AArch64: Use a single set of Arm register set size defines Alan Hayward
2019-06-26 13:19 ` [PATCH 2/3] Arm: Prefix register sizes with ARM_ Alan Hayward
@ 2019-07-04 11:54 ` Alan Hayward
2 siblings, 0 replies; 5+ messages in thread
From: Alan Hayward @ 2019-07-04 11:54 UTC (permalink / raw)
To: gdb-patches; +Cc: nd
I pushed this set.
> On 26 Jun 2019, at 14:19, Alan Hayward <Alan.Hayward@arm.com> wrote:
>
> Both targets define DISPLACED_MODIFIED_INSNS, each with different values.
> Add ARM_ and AARCH64_ to the start of the name to prevent confusion.
>
> No functionality changes.
>
> gdb/ChangeLog:
>
> 2019-06-26 Alan Hayward <alan.hayward@arm.com>
>
> * aarch64-linux-tdep.c (aarch64_linux_init_abi): Use
> AARCH64_DISPLACED_MODIFIED_INSNS.
> * aarch64-tdep.c (struct aarch64_displaced_step_data)
> (aarch64_displaced_step_copy_insn): Likewise.
> * aarch64-tdep.h (DISPLACED_MODIFIED_INSNS): Rename from..
> (AARCH64_DISPLACED_MODIFIED_INSNS): ...to this.
> * arm-linux-tdep.c (arm_linux_cleanup_svc): Use
> ARM_DISPLACED_MODIFIED_INSNS.
> * arm-tdep.c (arm_gdbarch_init): Likewise.
> * arm-tdep.h (DISPLACED_MODIFIED_INSNS): Rename from..
> (ARM_DISPLACED_MODIFIED_INSNS): ...to this.
> (struct arm_displaced_step_closure): Use
> ARM_DISPLACED_MODIFIED_INSNS.
> ---
> gdb/aarch64-linux-tdep.c | 2 +-
> gdb/aarch64-tdep.c | 4 ++--
> gdb/aarch64-tdep.h | 2 +-
> gdb/arm-linux-tdep.c | 2 +-
> gdb/arm-tdep.c | 2 +-
> gdb/arm-tdep.h | 4 ++--
> 6 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c
> index 7f2193f2fa..831e62fb86 100644
> --- a/gdb/aarch64-linux-tdep.c
> +++ b/gdb/aarch64-linux-tdep.c
> @@ -1658,7 +1658,7 @@ aarch64_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
> set_gdbarch_get_syscall_number (gdbarch, aarch64_linux_get_syscall_number);
>
> /* Displaced stepping. */
> - set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
> + set_gdbarch_max_insn_length (gdbarch, 4 * AARCH64_DISPLACED_MODIFIED_INSNS);
> set_gdbarch_displaced_step_copy_insn (gdbarch,
> aarch64_displaced_step_copy_insn);
> set_gdbarch_displaced_step_fixup (gdbarch, aarch64_displaced_step_fixup);
> diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
> index 96ebce4c35..f33cee6622 100644
> --- a/gdb/aarch64-tdep.c
> +++ b/gdb/aarch64-tdep.c
> @@ -2756,7 +2756,7 @@ struct aarch64_displaced_step_data
> /* The address where the instruction will be executed at. */
> CORE_ADDR new_addr;
> /* Buffer of instructions to be copied to NEW_ADDR to execute. */
> - uint32_t insn_buf[DISPLACED_MODIFIED_INSNS];
> + uint32_t insn_buf[AARCH64_DISPLACED_MODIFIED_INSNS];
> /* Number of instructions in INSN_BUF. */
> unsigned insn_count;
> /* Registers when doing displaced stepping. */
> @@ -3000,7 +3000,7 @@ aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
> dsd.insn_count = 0;
> aarch64_relocate_instruction (insn, &visitor,
> (struct aarch64_insn_data *) &dsd);
> - gdb_assert (dsd.insn_count <= DISPLACED_MODIFIED_INSNS);
> + gdb_assert (dsd.insn_count <= AARCH64_DISPLACED_MODIFIED_INSNS);
>
> if (dsd.insn_count != 0)
> {
> diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h
> index f73392d59b..e4b045b599 100644
> --- a/gdb/aarch64-tdep.h
> +++ b/gdb/aarch64-tdep.h
> @@ -56,7 +56,7 @@ struct regset;
>
> /* The maximum number of modified instructions generated for one
> single-stepped instruction. */
> -#define DISPLACED_MODIFIED_INSNS 1
> +#define AARCH64_DISPLACED_MODIFIED_INSNS 1
>
> /* Target-dependent structure in gdbarch. */
> struct gdbarch_tdep
> diff --git a/gdb/arm-linux-tdep.c b/gdb/arm-linux-tdep.c
> index a5ad06434c..8c0c0585d7 100644
> --- a/gdb/arm-linux-tdep.c
> +++ b/gdb/arm-linux-tdep.c
> @@ -954,7 +954,7 @@ arm_linux_cleanup_svc (struct gdbarch *gdbarch,
>
> within_scratch = (apparent_pc >= dsc->scratch_base
> && apparent_pc < (dsc->scratch_base
> - + DISPLACED_MODIFIED_INSNS * 4 + 4));
> + + ARM_DISPLACED_MODIFIED_INSNS * 4 + 4));
>
> if (debug_displaced)
> {
> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
> index 2ba77e207d..5b1f360f9f 100644
> --- a/gdb/arm-tdep.c
> +++ b/gdb/arm-tdep.c
> @@ -9271,7 +9271,7 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
> /* Note: for displaced stepping, this includes the breakpoint, and one word
> of additional scratch space. This setting isn't used for anything beside
> displaced stepping at present. */
> - set_gdbarch_max_insn_length (gdbarch, 4 * DISPLACED_MODIFIED_INSNS);
> + set_gdbarch_max_insn_length (gdbarch, 4 * ARM_DISPLACED_MODIFIED_INSNS);
>
> /* This should be low enough for everything. */
> tdep->lowest_pc = 0x20;
> diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h
> index 23dd40ea8b..7da11656c2 100644
> --- a/gdb/arm-tdep.h
> +++ b/gdb/arm-tdep.h
> @@ -152,7 +152,7 @@ struct gdbarch_tdep
> /* The maximum number of modified instructions generated for one single-stepped
> instruction, including the breakpoint (usually at the end of the instruction
> sequence) and any scratch words, etc. */
> -#define DISPLACED_MODIFIED_INSNS 8
> +#define ARM_DISPLACED_MODIFIED_INSNS 8
>
> struct arm_displaced_step_closure : public displaced_step_closure
> {
> @@ -215,7 +215,7 @@ struct arm_displaced_step_closure : public displaced_step_closure
> - ARM instruction occupies one slot,
> - Thumb 16 bit instruction occupies one slot,
> - Thumb 32-bit instruction occupies *two* slots, one part for each. */
> - unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
> + unsigned long modinsn[ARM_DISPLACED_MODIFIED_INSNS];
> int numinsns;
> CORE_ADDR insn_addr;
> CORE_ADDR scratch_base;
> --
> 2.20.1 (Apple Git-117)
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-07-04 11:54 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-26 13:19 [PATCH 1/3] Arm/AArch64: Split DISPLACED_MODIFIED_INSNS name clash Alan Hayward
2019-06-26 13:19 ` [PATCH 3/3] Arm/AArch64: Use a single set of Arm register set size defines Alan Hayward
2019-06-26 13:19 ` [PATCH 2/3] Arm: Prefix register sizes with ARM_ Alan Hayward
2019-06-27 15:53 ` Alan Hayward
2019-07-04 11:54 ` [PATCH 1/3] Arm/AArch64: Split DISPLACED_MODIFIED_INSNS name clash Alan Hayward
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