From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from hqnvemgate24.nvidia.com (hqnvemgate24.nvidia.com [216.228.121.143]) by sourceware.org (Postfix) with ESMTPS id C1760396E81A for ; Wed, 24 Jun 2020 01:29:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org C1760396E81A Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 23 Jun 2020 18:27:37 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 23 Jun 2020 18:29:09 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 23 Jun 2020 18:29:09 -0700 Received: from nvbus.nvidia.com (10.124.1.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 24 Jun 2020 01:29:09 +0000 From: Victor Collod To: Subject: [PATCH v3 7/7] amd64_analyze_prologue: use target_read_code instead of read_code Date: Tue, 23 Jun 2020 18:28:57 -0700 Message-ID: <20200624012857.31849-8-vcollod@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200624012857.31849-1-vcollod@nvidia.com> References: <0cc93067-1313-6434-4330-61a21736376f@simark.ca> <20200624012857.31849-1-vcollod@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 24 Jun 2020 01:29:11 -0000 Using target_read_code enables gracefuly handling error cases. 2020-06-23 Victor Collod * amd64-tdep.c (amd64_analyze_prologue): Use target_read_code instead of read_code. --- gdb/amd64-tdep.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c index 901733cf443..7f70c1d0d8d 100644 --- a/gdb/amd64-tdep.c +++ b/gdb/amd64-tdep.c @@ -2394,9 +2394,15 @@ amd64_analyze_prologue (struct gdbarch *gdbarch, else pc =3D amd64_analyze_stack_align (pc, current_pc, cache); =20 - read_code (pc, buf, 4); - /* Check for the `endbr64' instruction and skip it if found. */ - if (memcmp (buf, endbr64, sizeof (endbr64)) =3D=3D 0) + /* Try to read enough bytes to check for `endbr64'. */ + if (target_read_code (pc, buf, 4) !=3D 0) + { + /* If it fails, read just enough data for `pushq %rbp'. */ + if (target_read_code (pc, buf, 1) !=3D 0) + return pc; + } + /* If reading succeeded, check for the `endbr64' instruction and skip it= if found. */ + else if (memcmp (buf, endbr64, sizeof (endbr64)) =3D=3D 0) { pc +=3D sizeof (endbr64); /* If we went past the allowed bound, stop. */ @@ -2404,7 +2410,8 @@ amd64_analyze_prologue (struct gdbarch *gdbarch, return current_pc; =20 /* Update the code buffer, as pc changed. */ - read_code (pc, buf, 1); + if (target_read_code (pc, buf, 1) !=3D 0) + return pc; } =20 /* Stop right now if there's no `pushq %rbp'. */ @@ -2422,7 +2429,9 @@ amd64_analyze_prologue (struct gdbarch *gdbarch, if (pc >=3D current_pc) return current_pc; =20 - read_code (pc, buf, 3); + /* Try to read the code for the stack base move. */ + if (target_read_code (pc, buf, 3) !=3D 0) + return pc; =20 /* Check for `movq %rsp, %rbp'. */ if (memcmp (buf, mov_rsp_rbp_1, 3) =3D=3D 0 --=20 2.20.1