From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x542.google.com (mail-ed1-x542.google.com [IPv6:2a00:1450:4864:20::542]) by sourceware.org (Postfix) with ESMTPS id 27D253846416 for ; Wed, 5 Aug 2020 11:10:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 27D253846416 Received: by mail-ed1-x542.google.com with SMTP id c15so22536118edj.3 for ; Wed, 05 Aug 2020 04:10:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YfzwUSnE/WoGSLy8151VgEtz6JYkaz/T3elaUdncvEo=; b=Ph9Ya/PqBHMDwt7uRWrijlB2jYijrGU+/lnP69Q1BvpLtLI7qTDS8aN/yt69Bu8wqJ rSRWPUFlfx1LIKYj1u5XRjBR1rTnzUUO+Pmuu6zcdzuJ9aGEpOKDDRi0ffpsi+ZJN+ve /8q/pQDW9NqOq2UXSIu0F7xwjbvcgthzA9eMZR+3I70X3wl4JuMt3SgvsAA8cyuk/Wl6 sVrEJ7Tp5Q2jDfyrfWZZzv9Q9tQG6lS4BeL6vPFHrMkCOf25kFfvQM0maB2UfE6cAQ7T GyIsMM9l+UoPyZNnE2FIeIyxEHJPjx3/HULVBvz6COi8TtL5ZD14jsjulN762MrpxYMm by4g== X-Gm-Message-State: AOAM532B+Qk93gBgSuQ9BkUmnG19efgr4GnOj05/0znQRELvgv2ni0di gOtxrB9ub3ObP06J+tDwoWsNnscM9oM= X-Google-Smtp-Source: ABdhPJweOJdBLdiBndm54nOYTOVLZUC+6LPtuk7ZUghtOzS0mq8PeRx5FE8tP4kKIAz2sTXErg94PA== X-Received: by 2002:a50:ccd0:: with SMTP id b16mr2218639edj.148.1596625829926; Wed, 05 Aug 2020 04:10:29 -0700 (PDT) Received: from atlantis.home ([2a03:1b20:3:f011::6d]) by smtp.gmail.com with ESMTPSA id q17sm1361072ejd.20.2020.08.05.04.10.28 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Aug 2020 04:10:29 -0700 (PDT) From: Shahab Vahedi To: gdb-patches@sourceware.org Cc: Shahab Vahedi , Shahab Vahedi , Simon Marchi , Tom Tromey , Eli Zaretskii , Anton Kolesov , Francois Bedard Subject: [PATCH v6 3/4] arc: Add hardware loop detection Date: Wed, 5 Aug 2020 13:09:33 +0200 Message-Id: <20200805110934.6225-4-shahab.vahedi@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200805110934.6225-1-shahab.vahedi@gmail.com> References: <20200326125206.13120-1-shahab.vahedi@gmail.com> <20200805110934.6225-1-shahab.vahedi@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 05 Aug 2020 11:10:32 -0000 From: Shahab Vahedi For ARC there are registers that are not part of a required set in XML target descriptions by default, but are almost always present on ARC targets and are universally exposed by the ptrace interface. Hardware loop registers being one of them. LP_START and LP_END auxiliary registers are hardware loop start and end. Formally, they are optional, but it is hard to find an ARC configuration that doesn't have them. They are always present in processors that can run GNU/Linux. GDB needs to know about those registers to implement proper software single stepping, since they affect what instruction will be next. This commit adds the code to check for the existance of "lp_start" and "lp_end" in XML target descriptions. If they exist, then the function reports that the target supports hardware loops. gdb/ChangeLog: * arc-tdep.c (arc_check_for_hardware_loop): New. * arc-tdep.h (gdbarch_tdep): New field has_hw_loops. gdb/doc/ChangeLog: * gdb.texinfo (Synopsys ARC): Document LP_START, LP_END and BTA. --- gdb/arc-tdep.c | 39 +++++++++++++++++++++++++++++++++++---- gdb/arc-tdep.h | 3 +++ gdb/doc/gdb.texinfo | 11 +++++++++-- 3 files changed, 47 insertions(+), 6 deletions(-) diff --git a/gdb/arc-tdep.c b/gdb/arc-tdep.c index 9ef929191de..54f67a03818 100644 --- a/gdb/arc-tdep.c +++ b/gdb/arc-tdep.c @@ -2041,6 +2041,35 @@ arc_check_tdesc_feature (struct tdesc_arch_data *tdesc_data, return true; } +/* Check for the existance of "lp_start" and "lp_end" in target description. + If both are present, assume there is hardware loop support in the target. + This can be improved by looking into "lpc_size" field of "isa_config" + auxiliary register. */ + +static bool +arc_check_for_hw_loops (const struct target_desc *tdesc, + struct tdesc_arch_data *data) +{ + const auto feature_aux = tdesc_find_feature (tdesc, ARC_AUX_FEATURE_NAME); + const auto aux_regset = determine_aux_reg_feature_set (); + + if (feature_aux == nullptr) + return false; + + bool hw_loop_p = false; + const auto lp_start_name = + aux_regset->registers[ARC_LP_START_REGNUM - ARC_FIRST_AUX_REGNUM].names[0]; + const auto lp_end_name = + aux_regset->registers[ARC_LP_END_REGNUM - ARC_FIRST_AUX_REGNUM].names[0]; + + hw_loop_p = tdesc_numbered_register (feature_aux, data, + ARC_LP_START_REGNUM, lp_start_name); + hw_loop_p &= tdesc_numbered_register (feature_aux, data, + ARC_LP_END_REGNUM, lp_end_name); + + return hw_loop_p; +} + /* Initialize target description for the ARC. Returns true if input TDESC was valid and in this case it will assign TDESC @@ -2163,13 +2192,15 @@ arc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) debug_printf ("arc: Architecture initialization.\n"); if (!arc_tdesc_init (info, &tdesc, &tdesc_data)) - return NULL; + return nullptr; /* Allocate the ARC-private target-dependent information structure, and the GDB target-independent information structure. */ - struct gdbarch_tdep *tdep = XCNEW (struct gdbarch_tdep); + gdb::unique_xmalloc_ptr tdep + (XCNEW (struct gdbarch_tdep)); tdep->jb_pc = -1; /* No longjmp support by default. */ - struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep); + tdep->has_hw_loops = arc_check_for_hw_loops (tdesc, tdesc_data); + struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep.release ()); /* Data types. */ set_gdbarch_short_bit (gdbarch, 16); @@ -2250,7 +2281,7 @@ arc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) It can override functions set earlier. */ gdbarch_init_osabi (info, gdbarch); - if (tdep->jb_pc >= 0) + if (gdbarch_tdep (gdbarch)->jb_pc >= 0) set_gdbarch_get_longjmp_target (gdbarch, arc_get_longjmp_target); /* Disassembler options. Enforce CPU if it was specified in XML target diff --git a/gdb/arc-tdep.h b/gdb/arc-tdep.h index 5968abd4600..e752348a262 100644 --- a/gdb/arc-tdep.h +++ b/gdb/arc-tdep.h @@ -111,6 +111,9 @@ struct gdbarch_tdep /* Offset to PC value in jump buffer. If this is negative, longjmp support will be disabled. */ int jb_pc; + + /* Whether target has hardware (aka zero-delay) loops. */ + bool has_hw_loops; }; /* Utility functions used by other ARC-specific modules. */ diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index 8cfdb8ccc92..106f0306bbf 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -45238,8 +45238,15 @@ Extension core registers @samp{r32} through @samp{r59} are optional and their existence depends on the configuration. When debugging GNU/Linux applications, i.e. user space debugging, these core registers are not available. -The @samp{org.gnu.gdb.arc.aux} feature is required for all ARC targets. It -should at least contain @samp{pc} and @samp{status32} registers. +The @samp{org.gnu.gdb.arc.aux} feature is required for all ARC targets. Here +is the list of registers pertinent to this feature: + +@itemize @minus +@item +mandatory: @samp{pc} and @samp{status32}. +@item +optional: @samp{lp_start}, @samp{lp_end}, and @samp{bta}. +@end itemize @node ARM Features @subsection ARM Features -- 2.28.0