From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by sourceware.org (Postfix) with ESMTPS id E92D73861887 for ; Mon, 18 Jan 2021 14:15:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org E92D73861887 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=andrew.burgess@embecosm.com Received: by mail-wm1-x332.google.com with SMTP id m187so7484274wme.2 for ; Mon, 18 Jan 2021 06:15:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=W8NvfQO2N9XXGsc+t7tHOqJeVD7ql6VMgIakn+lwIAk=; b=VarmOlvhusbA+PwOId2yXswhWo9wBZMCL2rfvAaLxUBbK6BZx3GlTZI+QL9uUfdJ6S jWc8xRPQJ8RpOtV1tKoeEjpbuSnW2KryaZHp3sgdAPNGspiHErx/rDQgz3FCBnJTkOCi NkSJimRxYDwGlYaJZoy01HM9BBo3VH/E4PWsRATKsz+ssNNA+Jsl+gKsI7/E5LciWIjn QXOGD8cBnZsnOOdzeLDyP/0oBR6sC+QL6Kt9/wCLVhKSK/rwO/b6GBQIGEq+zOZOyIKh FgEZt9NvxsP3peBj/zAPbd1vGuY6FbUKSt30yo1kR7nIdlK86O9SP3ARLzf+4R9dbF0B jbDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=W8NvfQO2N9XXGsc+t7tHOqJeVD7ql6VMgIakn+lwIAk=; b=f6YqYBQ77H/BHgQGuF3OOOVGoEsf6Z1jx8wMHB9g2S7QwKA+Ik9R5+TfxtcrVirnMM eFctFJOhJNFR5X/8pnftN1sf4glk1T32p+W6U4NchEd+gc+FAp5i0h/FxwNzEvSjY7Mb kpP02+0FLVjGRGYoGQhebuDkCiLXw1K3KR06CevftNtJbozfnpHskpY4jwa8Jj1nnApC zJfnm2boegjTmubQVtwYR8C2UXqlFQno1mVZdASPC2Ac/b1iK0GHjfiu5i/+2prVu17i gRsHFeXkaUl0BufvXHAVOd5sCRHK2j96PIrn8ckRolhTQ+XGOGgySUThMx/Ry43dooxk +VHg== X-Gm-Message-State: AOAM532+9u0B+h2nwpBP+tM7T5hPfJrMB0WC8/UX/YX3GNHk/0QpQveJ Vll/6a8aib5IBa58QCgNUuwzHQ== X-Google-Smtp-Source: ABdhPJy6pEG+vM8mG9H0racDOdCblXhIP6nwsxcHhYIwCt3Vhwa5B2nm6NNr5p+XzaizzUXQ88vF7Q== X-Received: by 2002:a1c:5941:: with SMTP id n62mr21094150wmb.63.1610979357047; Mon, 18 Jan 2021 06:15:57 -0800 (PST) Received: from localhost (host86-166-129-230.range86-166.btcentralplus.com. [86.166.129.230]) by smtp.gmail.com with ESMTPSA id r15sm30238899wrq.1.2021.01.18.06.15.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Jan 2021 06:15:56 -0800 (PST) Date: Mon, 18 Jan 2021 14:15:55 +0000 From: Andrew Burgess To: binutils@sourceware.org, gdb-patches@sourceware.org Subject: Re: [PATCH 1/8] gdb/riscv: use a single regset supply function for riscv fbsd & linux Message-ID: <20210118141555.GU265215@embecosm.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Operating-System: Linux/5.8.13-100.fc31.x86_64 (x86_64) X-Uptime: 14:15:08 up 40 days, 18:59, X-Editor: GNU Emacs [ http://www.gnu.org/software/emacs ] X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jan 2021 14:16:00 -0000 * Andrew Burgess [2020-12-02 17:39:25 +0000]: > The RISC-V x0 register is hard-coded to zero. As such neither Linux > or FreeBSD supply the value of the register x0 in their core dump > files. > > For FreeBSD we take care of this by manually supplying the value of x0 > in riscv_fbsd_supply_gregset, however we don't do this for Linux. As > a result after loading a core file on Linux we see this behaviour: > > (gdb) p $x0 > $1 = > > In this commit I make riscv_fbsd_supply_gregset a common function that > can be shared between RISC-V for FreeBSD and Linux, this resolves the > above issue. > > There is a similar problem for the two registers `fflags` and `frm`. > These two floating point related CSRs are a little weird. They are > separate CSRs in the RISC-V specification, but are actually sub-fields > of the `fcsr` CSR. > > As a result neither Linux or FreeBSD supply the `fflags` or `frm` > registers as separate fields in their core dumps, and so, after > restoring a core dump these register are similarly unavailable. > > In this commit I supply `fflags` and `frm` by first asking for the > value of `fcsr`, extracting the two fields, and using these to supply > the values for `fflags` and `frm`. > > gdb/ChangeLog: > > * riscv-fbsd-tdep.c (riscv_fbsd_supply_gregset): Delete. > (riscv_fbsd_gregset): Use riscv_supply_regset. > (riscv_fbsd_fpregset): Likewise. > * riscv-linux-tdep.c (riscv_linux_gregset): Likewise. > (riscv_linux_fregset): Likewise. > * riscv-tdep.c (riscv_supply_regset): Define new function. > * riscv-tdep.h (riscv_supply_regset): Declare new function. I have now pushed this patch only from this series. I'm going to revise the rest of this series and post a new version. Thanks, Andrew > --- > gdb/ChangeLog | 10 +++++++++ > gdb/riscv-fbsd-tdep.c | 20 ++--------------- > gdb/riscv-linux-tdep.c | 4 ++-- > gdb/riscv-tdep.c | 50 ++++++++++++++++++++++++++++++++++++++++++ > gdb/riscv-tdep.h | 23 +++++++++++++++++++ > 5 files changed, 87 insertions(+), 20 deletions(-) > > diff --git a/gdb/riscv-fbsd-tdep.c b/gdb/riscv-fbsd-tdep.c > index 6e0eb2bb788..f9eaaa16b25 100644 > --- a/gdb/riscv-fbsd-tdep.c > +++ b/gdb/riscv-fbsd-tdep.c > @@ -53,32 +53,16 @@ static const struct regcache_map_entry riscv_fbsd_fpregmap[] = > { 0 } > }; > > -/* Supply the general-purpose registers stored in GREGS to REGCACHE. > - This function only exists to supply the always-zero x0 in addition > - to the registers in GREGS. */ > - > -static void > -riscv_fbsd_supply_gregset (const struct regset *regset, > - struct regcache *regcache, int regnum, > - const void *gregs, size_t len) > -{ > - regcache->supply_regset (&riscv_fbsd_gregset, regnum, gregs, len); > - if (regnum == -1 || regnum == RISCV_ZERO_REGNUM) > - regcache->raw_supply_zeroed (RISCV_ZERO_REGNUM); > -} > - > /* Register set definitions. */ > > const struct regset riscv_fbsd_gregset = > { > - riscv_fbsd_gregmap, > - riscv_fbsd_supply_gregset, regcache_collect_regset > + riscv_fbsd_gregmap, riscv_supply_regset, regcache_collect_regset > }; > > const struct regset riscv_fbsd_fpregset = > { > - riscv_fbsd_fpregmap, > - regcache_supply_regset, regcache_collect_regset > + riscv_fbsd_fpregmap, riscv_supply_regset, regcache_collect_regset > }; > > /* Implement the "iterate_over_regset_sections" gdbarch method. */ > diff --git a/gdb/riscv-linux-tdep.c b/gdb/riscv-linux-tdep.c > index fce838097e2..86dd536edf4 100644 > --- a/gdb/riscv-linux-tdep.c > +++ b/gdb/riscv-linux-tdep.c > @@ -52,14 +52,14 @@ static const struct regcache_map_entry riscv_linux_fregmap[] = > > static const struct regset riscv_linux_gregset = > { > - riscv_linux_gregmap, regcache_supply_regset, regcache_collect_regset > + riscv_linux_gregmap, riscv_supply_regset, regcache_collect_regset > }; > > /* Define the FP register regset. */ > > static const struct regset riscv_linux_fregset = > { > - riscv_linux_fregmap, regcache_supply_regset, regcache_collect_regset > + riscv_linux_fregmap, riscv_supply_regset, regcache_collect_regset > }; > > /* Define hook for core file support. */ > diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c > index 4e255056863..a428f79940d 100644 > --- a/gdb/riscv-tdep.c > +++ b/gdb/riscv-tdep.c > @@ -3693,6 +3693,56 @@ riscv_init_reggroups () > csr_reggroup = reggroup_new ("csr", USER_REGGROUP); > } > > +/* See riscv-tdep.h. */ > + > +void > +riscv_supply_regset (const struct regset *regset, > + struct regcache *regcache, int regnum, > + const void *regs, size_t len) > +{ > + regcache->supply_regset (regset, regnum, regs, len); > + > + if (regnum == -1 || regnum == RISCV_ZERO_REGNUM) > + regcache->raw_supply_zeroed (RISCV_ZERO_REGNUM); > + > + if (regnum == -1 || regnum == RISCV_CSR_FFLAGS_REGNUM > + || regnum == RISCV_CSR_FRM_REGNUM) > + { > + int fcsr_regnum = RISCV_CSR_FCSR_REGNUM; > + > + /* Ensure that FCSR has been read into REGCACHE. */ > + if (regnum != -1) > + regcache->supply_regset (regset, fcsr_regnum, regs, len); > + > + /* Grab the FCSR value if it is now in the regcache. We must check > + the status first as, if the register was not supplied by REGSET, > + this call will trigger a recursive attempt to fetch the > + registers. */ > + if (regcache->get_register_status (fcsr_regnum) == REG_VALID) > + { > + ULONGEST fcsr_val; > + regcache->raw_read (fcsr_regnum, &fcsr_val); > + > + /* Extract the fflags and frm values. */ > + ULONGEST fflags_val = fcsr_val & 0x1f; > + ULONGEST frm_val = (fcsr_val >> 5) & 0x7; > + > + /* And supply these if needed. */ > + if (regnum == -1 || regnum == RISCV_CSR_FFLAGS_REGNUM) > + regcache->raw_supply_integer (RISCV_CSR_FFLAGS_REGNUM, > + (gdb_byte *) &fflags_val, > + sizeof (fflags_val), > + /* is_signed */ false); > + > + if (regnum == -1 || regnum == RISCV_CSR_FRM_REGNUM) > + regcache->raw_supply_integer (RISCV_CSR_FRM_REGNUM, > + (gdb_byte *)&frm_val, > + sizeof (fflags_val), > + /* is_signed */ false); > + } > + } > +} > + > void _initialize_riscv_tdep (); > void > _initialize_riscv_tdep () > diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h > index 5bd3314d450..1064ced1192 100644 > --- a/gdb/riscv-tdep.h > +++ b/gdb/riscv-tdep.h > @@ -132,4 +132,27 @@ extern int riscv_abi_flen (struct gdbarch *gdbarch); > extern std::vector riscv_software_single_step > (struct regcache *regcache); > > +/* Supply register REGNUM from the buffer REGS (length LEN) into > + REGCACHE. REGSET describes the layout of the buffer. If REGNUM is -1 > + then all registers described by REGSET are supplied. > + > + The register RISCV_ZERO_REGNUM should not be described by REGSET, > + however, this register (which always has the value 0) will be supplied > + by this function if requested. > + > + The registers RISCV_CSR_FFLAGS_REGNUM and RISCV_CSR_FRM_REGNUM should > + not be described by REGSET, however, these register will be provided if > + requested assuming either: > + (a) REGCACHE already contains the value of RISCV_CSR_FCSR_REGNUM, or > + (b) REGSET describes the location of RISCV_CSR_FCSR_REGNUM in the REGS > + buffer. > + > + This function can be used as the supply function for either x-regs or > + f-regs when loading corefiles, and doesn't care which abi is currently > + in use. */ > + > +extern void riscv_supply_regset (const struct regset *regset, > + struct regcache *regcache, int regnum, > + const void *regs, size_t len); > + > #endif /* RISCV_TDEP_H */ > -- > 2.25.4 >