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From: Andrew Burgess <andrew.burgess@embecosm.com>
To: Jim Wilson <jimw@sifive.com>
Cc: gdb-patches@sourceware.org
Subject: Re: [PATCH] Aarch64 sim fix for gcc-10 miscompilation.
Date: Thu, 8 Apr 2021 11:36:01 +0100	[thread overview]
Message-ID: <20210408103601.GL5391@embecosm.com> (raw)
In-Reply-To: <20210408015403.29192-1-jimw@sifive.com>

* Jim Wilson <jimw@sifive.com> [2021-04-07 18:54:03 -0700]:

> This fixes a problem that occurs when compiled by gcc-10, as the code
> is relying on undefined overflow behavior.  This is fixed by replacing
> compares between 32-bit and 64-bit results with compares that just use
> the 64-bit results with a cast.
> 
> Tested with the simulator make check and a gcc make check.  There were no
> regressions.
> 
> Committed.
> 
> 	PR sim/27483
> 	* simulator.c (set_flags_for_add32): Compare uresult against
> 	itself.  Compare sresult against itself.

LGTM.

Thanks,
Andrew


> ---
>  sim/aarch64/simulator.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c
> index 6ba29a0ed57..e0b428d26d9 100644
> --- a/sim/aarch64/simulator.c
> +++ b/sim/aarch64/simulator.c
> @@ -1650,10 +1650,10 @@ set_flags_for_add32 (sim_cpu *cpu, int32_t value1, int32_t value2)
>    if (result & (1 << 31))
>      flags |= N;
>  
> -  if (uresult != (uint32_t)result)
> +  if (uresult != (uint32_t)uresult)
>      flags |= C;
>  
> -  if (sresult != result)
> +  if (sresult != (int32_t)sresult)
>      flags |= V;
>  
>    aarch64_set_CPSR (cpu, flags);
> -- 
> 2.17.1
> 

      reply	other threads:[~2021-04-08 10:36 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-08  1:54 Jim Wilson
2021-04-08 10:36 ` Andrew Burgess [this message]

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