From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by sourceware.org (Postfix) with ESMTPS id 775FB3854833 for ; Thu, 8 Apr 2021 10:36:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 775FB3854833 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=andrew.burgess@embecosm.com Received: by mail-wm1-x335.google.com with SMTP id o20-20020a05600c4fd4b0290114265518afso958840wmq.4 for ; Thu, 08 Apr 2021 03:36:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=I2QOW7jyw9iWqnRBVjN8pfg51yHhKDd4kYvQn0P3GQE=; b=AaigokFZgEf3McuXxmH3jSf1C7RMZmUcsszgpCKAeVNn8OXSd1Ik17vw8rabJt/fmz /HL9LAi30E2FIYqiSrr6VpqmV9Rug/Bsme7JItyyf+qRNp2xUoAuXMpENjSzfJ/7ya7X b0TG4P4KN/9xSc6/nHhYTXmhUakUGvev8oRrCXpO7uEP7o61MVdnDw4tKU7cUvv4L5GU GjY7ipvPv4A4txkDAAYZdaeoz++ZGseB5QmFzOpCokRt6G+LTI4cqrm1gNoYuHHg0yF+ eJRuWRevCupH7La3fnhe2075pP6aphZrXdfHw1ViWmeJcZA/dorjyPV68W1xBS10uxL4 LJsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=I2QOW7jyw9iWqnRBVjN8pfg51yHhKDd4kYvQn0P3GQE=; b=MHzHz2GQhYXm5PZoQEkb91ySPRU6iEuML/AaM4Wt6fvagqCvngpWgfnouVvRxpe5Ez ct3XdMQx0+TXIz57hLQMlOnhbV77HcR+Z+BMpoR6k4tnBbQd7wnAr7XVw6Lisx1dxbXY 3zzw3TdJVZYaycGFbztsJH3KDFyJw9utAeh/vap0Tx6Kgu2+uoiRCbd96EHSRuWujQ8O X8kwewF027P/wyDFyfWKb+r9nubq/EIzhgg/q4uNOi1GBeR1yJCP80aMGKeC7uWIf8S6 FKsnVlIaX2lz4XXvMAXuxmWivBBrdTGi7RxVVHDZ+xJRMg1YFpeGrSXpxMA3Sf+EuFha Ke4w== X-Gm-Message-State: AOAM530l8Pk2e+uhvkO16v4k7f/Eemks7EBa1VE6m9rlPSmkdjTdyEuF kICQ2DMjeGBlT0OkzsgfKtE17Z2YaUe4Fw== X-Google-Smtp-Source: ABdhPJwSghKbjS+5V8tid2Qr3NtdtGkf9K6/gZ79rzq3Wb3YYkzpJhgS42q1zXB1YtTEZ+vcTxw8pw== X-Received: by 2002:a05:600c:230e:: with SMTP id 14mr7691137wmo.150.1617878162592; Thu, 08 Apr 2021 03:36:02 -0700 (PDT) Received: from localhost (host109-151-46-70.range109-151.btcentralplus.com. [109.151.46.70]) by smtp.gmail.com with ESMTPSA id r5sm9353257wrx.87.2021.04.08.03.36.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Apr 2021 03:36:02 -0700 (PDT) Date: Thu, 8 Apr 2021 11:36:01 +0100 From: Andrew Burgess To: Jim Wilson Cc: gdb-patches@sourceware.org Subject: Re: [PATCH] Aarch64 sim fix for gcc-10 miscompilation. Message-ID: <20210408103601.GL5391@embecosm.com> References: <20210408015403.29192-1-jimw@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210408015403.29192-1-jimw@sifive.com> X-Operating-System: Linux/5.8.18-100.fc31.x86_64 (x86_64) X-Uptime: 11:35:50 up 8 days, 20:03, X-Editor: GNU Emacs [ http://www.gnu.org/software/emacs ] X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Apr 2021 10:36:05 -0000 * Jim Wilson [2021-04-07 18:54:03 -0700]: > This fixes a problem that occurs when compiled by gcc-10, as the code > is relying on undefined overflow behavior. This is fixed by replacing > compares between 32-bit and 64-bit results with compares that just use > the 64-bit results with a cast. > > Tested with the simulator make check and a gcc make check. There were no > regressions. > > Committed. > > PR sim/27483 > * simulator.c (set_flags_for_add32): Compare uresult against > itself. Compare sresult against itself. LGTM. Thanks, Andrew > --- > sim/aarch64/simulator.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c > index 6ba29a0ed57..e0b428d26d9 100644 > --- a/sim/aarch64/simulator.c > +++ b/sim/aarch64/simulator.c > @@ -1650,10 +1650,10 @@ set_flags_for_add32 (sim_cpu *cpu, int32_t value1, int32_t value2) > if (result & (1 << 31)) > flags |= N; > > - if (uresult != (uint32_t)result) > + if (uresult != (uint32_t)uresult) > flags |= C; > > - if (sresult != result) > + if (sresult != (int32_t)sresult) > flags |= V; > > aarch64_set_CPSR (cpu, flags); > -- > 2.17.1 >