From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from gateway34.websitewelcome.com (gateway34.websitewelcome.com [192.185.148.194]) by sourceware.org (Postfix) with ESMTPS id 1B8F3395383C for ; Thu, 8 Apr 2021 16:44:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 1B8F3395383C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=tromey.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=tom@tromey.com Received: from cm13.websitewelcome.com (cm13.websitewelcome.com [100.42.49.6]) by gateway34.websitewelcome.com (Postfix) with ESMTP id 8E26040C491 for ; Thu, 8 Apr 2021 11:44:38 -0500 (CDT) Received: from box5379.bluehost.com ([162.241.216.53]) by cmsmtp with SMTP id UXlmlHX0HmJLsUXlmloOJl; Thu, 08 Apr 2021 11:44:38 -0500 X-Authority-Reason: nr=8 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=tromey.com; s=default; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=5e1i6/U1WA79WrQ9u7YJFiw2a+RuaXmUQcJJUlpgyuk=; b=t4Fr4qnBr0gk8W4GMaYVIGSw3X Yeo4nAoM6z5jE+/hxgpQbNnhDjEC95KmhjsNcsrB84uPidqU3o5NoiUyqsKUAwbsvntoV53+Qqshk s4eliTJmL8csrHq5QXDy3yiFd; Received: from 71-211-182-15.hlrn.qwest.net ([71.211.182.15]:55380 helo=localhost.localdomain) by box5379.bluehost.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1lUXlm-001rc1-7S; Thu, 08 Apr 2021 10:44:38 -0600 From: Tom Tromey To: gdb-patches@sourceware.org Cc: Tom Tromey Subject: [PATCH 2/2] Add system includes in sim Date: Thu, 8 Apr 2021 10:44:36 -0600 Message-Id: <20210408164436.2165323-3-tom@tromey.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210408164436.2165323-1-tom@tromey.com> References: <20210408164436.2165323-1-tom@tromey.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - box5379.bluehost.com X-AntiAbuse: Original Domain - sourceware.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - tromey.com X-BWhitelist: no X-Source-IP: 71.211.182.15 X-Source-L: No X-Exim-ID: 1lUXlm-001rc1-7S X-Source: X-Source-Args: X-Source-Dir: X-Source-Sender: 71-211-182-15.hlrn.qwest.net (localhost.localdomain) [71.211.182.15]:55380 X-Source-Auth: tom+tromey.com X-Email-Count: 3 X-Source-Cap: ZWx5bnJvYmk7ZWx5bnJvYmk7Ym94NTM3OS5ibHVlaG9zdC5jb20= X-Local-Domain: yes X-Spam-Status: No, score=-3028.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_BL_SPAMCOP_NET, RCVD_IN_DNSWL_NONE, RCVD_IN_SBL_CSS, SPF_HELO_PASS, SPF_NEUTRAL, TXREP, URIBL_CSS, URIBL_CSS_A autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Apr 2021 16:44:41 -0000 This updates various parts of the sim to include missing system headers. I made the includes unconditional, because other parts of the tree are already doing this. sim/cris/ChangeLog 2021-04-08 Tom Tromey * traps.c: Include stdlib.h. * cris-tmpl.c: Include stdlib.h. sim/erc32/ChangeLog 2021-04-08 Tom Tromey * func.c: Include sys/time.h. sim/frv/ChangeLog 2021-04-08 Tom Tromey * traps.c: Include stdlib.h. * registers.c: Include stdlib.h. * profile.c: Include stdlib.h. * memory.c: Include stdlib.h. * interrupts.c: Include stdlib.h. * frv.c: Include stdlib.h. * cache.c: Include stdlib.h. sim/iq2000/ChangeLog 2021-04-08 Tom Tromey * iq2000.c: Include stdlib.h. sim/m32r/ChangeLog 2021-04-08 Tom Tromey * traps.c: Include stdlib.h. * m32r.c: Include stdlib.h. sim/ppc/ChangeLog 2021-04-08 Tom Tromey * emul_unix.c: Include time.h. --- sim/cris/ChangeLog | 5 +++++ sim/cris/cris-tmpl.c | 2 ++ sim/cris/traps.c | 1 + sim/erc32/ChangeLog | 4 ++++ sim/erc32/func.c | 1 + sim/frv/ChangeLog | 10 ++++++++++ sim/frv/cache.c | 1 + sim/frv/frv.c | 1 + sim/frv/interrupts.c | 1 + sim/frv/memory.c | 1 + sim/frv/profile.c | 1 + sim/frv/registers.c | 1 + sim/frv/traps.c | 2 ++ sim/iq2000/ChangeLog | 4 ++++ sim/iq2000/iq2000.c | 1 + sim/m32r/ChangeLog | 5 +++++ sim/m32r/m32r.c | 1 + sim/m32r/traps.c | 1 + sim/ppc/ChangeLog | 4 ++++ sim/ppc/emul_unix.c | 1 + 20 files changed, 48 insertions(+) diff --git a/sim/cris/cris-tmpl.c b/sim/cris/cris-tmpl.c index b5ad7189191..95579dbffa9 100644 --- a/sim/cris/cris-tmpl.c +++ b/sim/cris/cris-tmpl.c @@ -25,6 +25,8 @@ along with this program. If not, see . */ #include "cgen-mem.h" #include "cgen-ops.h" +#include + #define MY(f) XCONCAT3(crisv,BASENUM,f) /* Dispatcher for break insn. */ diff --git a/sim/cris/traps.c b/sim/cris/traps.c index 2aaa1f43b16..1c8ca41d14e 100644 --- a/sim/cris/traps.c +++ b/sim/cris/traps.c @@ -23,6 +23,7 @@ along with this program. If not, see . */ #include "bfd.h" /* FIXME: get rid of targ-vals.h usage everywhere else. */ +#include #include #include #ifdef HAVE_UNISTD_H diff --git a/sim/erc32/func.c b/sim/erc32/func.c index 98217f062ae..c6dfa1927ad 100644 --- a/sim/erc32/func.c +++ b/sim/erc32/func.c @@ -26,6 +26,7 @@ #include #include "sim-config.h" #include +#include #define VAL(x) strtoul(x,(char **)NULL,0) diff --git a/sim/frv/cache.c b/sim/frv/cache.c index 9e2a99f5f7e..c10d46373f5 100644 --- a/sim/frv/cache.c +++ b/sim/frv/cache.c @@ -24,6 +24,7 @@ along with this program. If not, see . */ #include "sim-main.h" #include "cache.h" #include "bfd.h" +#include void frv_cache_init (SIM_CPU *cpu, FRV_CACHE *cache) diff --git a/sim/frv/frv.c b/sim/frv/frv.c index 88290be3e8e..fee59c2aae7 100644 --- a/sim/frv/frv.c +++ b/sim/frv/frv.c @@ -28,6 +28,7 @@ along with this program. If not, see . */ #include "bfd.h" #include "gdb/sim-frv.h" #include +#include /* Maintain a flag in order to know when to write the address of the next VLIW instruction into the LR register. Used by JMPL. JMPIL, and CALL diff --git a/sim/frv/interrupts.c b/sim/frv/interrupts.c index d38620c9a72..0b8ed763987 100644 --- a/sim/frv/interrupts.c +++ b/sim/frv/interrupts.c @@ -22,6 +22,7 @@ along with this program. If not, see . */ #include "sim-main.h" #include "bfd.h" +#include /* FR-V Interrupt table. Describes the interrupts supported by the FR-V. diff --git a/sim/frv/memory.c b/sim/frv/memory.c index ea7f68e4349..5978d151627 100644 --- a/sim/frv/memory.c +++ b/sim/frv/memory.c @@ -23,6 +23,7 @@ along with this program. If not, see . */ #include "sim-main.h" #include "cgen-mem.h" #include "bfd.h" +#include /* Check for alignment and access restrictions. Return the corrected address. */ diff --git a/sim/frv/profile.c b/sim/frv/profile.c index c08950886d1..441590eb581 100644 --- a/sim/frv/profile.c +++ b/sim/frv/profile.c @@ -24,6 +24,7 @@ along with this program. If not, see . #include "sim-main.h" #include "bfd.h" +#include #if WITH_PROFILE_MODEL_P diff --git a/sim/frv/registers.c b/sim/frv/registers.c index c9d26fda018..764a6755b3f 100644 --- a/sim/frv/registers.c +++ b/sim/frv/registers.c @@ -22,6 +22,7 @@ along with this program. If not, see . */ #include "sim-main.h" #include "bfd.h" +#include #define IMPL 1 /* Implemented */ #define SUP 1 /* Supervisor register */ diff --git a/sim/frv/traps.c b/sim/frv/traps.c index 79ea1571ac2..c0ed9b1c49f 100644 --- a/sim/frv/traps.c +++ b/sim/frv/traps.c @@ -29,6 +29,8 @@ along with this program. If not, see . */ #include "bfd.h" #include "libiberty.h" +#include + CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot; /* The semantic code invokes this for invalid (unrecognized) instructions. */ diff --git a/sim/iq2000/iq2000.c b/sim/iq2000/iq2000.c index 23a342983ce..e03c47919fd 100644 --- a/sim/iq2000/iq2000.c +++ b/sim/iq2000/iq2000.c @@ -23,6 +23,7 @@ #include "sim-main.h" #include "cgen-mem.h" #include "cgen-ops.h" +#include enum { diff --git a/sim/m32r/m32r.c b/sim/m32r/m32r.c index 1c5379cfd74..1d0a7356bb0 100644 --- a/sim/m32r/m32r.c +++ b/sim/m32r/m32r.c @@ -23,6 +23,7 @@ #include "sim-main.h" #include "cgen-mem.h" #include "cgen-ops.h" +#include /* Return the size of REGNO in bytes. */ diff --git a/sim/m32r/traps.c b/sim/m32r/traps.c index 9edf66b58f1..9fca2b1ec1d 100644 --- a/sim/m32r/traps.c +++ b/sim/m32r/traps.c @@ -20,6 +20,7 @@ #include "sim-main.h" #include "sim-syscall.h" #include "targ-vals.h" +#include #define TRAP_FLUSH_CACHE 12 /* The semantic code invokes this for invalid (unrecognized) instructions. */ diff --git a/sim/ppc/emul_unix.c b/sim/ppc/emul_unix.c index 92c3c1ededf..2616ae408ba 100644 --- a/sim/ppc/emul_unix.c +++ b/sim/ppc/emul_unix.c @@ -124,6 +124,7 @@ int getrusage(); #endif #include +#include #if defined(BSD) && !defined(errno) && (BSD < 199306) /* here BSD as just a bug */ extern int errno; -- 2.26.2