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From: Jim Wilson <jimw@sifive.com>
To: gdb-patches@sourceware.org
Cc: Kuan-Lin Chen <rufus@andestech.com>
Subject: [PATCH 13/24] RISC-V sim: Add gettimeofday.
Date: Sat, 17 Apr 2021 10:58:20 -0700	[thread overview]
Message-ID: <20210417175831.16413-14-jimw@sifive.com> (raw)
In-Reply-To: <20210417175831.16413-1-jimw@sifive.com>

From: Kuan-Lin Chen <rufus@andestech.com>

Handle TARGET_SYS_gettimeofday.

	sim/riscv/
	* sim-main.c: Include sys/time.h.
	(execute_i): In MATCH_ECALL case, handle TARGET_sys_gettimeofday.
---
 sim/riscv/sim-main.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 7262ac1..f330ef9 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -26,6 +26,7 @@
 #include <inttypes.h>
 #include <time.h>
 #include <unistd.h>
+#include <sys/time.h>
 
 #include "sim-main.h"
 #include "sim-fpu.h"
@@ -1752,6 +1753,32 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 		  cpu->endbrk = cpu->a0;
 		break;
 	      }
+	    case TARGET_SYS_gettimeofday:
+	      {
+		int rv;
+		struct timeval tv;
+
+		rv = gettimeofday (&tv, 0);
+		if (RISCV_XLEN (cpu) == 32)
+		  {
+		    sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
+						cpu->a0, tv.tv_sec);
+		    sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
+						cpu->a0 + 4,
+						tv.tv_usec);
+		  }
+		else
+		  {
+		    sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
+						cpu->a0, tv.tv_sec);
+		    sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
+						cpu->a0 + 8,
+						tv.tv_usec);
+		  }
+
+		cpu->a0 = rv;
+		break;
+	      }
 	    default:
 	      cpu->a0 = sim_syscall (cpu, cpu->a7, cpu->a0,
 				     cpu->a1, cpu->a2, cpu->a3);
-- 
2.7.4


  parent reply	other threads:[~2021-04-17 17:59 UTC|newest]

Thread overview: 70+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-17 17:58 [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain Jim Wilson
2021-04-17 17:58 ` [PATCH 01/24] RISC-V sim: Fix fence.i Jim Wilson
2021-04-17 20:36   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 02/24] RISC-V sim: Fix for jalr Jim Wilson
2021-04-19  3:41   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 03/24] RISC-V sim: Atomic fixes Jim Wilson
2021-04-19  3:56   ` Mike Frysinger
2021-04-21 23:00     ` Jim Wilson
2021-04-22  0:09       ` Mike Frysinger
2021-04-22  3:12         ` Jim Wilson
2021-04-17 17:58 ` [PATCH 04/24] RISC-V sim: More atomic fixes Jim Wilson
2021-04-19  3:57   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 05/24] RISC-V sim: Fix stack pointer alignment Jim Wilson
2021-04-19  3:58   ` Mike Frysinger
2021-04-21 22:39     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 06/24] RISC-V: Add fp support Jim Wilson
2021-04-19  4:08   ` Mike Frysinger
2021-04-21 23:34     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 07/24] RISC-V sim: Add link syscall support Jim Wilson
2021-04-19  4:09   ` Mike Frysinger
2021-04-21 23:36     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 08/24] RISC-V sim: Add brk syscall Jim Wilson
2021-04-19  5:24   ` Mike Frysinger
2021-04-21 23:51     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 09/24] RISC-V sim: Fix syscall fallback Jim Wilson
2021-04-21 23:38   ` Jim Wilson
2021-04-22  3:23     ` Mike Frysinger
2021-04-23 20:35       ` Jim Wilson
2021-04-17 17:58 ` [PATCH 10/24] RISC-V sim: Fix ebreak Jim Wilson
2021-04-19  4:20   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 11/24] RISC-V sim: Fix ebreak, part 2 Jim Wilson
2021-04-19  4:20   ` Mike Frysinger
2021-04-21 23:41     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 12/24] RISC-V sim: Add compressed support Jim Wilson
2021-04-19  4:13   ` Mike Frysinger
2021-04-21 23:42     ` Jim Wilson
2021-04-17 17:58 ` Jim Wilson [this message]
2021-04-19  4:19   ` [PATCH 13/24] RISC-V sim: Add gettimeofday Mike Frysinger
2021-04-17 17:58 ` [PATCH 14/24] RISC-V sim: Add csrr*i instructions Jim Wilson
2021-04-19  4:26   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 15/24] RISC-V sim: Improve cycle and instret counts Jim Wilson
2021-04-19  4:25   ` Mike Frysinger
2021-04-22  2:26     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 16/24] RISC-V sim: Check sbrk argument Jim Wilson
2021-04-19  5:33   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 17/24] RISC-V sim: Fix tracing typo Jim Wilson
2021-04-19  4:26   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 18/24] RISC-V sim: Improve branch tracing Jim Wilson
2021-04-19  4:27   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 19/24] RISC-V sim: Improve tracing for slt* instructions Jim Wilson
2021-04-19  4:27   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 20/24] RISC-V sim: Set brk to _end if possible Jim Wilson
2021-04-19  5:41   ` Mike Frysinger
2021-04-22  2:45     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 21/24] RISC-V sim: Fix mingw builds Jim Wilson
2021-04-19  4:12   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 22/24] RISC-V sim: Support compressed FP instructions Jim Wilson
2021-04-19  4:27   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 23/24] RISC-V sim: Add zicsr support Jim Wilson
2021-04-19  5:13   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 24/24] RISC-V sim: Fix divw and remw Jim Wilson
2021-04-19  5:10   ` Mike Frysinger
2021-04-17 20:38 ` [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain Mike Frysinger
2021-04-19  2:33   ` Jim Wilson
2021-04-19  3:23     ` Mike Frysinger
2021-04-19  4:32       ` Jim Wilson
2021-04-19  3:42 ` Mike Frysinger
2021-04-19  4:37   ` Jim Wilson
2021-04-21 15:47 ` Andrew Burgess
2021-04-21 17:49   ` Andrew Burgess

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