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From: Jim Wilson <jimw@sifive.com>
To: gdb-patches@sourceware.org
Cc: Kito Cheng <kito.cheng@gmail.com>
Subject: [PATCH 20/24] RISC-V sim: Set brk to _end if possible.
Date: Sat, 17 Apr 2021 10:58:27 -0700	[thread overview]
Message-ID: <20210417175831.16413-21-jimw@sifive.com> (raw)
In-Reply-To: <20210417175831.16413-1-jimw@sifive.com>

From: Kito Cheng <kito.cheng@gmail.com>

Search the symbol table for the address of _end and use it to initialize
brk.  Otherwise, set it to the end of the section with the highest address.

	sim/riscv/
	* interp.c (riscv_get_symbol): New.
	(sim_create_inferior): Call riscv_get_symbol to get address of
	_end.  Use it to set cpu->endbrk.
---
 sim/riscv/interp.c | 46 ++++++++++++++++++++++++++++++++++++++--------
 1 file changed, 38 insertions(+), 8 deletions(-)

diff --git a/sim/riscv/interp.c b/sim/riscv/interp.c
index c98f6ab..7af97d5 100644
--- a/sim/riscv/interp.c
+++ b/sim/riscv/interp.c
@@ -127,14 +127,35 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback,
   return sd;
 }
 \f
+/* Search the symbol table for the symbol SYM, and return its address.  */
+
+static bfd_vma
+riscv_get_symbol (SIM_DESC sd, const char *sym)
+{
+  long symcount = STATE_PROG_SYMS_COUNT (sd);
+  asymbol **symtab = STATE_PROG_SYMS (sd);
+  int i;
+
+  for (i = 0;i < symcount; ++i)
+    {
+      if (strcmp (sym, bfd_asymbol_name (symtab[i])) == 0)
+	{
+	  bfd_vma sa;
+	  sa = bfd_asymbol_value (symtab[i]);
+	  return sa;
+	}
+    }
+
+  /* Symbol not found.  */
+  return 0;
+}
+
 SIM_RC
 sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
 		     char * const *argv, char * const *env)
 {
   SIM_CPU *cpu = STATE_CPU (sd, 0);
   SIM_ADDR addr;
-  Elf_Internal_Phdr *phdr;
-  int i, phnum;
 
   /* Set the PC.  */
   if (abfd != NULL)
@@ -143,13 +164,22 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
     addr = 0;
   sim_pc_set (cpu, addr);
 
-  /* Set endbrk to highest section end address.  */
-  phdr = elf_tdata (abfd)->phdr;
-  phnum = elf_elfheader (abfd)->e_phnum;
-  for (i = 0; i < phnum; i++)
+  /* Try to find _end symbol, and set it to the end of brk.  */
+  trace_load_symbols (sd);
+  cpu->endbrk = riscv_get_symbol (sd, "_end");
+
+  /* If not found, set end of brk to end of all section.  */
+  if (cpu->endbrk == 0)
     {
-      if (phdr[i].p_paddr + phdr[i].p_memsz > cpu->endbrk)
-	cpu->endbrk = phdr[i].p_paddr + phdr[i].p_memsz;
+      Elf_Internal_Phdr *phdr = elf_tdata (abfd)->phdr;
+      int phnum = elf_elfheader (abfd)->e_phnum;
+      int i;
+
+      for (i = 0; i < phnum; i++)
+	{
+	  if (phdr[i].p_paddr + phdr[i].p_memsz > cpu->endbrk)
+	    cpu->endbrk = phdr[i].p_paddr + phdr[i].p_memsz;
+	}
     }
 
   /* Standalone mode (i.e. `run`) will take care of the argv for us in
-- 
2.7.4


  parent reply	other threads:[~2021-04-17 17:59 UTC|newest]

Thread overview: 70+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-17 17:58 [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain Jim Wilson
2021-04-17 17:58 ` [PATCH 01/24] RISC-V sim: Fix fence.i Jim Wilson
2021-04-17 20:36   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 02/24] RISC-V sim: Fix for jalr Jim Wilson
2021-04-19  3:41   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 03/24] RISC-V sim: Atomic fixes Jim Wilson
2021-04-19  3:56   ` Mike Frysinger
2021-04-21 23:00     ` Jim Wilson
2021-04-22  0:09       ` Mike Frysinger
2021-04-22  3:12         ` Jim Wilson
2021-04-17 17:58 ` [PATCH 04/24] RISC-V sim: More atomic fixes Jim Wilson
2021-04-19  3:57   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 05/24] RISC-V sim: Fix stack pointer alignment Jim Wilson
2021-04-19  3:58   ` Mike Frysinger
2021-04-21 22:39     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 06/24] RISC-V: Add fp support Jim Wilson
2021-04-19  4:08   ` Mike Frysinger
2021-04-21 23:34     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 07/24] RISC-V sim: Add link syscall support Jim Wilson
2021-04-19  4:09   ` Mike Frysinger
2021-04-21 23:36     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 08/24] RISC-V sim: Add brk syscall Jim Wilson
2021-04-19  5:24   ` Mike Frysinger
2021-04-21 23:51     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 09/24] RISC-V sim: Fix syscall fallback Jim Wilson
2021-04-21 23:38   ` Jim Wilson
2021-04-22  3:23     ` Mike Frysinger
2021-04-23 20:35       ` Jim Wilson
2021-04-17 17:58 ` [PATCH 10/24] RISC-V sim: Fix ebreak Jim Wilson
2021-04-19  4:20   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 11/24] RISC-V sim: Fix ebreak, part 2 Jim Wilson
2021-04-19  4:20   ` Mike Frysinger
2021-04-21 23:41     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 12/24] RISC-V sim: Add compressed support Jim Wilson
2021-04-19  4:13   ` Mike Frysinger
2021-04-21 23:42     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 13/24] RISC-V sim: Add gettimeofday Jim Wilson
2021-04-19  4:19   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 14/24] RISC-V sim: Add csrr*i instructions Jim Wilson
2021-04-19  4:26   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 15/24] RISC-V sim: Improve cycle and instret counts Jim Wilson
2021-04-19  4:25   ` Mike Frysinger
2021-04-22  2:26     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 16/24] RISC-V sim: Check sbrk argument Jim Wilson
2021-04-19  5:33   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 17/24] RISC-V sim: Fix tracing typo Jim Wilson
2021-04-19  4:26   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 18/24] RISC-V sim: Improve branch tracing Jim Wilson
2021-04-19  4:27   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 19/24] RISC-V sim: Improve tracing for slt* instructions Jim Wilson
2021-04-19  4:27   ` Mike Frysinger
2021-04-17 17:58 ` Jim Wilson [this message]
2021-04-19  5:41   ` [PATCH 20/24] RISC-V sim: Set brk to _end if possible Mike Frysinger
2021-04-22  2:45     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 21/24] RISC-V sim: Fix mingw builds Jim Wilson
2021-04-19  4:12   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 22/24] RISC-V sim: Support compressed FP instructions Jim Wilson
2021-04-19  4:27   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 23/24] RISC-V sim: Add zicsr support Jim Wilson
2021-04-19  5:13   ` Mike Frysinger
2021-04-17 17:58 ` [PATCH 24/24] RISC-V sim: Fix divw and remw Jim Wilson
2021-04-19  5:10   ` Mike Frysinger
2021-04-17 20:38 ` [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain Mike Frysinger
2021-04-19  2:33   ` Jim Wilson
2021-04-19  3:23     ` Mike Frysinger
2021-04-19  4:32       ` Jim Wilson
2021-04-19  3:42 ` Mike Frysinger
2021-04-19  4:37   ` Jim Wilson
2021-04-21 15:47 ` Andrew Burgess
2021-04-21 17:49   ` Andrew Burgess

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