From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by sourceware.org (Postfix) with ESMTPS id F25253938C18 for ; Sat, 17 Apr 2021 17:59:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org F25253938C18 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=jimw@sifive.com Received: by mail-pf1-x42f.google.com with SMTP id d124so20418773pfa.13 for ; Sat, 17 Apr 2021 10:59:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nBXc25ny0OAAn+9t4ZdB2o+HPAOJv1+EkPucggmqci0=; b=Sk/gdySNDzcoUWIeOMyAu2BknRlKtFOqR4EzO5JAErV8OWc1wvQM86t+nKcTTRz/c5 eiVLkrvaMJCQYPIfdgeByqX8CNKfhthsvDkV5F9o40m9HtiqDTkAtg+UOvd5Kx/hw6ro bFR+sNpf9FxVgYv9fNUbMgs49sMr4j2BD3cf5yS2KH7bcFOOK2+pxE8v8TARlkB2qB6x sVuAIS3ewd56dTL0wP1DDZYVvW7uKiNdl3xxu0HtVGsmVsvuacxheINh74RvFE8v55J0 lGzpY0k/jHQQS9S5peZAGlTrrVrJJ++c9uG+lyi69Und3hGcfHgxmY5+GDstNI+BaIh9 BBmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nBXc25ny0OAAn+9t4ZdB2o+HPAOJv1+EkPucggmqci0=; b=POYTKr/9zFmSb2d8PuVAo/iQj5F7eyZAsAdvHbTeGtthW+UwodtfvSyudnsGutkOyX 2fczrOdy4DaKSFi4N0XVpBpgF2FiIfzkBHrI1HBhzjW8raUrLWD4NrVeJs8zT/b+Dpjg T9QMzYHMoam+viaSKptb9hnbVGqgK595di94Q9FYAsv+MaYGFo5LrgJUN+xDRcNF//9a Twy3tA5GpoCK4OqQ6UtcUgv2FIQXqdsGKrG6QuT/w6YPYJheSVsrPn09x+ZuMcd4W+Yx +6IsX3AFSJz1yexsXfYjWIG7Eg4s1UDX2nP+88ATsM7jnpNh0jJXzdgmWhU3nf8fR6lf 13bw== X-Gm-Message-State: AOAM532fBEflzIrM5veE7LSCYsgETCbFwMbKqdzgS9ZEznuBBeZRIotp I3AYdGj1Si9lDfbRj/YEmBJFTA7xWUZFpA== X-Google-Smtp-Source: ABdhPJwkNE4p79QUE3E+CPB8N4Rs+QATjcHneonELH4SMiCDTnZOSMrNGugUGdnu9DwjoO5NcXmC5Q== X-Received: by 2002:a62:7944:0:b029:253:f31f:fad5 with SMTP id u65-20020a6279440000b0290253f31ffad5mr12858072pfc.43.1618682370724; Sat, 17 Apr 2021 10:59:30 -0700 (PDT) Received: from rohan.hsd1.ca.comcast.net ([2601:646:c180:b150:1820:3ed4:975:3fbe]) by smtp.gmail.com with ESMTPSA id u4sm5030705pfk.56.2021.04.17.10.59.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Apr 2021 10:59:30 -0700 (PDT) From: Jim Wilson To: gdb-patches@sourceware.org Subject: [PATCH 23/24] RISC-V sim: Add zicsr support. Date: Sat, 17 Apr 2021 10:58:30 -0700 Message-Id: <20210417175831.16413-24-jimw@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210417175831.16413-1-jimw@sifive.com> References: <20210417175831.16413-1-jimw@sifive.com> X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 17 Apr 2021 17:59:53 -0000 The CSR and f*csr, f*rm, and f*flags instructions are in INSN_CLASS_ZICSR. Move to a new execute_zicsr function. sim/riscv/ * sim-main.c (execute_f): Remove CSR instructions. (execute_i): Likewise. (execute_zicsr): New function. (execute_one): Call execute_zicsr. --- sim/riscv/sim-main.c | 256 ++++++++++++++++++++++++++++----------------------- 1 file changed, 140 insertions(+), 116 deletions(-) diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 67ad768..3974f61 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -761,39 +761,6 @@ execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) break; } break; - case MATCH_FRCSR: - TRACE_INSN (cpu, "frcsr %s", - rd_name); - store_rd (cpu, rd, fetch_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr)); - break; - case MATCH_FSCSR: - TRACE_INSN (cpu, "fscsr %s, %sf", - rd_name, rs1_name); - store_rd (cpu, rd, fetch_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr)); - store_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr, cpu->regs[rs1]); - break; - case MATCH_FRRM: - TRACE_INSN (cpu, "frrm %s", - rd_name); - store_rd (cpu, rd, fetch_csr (cpu, "frm", CSR_FRM, &cpu->csr.frm)); - break; - case MATCH_FSRM: - TRACE_INSN (cpu, "fsrm %s, %s", - rd_name, rs1_name); - store_rd (cpu, rd, fetch_csr (cpu, "frm", CSR_FCSR, &cpu->csr.frm)); - store_csr (cpu, "frm", CSR_FCSR, &cpu->csr.frm, cpu->regs[rs1]); - break; - case MATCH_FRFLAGS: - TRACE_INSN (cpu, "frflags %s", - rd_name); - store_rd (cpu, rd, fetch_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags)); - break; - case MATCH_FSFLAGS: - TRACE_INSN (cpu, "fsflags %s, %s", - rd_name, frs1_name); - store_rd (cpu, rd, fetch_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags)); - store_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags, cpu->regs[rs1]); - break; default: TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name); sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL); @@ -1872,89 +1839,6 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) cpu->regs[rs1] + s_imm, cpu->regs[rs2]); break; - case MATCH_CSRRC: - TRACE_INSN (cpu, "csrrc"); - switch (csr) - { -#define DECLARE_CSR(name, num, ...) \ - case num: \ - store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \ - store_csr (cpu, #name, num, &cpu->csr.name, \ - cpu->csr.name & !cpu->regs[rs1]); \ - break; -#include "opcode/riscv-opc.h" -#undef DECLARE_CSR - } - break; - case MATCH_CSRRCI: - TRACE_INSN (cpu, "csrrci"); - switch (csr) - { -#define DECLARE_CSR(name, num, ...) \ - case num: \ - store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \ - store_csr (cpu, #name, num, &cpu->csr.name, \ - cpu->csr.name & !rs1); \ - break; -#include "opcode/riscv-opc.h" -#undef DECLARE_CSR - } - break; - case MATCH_CSRRS: - TRACE_INSN (cpu, "csrrs"); - switch (csr) - { -#define DECLARE_CSR(name, num, ...) \ - case num: \ - store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \ - store_csr (cpu, #name, num, &cpu->csr.name, \ - cpu->csr.name | cpu->regs[rs1]); \ - break; -#include "opcode/riscv-opc.h" -#undef DECLARE_CSR - } - break; - case MATCH_CSRRSI: - TRACE_INSN (cpu, "csrrsi"); - switch (csr) - { -#define DECLARE_CSR(name, num, ...) \ - case num: \ - store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \ - store_csr (cpu, #name, num, &cpu->csr.name, \ - cpu->csr.name | rs1); \ - break; -#include "opcode/riscv-opc.h" -#undef DECLARE_CSR - } - break; - case MATCH_CSRRW: - TRACE_INSN (cpu, "csrrw"); - switch (csr) - { -#define DECLARE_CSR(name, num, ...) \ - case num: \ - store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \ - store_csr (cpu, #name, num, &cpu->csr.name, cpu->regs[rs1]); \ - break; -#include "opcode/riscv-opc.h" -#undef DECLARE_CSR - } - break; - case MATCH_CSRRWI: - TRACE_INSN (cpu, "csrrwi"); - switch (csr) - { -#define DECLARE_CSR(name, num, ...) \ - case num: \ - store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \ - store_csr (cpu, #name, num, &cpu->csr.name, rs1); \ - break; -#include "opcode/riscv-opc.h" -#undef DECLARE_CSR - } - break; - case MATCH_RDCYCLE: TRACE_INSN (cpu, "rdcycle %s;", rd_name); store_rd (cpu, rd, fetch_csr (cpu, "cycle", CSR_CYCLE, &cpu->csr.cycle)); @@ -2409,6 +2293,144 @@ execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) } static sim_cia +execute_zicsr (SIM_CPU *cpu, unsigned_word iw, + const struct riscv_opcode *op) +{ + SIM_DESC sd = CPU_STATE (cpu); + sim_cia pc = cpu->pc + 4; + int rd = (iw >> OP_SH_RD) & OP_MASK_RD; + int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1; + const char *rd_name = riscv_gpr_names_abi[rd]; + const char *rs1_name = riscv_gpr_names_abi[rs1]; + const char *frs1_name = riscv_fpr_names_abi[rs1]; + unsigned int csr = (iw >> OP_SH_CSR) & OP_MASK_CSR; + + switch (op->match) + { + case MATCH_CSRRC: + TRACE_INSN (cpu, "csrrc"); + switch (csr) + { +#define DECLARE_CSR(name, num, ...) \ + case num: \ + store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \ + store_csr (cpu, #name, num, &cpu->csr.name, \ + cpu->csr.name & !cpu->regs[rs1]); \ + break; +#include "opcode/riscv-opc.h" +#undef DECLARE_CSR + } + break; + case MATCH_CSRRCI: + TRACE_INSN (cpu, "csrrci"); + switch (csr) + { +#define DECLARE_CSR(name, num, ...) \ + case num: \ + store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \ + store_csr (cpu, #name, num, &cpu->csr.name, \ + cpu->csr.name & !rs1); \ + break; +#include "opcode/riscv-opc.h" +#undef DECLARE_CSR + } + break; + case MATCH_CSRRS: + TRACE_INSN (cpu, "csrrs"); + switch (csr) + { +#define DECLARE_CSR(name, num, ...) \ + case num: \ + store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \ + store_csr (cpu, #name, num, &cpu->csr.name, \ + cpu->csr.name | cpu->regs[rs1]); \ + break; +#include "opcode/riscv-opc.h" +#undef DECLARE_CSR + } + break; + case MATCH_CSRRSI: + TRACE_INSN (cpu, "csrrsi"); + switch (csr) + { +#define DECLARE_CSR(name, num, ...) \ + case num: \ + store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \ + store_csr (cpu, #name, num, &cpu->csr.name, \ + cpu->csr.name | rs1); \ + break; +#include "opcode/riscv-opc.h" +#undef DECLARE_CSR + } + break; + case MATCH_CSRRW: + TRACE_INSN (cpu, "csrrw"); + switch (csr) + { +#define DECLARE_CSR(name, num, ...) \ + case num: \ + store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \ + store_csr (cpu, #name, num, &cpu->csr.name, cpu->regs[rs1]); \ + break; +#include "opcode/riscv-opc.h" +#undef DECLARE_CSR + } + break; + case MATCH_CSRRWI: + TRACE_INSN (cpu, "csrrwi"); + switch (csr) + { +#define DECLARE_CSR(name, num, ...) \ + case num: \ + store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \ + store_csr (cpu, #name, num, &cpu->csr.name, rs1); \ + break; +#include "opcode/riscv-opc.h" +#undef DECLARE_CSR + } + break; + case MATCH_FRCSR: + TRACE_INSN (cpu, "frcsr %s", + rd_name); + store_rd (cpu, rd, fetch_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr)); + break; + case MATCH_FSCSR: + TRACE_INSN (cpu, "fscsr %s, %sf", + rd_name, rs1_name); + store_rd (cpu, rd, fetch_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr)); + store_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr, cpu->regs[rs1]); + break; + case MATCH_FRRM: + TRACE_INSN (cpu, "frrm %s", + rd_name); + store_rd (cpu, rd, fetch_csr (cpu, "frm", CSR_FRM, &cpu->csr.frm)); + break; + case MATCH_FSRM: + TRACE_INSN (cpu, "fsrm %s, %s", + rd_name, rs1_name); + store_rd (cpu, rd, fetch_csr (cpu, "frm", CSR_FCSR, &cpu->csr.frm)); + store_csr (cpu, "frm", CSR_FCSR, &cpu->csr.frm, cpu->regs[rs1]); + break; + case MATCH_FRFLAGS: + TRACE_INSN (cpu, "frflags %s", + rd_name); + store_rd (cpu, rd, fetch_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags)); + break; + case MATCH_FSFLAGS: + TRACE_INSN (cpu, "fsflags %s, %s", + rd_name, frs1_name); + store_rd (cpu, rd, fetch_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags)); + store_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags, cpu->regs[rs1]); + break; + default: + TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name); + sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL); + } + + return pc; +} + +static sim_cia execute_zifencei (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) { @@ -2456,6 +2478,8 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) return execute_f_and_c (cpu, iw, op); case INSN_CLASS_D_AND_C: return execute_d_and_c (cpu, iw, op); + case INSN_CLASS_ZICSR: + return execute_zicsr (cpu, iw, op); case INSN_CLASS_ZIFENCEI: return execute_zifencei (cpu, iw, op); default: -- 2.7.4