From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by sourceware.org (Postfix) with ESMTPS id CBFB83860C32 for ; Wed, 21 Apr 2021 17:49:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org CBFB83860C32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=andrew.burgess@embecosm.com Received: by mail-wr1-x42b.google.com with SMTP id j5so41246745wrn.4 for ; Wed, 21 Apr 2021 10:49:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=mr6E4UledAWdELAtns7klrTlDZ2ML7d2dA6Bsjpk41M=; b=UxDmGcZZHjK2RekpYo9uVV0w3GwOMSmk+XGNIH7tUN73YtDA0vq30GgpygylZuQsjt 6u9DmAcpSx2M0E2xlGmdPqTpYHddI/jnnTU+CPqRWDIOXPlpKzr8BkuushjdKXDutn7W JZNzEkpIe8iCm0p+2xhZSqps/06g7hMmgzo9Bbl+vZlpNYJOYBCCnaJKquRirk4cpuNy EWFk6K7qJqhYgMf137IRD/tBphe19Xpn36HDdxbc6GsuUxpBniT1vDK7HBJHVgcQR3H+ exClaEs1CA0qjuOJ6WEzyNDpw2/+utIKBot+NW6TN/Gb9p4nPDt4AR8zo5vjBTBjbYjY n0FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=mr6E4UledAWdELAtns7klrTlDZ2ML7d2dA6Bsjpk41M=; b=ta+dYov0mSO6t150KCI5a8OF2Lx1zu7zs4CCI5QrzrBfq9UQtBZb9qYS+gDJVGuwEm n/mGq8oa+EkmDL6IARaZC2anYdmv+M1ioMEnY9q3g6BOqTVuVJgnOpj2oynsREg9RiwA y1Zjlvr9yyCRNmvqunKrpGOL5QofRgxmBo7l8k3W2wI9a7Fn9DmHWQuo7EoRuuACPK9L qP7hzqtJETuBmRfVyOjdb0LTVICql98HRIWNbr4rI4TUvoCsj7vZNH3N1xu242vmctOS DeEiI6pbyvqWkg9NdKGWXcEWaq2GnxprAkHITcUpx5Hu8eMdiDa4m+PuTTO049X1oPA8 GaYQ== X-Gm-Message-State: AOAM532pSsQqkwojPKYtSIjJs7+93CVvcoJ9G09ojvdOr9BQBm0Dbvma AYJftiwLQFxsD0POQK31NWflfw== X-Google-Smtp-Source: ABdhPJyLMJ1R4Qpe6DAYsiivw0GvAm5PGaDMxgyXxDWBL+Rzm10EZGlNyjNAizhqSg0yQAjJwTJEEQ== X-Received: by 2002:a5d:400d:: with SMTP id n13mr28140773wrp.372.1619027374969; Wed, 21 Apr 2021 10:49:34 -0700 (PDT) Received: from localhost (host109-151-46-70.range109-151.btcentralplus.com. [109.151.46.70]) by smtp.gmail.com with ESMTPSA id b206sm61179wmc.15.2021.04.21.10.49.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Apr 2021 10:49:34 -0700 (PDT) Date: Wed, 21 Apr 2021 18:49:33 +0100 From: Andrew Burgess To: Jim Wilson Cc: gdb-patches@sourceware.org Subject: Re: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain. Message-ID: <20210421174933.GL2610@embecosm.com> References: <20210417175831.16413-1-jimw@sifive.com> <20210421154739.GH2610@embecosm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210421154739.GH2610@embecosm.com> X-Operating-System: Linux/5.8.18-100.fc31.x86_64 (x86_64) X-Uptime: 18:48:18 up 11 days, 4:35, X-Editor: GNU Emacs [ http://www.gnu.org/software/emacs ] X-Spam-Status: No, score=-5.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Apr 2021 17:49:38 -0000 * Andrew Burgess [2021-04-21 16:47:39 +0100]: > * Jim Wilson [2021-04-17 10:58:07 -0700]: > > > These are mostly patches extracted from riscv-gnu-toolchain with minor > > changes to apply to current FSF GDB sim. I was careful to maintain the > > original author info, and the original commit logs when reasonable. > > Maybe a silly question, but all of these authors do have an FSF > copyright assignment in place, right? And they did all agree to pass > this code over to the FSF, right? > > I don't think we can assume that just because an assignment is in > place they choose to give this code over to FSF, it would depend upon > the context in which they originally posted the code. OK, I realise you actually already addressed this point. I don't know how I didn't see this given it was on the very next line. Apologies for the noise - it's been a long day :( Thanks, Andrew > > Thanks, > Andrew > > > > > > There are also a few extra patches from me added in, as I noticed some > > problems when reviewing the patches, and debugging issues. Note that > > Kito and Monk were at Andes when they wrote these patches, and are now > > at SiFive. So this is mostly Andes work, and they should get credit > > for this work. I kept their original email addresses even though they > > won't work anymore. We will need permission from Andes to merge the > > patches into FSF GDB. Hopefully Kuan-Lin can do that for us. The patches > > from Palmer and myself were written at SiFive. > > > > I tested this with a gcc make check using riscv-gnu-toolchain and pulling > > in FSF GDB sim with my patches applied. I get 13 gcc unexpected failures > > for rv32imac/ilp32 and 24 gcc unexpected failures for rv64gc/lp64d which > > matches the old simulator port in riscv-gnu-toolchain. I did have one > > problem with the GNUC code in mulhu function producing the wrong result, > > but I think that is a bug in the Ubuntu 16.04 gcc-4.8 on my server. If > > this is still broken with newer gcc versions I will take another look at > > that. > > > > This code can probably use some cleanup. I'd like to see the extensions > > in canonical arch order for instance. But dealing with this many patches > > is unwieldy, and I wanted to retain the original authorship for the > > patches, so I'd rather do cleanup work as follow on patches. > > > > Jim > > > > Jim Wilson (6): > > RISC-V sim: Fix fence.i. > > RISC-V sim: More atomic fixes. > > RISC-V sim: Fix ebreak, part 2. > > RISC-V sim: Fix mingw builds. > > RISC-V sim: Support compressed FP instructions. > > RISC-V sim: Add zicsr support. > > > > Kito Cheng (9): > > RISC-V sim: Atomic fixes. > > RISC-V sim: Fix syscall fallback. > > RISC-V sim: Add csrr*i instructions. > > RISC-V sim: Improve cycle and instret counts. > > RISC-V sim: Check sbrk argument. > > RISC-V sim: Improve branch tracing. > > RISC-V sim: Improve tracing for slt* instructions. > > RISC-V sim: Set brk to _end if possible. > > RISC-V sim: Fix divw and remw. > > > > Kuan-Lin Chen (5): > > RISC-V sim: Fix stack pointer alignment. > > RISC-V sim: Add link syscall support. > > RISC-V sim: Add brk syscall. > > RISC-V sim: Add gettimeofday. > > RISC-V sim: Fix tracing typo. > > > > Monk Chiang (3): > > RISC-V: Add fp support. > > RISC-V sim: Fix ebreak. > > RISC-V sim: Add compressed support. > > > > Palmer Dabbelt (1): > > RISC-V sim: Fix for jalr. > > > > sim/riscv/interp.c | 45 ++ > > sim/riscv/sim-main.c | 1790 ++++++++++++++++++++++++++++++++++++++++++++++---- > > sim/riscv/sim-main.h | 16 +- > > 3 files changed, 1733 insertions(+), 118 deletions(-) > > > > -- > > 2.7.4 > >