From: Faraz Shahbazker <fshahbazker@wavecomp.com>
To: gdb-patches@sourceware.org, Mike Frysinger <vapier@gentoo.org>
Cc: "Maciej W . Rozycki" <macro@orcam.me.uk>,
Chao-ying Fu <cfu@wavecomp.com>,
Faraz Shahbazker <fshahbazker@wavecomp.com>
Subject: [PATCH 1/2] [pr gdb/19447] sim: mips: Only truncate sign extension bits for 32-bit target models
Date: Wed, 5 May 2021 04:51:16 +0530 [thread overview]
Message-ID: <20210504232117.896136-1-fshahbazker@wavecomp.com> (raw)
64-bit BFD for MIPS applies a standard sign extension on all addresses
assuming 64-bit target. These bits are required for 64-bit and can only be
safely truncated for 32-bit target models. This partially reverts commit
b36d953bced0a4fecdde1823abac70ed7038ee95
2021-04-23 Faraz Shahbazker <fshahbazker@wavecomp.com>
sim/mips/ChangeLog:
* interp.c (sim_create_inferior): Only truncate sign extension
bits for 32-bit target models.
---
Notes:
The sign-extension logic modeled by BFD is an integral part of the MIPS64
architecture spec. It appears in the virtual address map, where sign extension
allows for 32-bit compatibility segments [1] with 64-bit
addressing. Truncating these addresses prematurely (commit
#b36d953bced0a4fecdde1823abac70ed7038ee95) in PC space breaks 64-bit models
(-DWITH_TARGET_WORD_BITSIZE=64).
In the ISA itself, direct addressing (Load-Upper-Immediate) and indirect
addressing (Load-Word) both automatically sign-extend their results. These
instructions regenerate the sign-extended addresses even if we don't start
with one. That's what causes the failures in pr gdb/19447.
Moreover, some instructions like ADD*/SUB* have unpredictable behaviour when
an operand is not correctly sign extended [3]. This affects PC-relative
addressing in particular. So arithmetic on the link-address generated in the
return address register by a jump-and-link is no longer possible, neither is
the use of the PC-relative addressing instructions provided by MIPSR6. I am
preparing upstream submission for R6, which is where I first encounted this
problem.
[1] "MIPS64 Architecture for Programmers Volume III: The MIPS64
Privileged Resource Architecture", Document Number: MD00091,
Revision 6.02, December 10, 2015, Section 4.3 "Virtual Address
Spaces", pp. 29-31
https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00091-2B-MIPS64PRA-AFP-06.03.pdf
[2] "MIPS64 Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Reference Manual", Document Number: MD00087,
Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical
List of Instructions", pp. 321
https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS64BIS-AFP-6.06.pdf
[3] "MIPS64 Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Reference Manual", Document Number: MD00087,
Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical
List of Instructions", pp. 56
https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS64BIS-AFP-6.06.pdf
sim/mips/ChangeLog | 5 +++++
sim/mips/interp.c | 19 ++++++++-----------
2 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 62b3b4cf2a6..5dd0dc8512f 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,8 @@
+2021-05-04 Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * interp.c (sim_create_inferior): Only truncate sign extension
+ bits for 32-bit target models.
+
2021-05-04 Mike Frysinger <vapier@gentoo.org>
* configure: Regenerate.
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index 64259cc3fed..fc3a953f3b9 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -1012,17 +1012,14 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
{
sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
- sim_cia pc = bfd_get_start_address (abfd);
-
- /* We need to undo brain-dead bfd behavior where it sign-extends
- addresses that are supposed to be unsigned. See the mips bfd
- sign_extend_vma setting. We have to check the ELF data itself
- in order to handle o32 & n32 ABIs. */
- if (abfd->tdata.elf_obj_data->elf_header->e_ident[EI_CLASS] ==
- ELFCLASS32)
- pc = (unsigned32) pc;
-
- CPU_PC_SET (cpu, pc);
+ /* The 64-bit BFD sign-extends MIPS addresses to model
+ 32-bit compatibility segments with 64-bit addressing.
+ These addresses work as is on 64-bit targets but
+ can be truncated for 32-bit targets. */
+ if (WITH_TARGET_WORD_BITSIZE == 32)
+ CPU_PC_SET (cpu, (unsigned32) bfd_get_start_address (abfd));
+ else
+ CPU_PC_SET (cpu, bfd_get_start_address (abfd));
}
}
--
2.25.1
next reply other threads:[~2021-05-04 23:21 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-04 23:21 Faraz Shahbazker [this message]
2021-05-04 23:21 ` [PATCH 2/2] [pr gdb/19447] sim: mips: Add shadow mappings for 32-bit memory address space Faraz Shahbazker
2021-05-12 18:21 ` Mike Frysinger
2021-05-17 7:37 ` Faraz Shahbazker
2021-05-17 7:45 ` [PATCH v2 1/2] [pr gdb/19447] sim: mips: Only truncate sign extension bits for 32-bit target models Faraz Shahbazker
2021-05-17 7:45 ` [PATCH v2 2/2] [pr gdb/19447] sim: mips: Add shadow mappings for 32-bit memory address space Faraz Shahbazker
2021-05-22 0:50 ` Mike Frysinger
2021-05-22 0:49 ` [PATCH v2 1/2] [pr gdb/19447] sim: mips: Only truncate sign extension bits for 32-bit target models Mike Frysinger
2021-05-11 21:56 ` [PATCH " Mike Frysinger
2021-05-12 16:36 ` [EXTERNAL]Re: " Faraz Shahbazker
2021-05-12 18:17 ` Mike Frysinger
2021-05-05 12:18 Faraz Shahbazker
2021-05-05 15:47 Faraz Shahbazker
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