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Rozycki" , Chao-ying Fu , Faraz Shahbazker Subject: [PATCH 5/5] gdb: mips: Add MIPSR6 support Date: Thu, 20 May 2021 13:15:54 +0530 Message-Id: <20210520074554.1465327-6-fshahbazker@wavecomp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210520074554.1465327-1-fshahbazker@wavecomp.com> References: <20210520074554.1465327-1-fshahbazker@wavecomp.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable X-Originating-IP: [123.201.194.96] X-ClientProxiedBy: PN2PR01CA0088.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:23::33) To MW3PR22MB2299.namprd22.prod.outlook.com (2603:10b6:303:47::10) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (123.201.194.96) by PN2PR01CA0088.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:23::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4129.25 via Frontend Transport; Thu, 20 May 2021 07:46:21 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6b7aee75-c04e-405c-3697-08d91b635d77 X-MS-TrafficTypeDiagnostic: MW2PR22MB2395: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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(b0s21_imm): New define. (mips32_relative_offset21, mips32_relative_offset26): New. (is_add32bit_overflow, is_add64bit_overflow): New. (mips32_next_pc): Handle r6 compact and fpu coprocessor branches. Move handling of BLEZ, BGTZ opcode into ... (mips32_blez_pc): New. (mips32_instruction_is_compact_branch): New. (mips32_insn_at_pc_has_forbidden_slot): New. (mips32_scan_prologue): Ignore pre-r6 addi encoding on r6. Stop at compact branch also. (LLSC_R6_OPCODE,LL_R6_FUNCT,LLE_FUNCT, LLD_R6_FUNCT,SC_R6_FUNCT,SCE_FUNCT, SCD_R6_FUNCT: New defines. (is_ll_insn, is_sc_insn): New. (mips_deal_with_atomic_sequence): Use is_ll_insn/is_sc_insn. Handle compact branches. (mips_about_to_return): Handle jrc and macro jr. (mips32_stack_frame_destroyed_p): Likewise. (mips32_instruction_has_delay_slot): Don't handle JALX no r6. Handle compact branches and coprocessor branches. (mips_adjust_breakpoint_address): Skip forbidden slot for compact branches. --- gdb/mips-tdep.c | 525 ++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 485 insertions(+), 40 deletions(-) diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c index 2fe83324738..504dee83bbf 100644 --- a/gdb/mips-tdep.c +++ b/gdb/mips-tdep.c @@ -76,6 +76,9 @@ static int mips16_insn_at_pc_has_delay_slot (struct gdbar= ch *gdbarch, static void mips_print_float_info (struct gdbarch *, struct ui_file *, struct frame_info *, const char *); =20 +static void mips_read_fp_register_single (struct frame_info *, int, + gdb_byte *); + /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ #define ST0_FR (1 << 26) @@ -1471,6 +1474,17 @@ mips_fetch_instruction (struct gdbarch *gdbarch, return extract_unsigned_integer (buf, instlen, byte_order); } =20 +/* Return one if the gdbarch is based on MIPS Release 6. */ + +static int +is_mipsr6_isa (struct gdbarch *gdbarch) +{ + const struct bfd_arch_info *info =3D gdbarch_bfd_arch_info (gdbarch); + + return (info->mach =3D=3D bfd_mach_mipsisa32r6 + || info->mach =3D=3D bfd_mach_mipsisa64r6); +} + /* These are the fields of 32 bit mips instructions. */ #define mips32_op(x) (x >> 26) #define itype_op(x) (x >> 26) @@ -1513,6 +1527,7 @@ mips_fetch_instruction (struct gdbarch *gdbarch, #define b0s11_op(x) ((x) & 0x7ff) #define b0s12_imm(x) ((x) & 0xfff) #define b0s16_imm(x) ((x) & 0xffff) +#define b0s21_imm(x) ((x) & 0x1fffff) #define b0s26_imm(x) ((x) & 0x3ffffff) #define b6s10_ext(x) (((x) >> 6) & 0x3ff) #define b11s5_reg(x) (((x) >> 11) & 0x1f) @@ -1549,6 +1564,18 @@ mips32_relative_offset (ULONGEST inst) return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; } =20 +static LONGEST +mips32_relative_offset21 (ULONGEST insn) +{ + return ((b0s21_imm (insn) ^ 0x100000) - 0x100000) << 2; +} + +static LONGEST +mips32_relative_offset26 (ULONGEST insn) +{ + return ((b0s26_imm (insn) ^ 0x2000000) - 0x2000000) << 2; +} + /* Determine the address of the next instruction executed after the INST floating condition branch instruction at PC. COUNT specifies the number of the floating condition bits tested by the branch. */ @@ -1607,6 +1634,73 @@ is_octeon_bbit_op (int op, struct gdbarch *gdbarch) return 0; } =20 +static int +is_add32bit_overflow (int32_t a, int32_t b) +{ + int32_t r =3D (uint32_t) a + (uint32_t) b; + return (a < 0 && b < 0 && r >=3D 0) || (a >=3D 0 && b >=3D 0 && r < 0); +} + +static int +is_add64bit_overflow (int64_t a, int64_t b) +{ + if (a !=3D (int32_t)a) + return 1; + if (b !=3D (int32_t)b) + return 1; + return is_add32bit_overflow ((int32_t)a, (int32_t)b); +} + +/* Calculate address of next instruction after BLEZ. */ + +static CORE_ADDR +mips32_blez_pc (struct gdbarch *gdbarch, struct regcache *regcache, + ULONGEST inst, CORE_ADDR pc, int invert) +{ + int rs =3D itype_rs (inst); + int rt =3D itype_rt (inst); + LONGEST val_rs =3D regcache_raw_get_signed (regcache, rs); + LONGEST val_rt =3D regcache_raw_get_signed (regcache, rt); + ULONGEST uval_rs =3D regcache_raw_get_unsigned (regcache, rs); + ULONGEST uval_rt =3D regcache_raw_get_unsigned (regcache, rt); + int taken =3D 0; + int delay_slot_size =3D 4; + + /* BLEZ, BLEZL, BGTZ, BGTZL */ + if (rt =3D=3D 0) + { + taken =3D (val_rs <=3D 0); + } + else if (is_mipsr6_isa (gdbarch)) + { + /* BLEZALC, BGTZALC */ + if (rs =3D=3D 0 && rt !=3D 0) + taken =3D (val_rt <=3D 0); + /* BGEZALC, BLTZALC */ + else if (rs =3D=3D rt && rt !=3D 0) + taken =3D (val_rt >=3D 0); + /* BGEUC, BLTUC */ + else if (rs !=3D rt && rs !=3D 0 && rt !=3D 0) + taken =3D (uval_rs >=3D uval_rt); + + /* Step through the forbidden slot to avoid repeated exceptions we d= o + not currently have access to the BD bit when hitting a breakpoint + and therefore cannot tell if the breakpoint hit on the branch or the + forbidden slot. */ + /* delay_slot_size =3D 0; */ + } + + if (invert) + taken =3D !taken; + + /* Calculate branch target */ + if (taken) + pc +=3D mips32_relative_offset (inst); + else + pc +=3D delay_slot_size; + + return pc; +} =20 /* Determine where to set a single step breakpoint while considering branch prediction. */ @@ -1617,12 +1711,17 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc) struct gdbarch *gdbarch =3D regcache->arch (); unsigned long inst; int op; + int mips64bitreg =3D 0; + + if (mips_isa_regsize (gdbarch) =3D=3D 8) + mips64bitreg =3D 1; + inst =3D mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); op =3D itype_op (inst); if ((inst & 0xe0000000) !=3D 0) /* Not a special, jump or branch instruction. */ { - if (op >> 2 =3D=3D 5) + if (op >> 2 =3D=3D 5 && ((op & 0x02) =3D=3D 0 || itype_rt (inst) =3D= =3D 0)) /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ { switch (op & 0x03) @@ -1632,7 +1731,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR = pc) case 1: /* BNEL */ goto neq_branch; case 2: /* BLEZL */ - goto less_branch; + goto lez_branch; case 3: /* BGTZL */ goto greater_branch; default: @@ -1642,15 +1741,19 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc) else if (op =3D=3D 17 && itype_rs (inst) =3D=3D 8) /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1); - else if (op =3D=3D 17 && itype_rs (inst) =3D=3D 9 + else if (!is_mipsr6_isa (gdbarch) + && op =3D=3D 17 + && itype_rs (inst) =3D=3D 9 && (itype_rt (inst) & 2) =3D=3D 0) /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2); - else if (op =3D=3D 17 && itype_rs (inst) =3D=3D 10 + else if (!is_mipsr6_isa (gdbarch) + && op =3D=3D 17 + && itype_rs (inst) =3D=3D 10 && (itype_rt (inst) & 2) =3D=3D 0) /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ pc =3D mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4); - else if (op =3D=3D 29) + else if (!is_mipsr6_isa (gdbarch) && op =3D=3D 29) /* JALX: 011101 */ /* The new PC will be alternate mode. */ { @@ -1678,7 +1781,128 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc) else pc +=3D 8; /* After the delay slot. */ } + else if (is_mipsr6_isa (gdbarch)) + { + /* BOVC, BEQZALC, BEQC and BNVC, BNEZALC, BNEC */ + if (op =3D=3D 8 || op =3D=3D 24) + { + int rs =3D rtype_rs (inst); + int rt =3D rtype_rt (inst); + LONGEST val_rs =3D regcache_raw_get_signed (regcache, rs); + LONGEST val_rt =3D regcache_raw_get_signed (regcache, rt); + int taken =3D 0; + /* BOVC (BNVC) */ + if (rs >=3D rt) + { + if (mips64bitreg =3D=3D 1) + taken =3D is_add64bit_overflow (val_rs, val_rt); + else + taken =3D is_add32bit_overflow (val_rs, val_rt); + } + /* BEQZALC (BNEZALC) */ + else if (rs < rt && rs =3D=3D 0) + taken =3D (val_rt =3D=3D 0); + /* BEQC (BNEC) */ + else + taken =3D (val_rs =3D=3D val_rt); + + /* BNVC, BNEZALC, BNEC */ + if (op =3D=3D 24) + taken =3D !taken; + + if (taken) + pc +=3D mips32_relative_offset (inst) + 4; + else + /* Step through the forbidden slot to avoid repeated exceptions + we do not currently have access to the BD bit when hitting a + breakpoint and therefore cannot tell if the breakpoint + hit on the branch or the forbidden slot. */ + pc +=3D 8; + } + /* BC1EQZ, BC1NEZ */ + else if (op =3D=3D 17 && (itype_rs (inst) =3D=3D 9 || itype_rs (inst) = =3D=3D 13)) + { + gdb_byte status; + gdb_byte true_val =3D 0; + unsigned int fp =3D gdbarch_num_regs (gdbarch) + + mips_regnum (gdbarch)->fp0 + + itype_rt (inst); + struct frame_info *frame =3D get_current_frame (); + gdb_byte *raw_buffer =3D (gdb_byte *) alloca (sizeof (gdb_byte) * 4= ); + mips_read_fp_register_single (frame, fp, raw_buffer); + + if (gdbarch_byte_order (gdbarch) =3D=3D BFD_ENDIAN_BIG) + status =3D *(raw_buffer + 3); + else + status =3D *(raw_buffer); =20 + if (itype_rs (inst) =3D=3D 13) + true_val =3D 1; + + if ((status & 0x1) =3D=3D true_val) + pc +=3D mips32_relative_offset (inst) + 4; + else + pc +=3D 8; + } + else if (op =3D=3D 22 || op =3D=3D 23) + /* BLEZC, BGEZC, BGEC, BGTZC, BLTZC, BLTC */ + { + int rs =3D rtype_rs (inst); + int rt =3D rtype_rt (inst); + LONGEST val_rs =3D regcache_raw_get_signed (regcache, rs); + LONGEST val_rt =3D regcache_raw_get_signed (regcache, rt); + int taken =3D 0; + /* The R5 rt =3D=3D 0 case is handled above so we treat it as + an unknown instruction here for future ISA usage. */ + if (rs =3D=3D 0 && rt !=3D 0) + taken =3D (val_rt <=3D 0); + else if (rs =3D=3D rt && rt !=3D 0) + taken =3D (val_rt >=3D 0); + else if (rs !=3D rt && rs !=3D 0 && rt !=3D 0) + taken =3D (val_rs >=3D val_rt); + + if (op =3D=3D 23) + taken =3D !taken; + + if (taken) + pc +=3D mips32_relative_offset (inst) + 4; + else + /* Step through the forbidden slot to avoid repeated exceptions + we do not currently have access to the BD bit when hitting a + breakpoint and therefore cannot tell if the breakpoint + hit on the branch or the forbidden slot. */ + pc +=3D 8; + } + else if (op =3D=3D 50 || op =3D=3D 58) + /* BC, BALC */ + pc +=3D mips32_relative_offset26 (inst) + 4; + else if ((op =3D=3D 54 || op =3D=3D 62) + && rtype_rs (inst) =3D=3D 0) + /* JIC, JIALC */ + { + pc =3D regcache_raw_get_signed (regcache, itype_rt (inst)); + pc +=3D (itype_immediate (inst) ^ 0x8000) - 0x8000; + } + else if (op =3D=3D 54 || op =3D=3D 62) + /* BEQZC, BNEZC */ + { + int rs =3D itype_rs (inst); + LONGEST rs_val =3D regcache_raw_get_signed (regcache, rs); + int taken =3D (rs_val =3D=3D 0); + if (op =3D=3D 62) + taken =3D !taken; + if (taken) + pc +=3D mips32_relative_offset21 (inst) + 4; + else + /* Step through the forbidden slot to avoid repeated exceptions + we do not currently have access to the BD bit when hitting a + breakpoint and therefore cannot tell if the breakpoint + hit on the branch or the forbidden slot. */ + pc +=3D 8; + } + else + pc +=3D 4; /* Not a branch, next instruction is easy. */ + } else pc +=3D 4; /* Not a branch, next instruction is easy. */ } @@ -1722,7 +1946,6 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR = pc) case 2: /* BLTZL */ case 16: /* BLTZAL */ case 18: /* BLTZALL */ - less_branch: if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0) pc +=3D mips32_relative_offset (inst) + 4; else @@ -1738,22 +1961,38 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc) pc +=3D 8; /* after the delay slot */ break; case 0x1c: /* BPOSGE32 */ + case 0x1d: /* BPOSGE32C */ case 0x1e: /* BPOSGE64 */ pc +=3D 4; if (itype_rs (inst) =3D=3D 0) { unsigned int pos =3D (op & 2) ? 64 : 32; int dspctl =3D mips_regnum (gdbarch)->dspctl; + int delay_slot_size =3D 4; =20 if (dspctl =3D=3D -1) /* No way to handle; it'll most likely trap anyway. */ break; =20 + /* BPOSGE32C */ + if (op =3D=3D 0x1d) + { + if (!is_mipsr6_isa (gdbarch)) + break; + + /* Step through the forbidden slot to avoid repeated + exceptions we do not currently have access to the BD + bit when hitting a breakpoint and therefore cannot + tell if the breakpoint hit on the branch or the + forbidden slot. */ + /* delay_slot_size =3D 0; */ + } + if ((regcache_raw_get_unsigned (regcache, dspctl) & 0x7f) >=3D pos) pc +=3D mips32_relative_offset (inst); else - pc +=3D 4; + pc +=3D delay_slot_size; } break; /* All of the other instructions in the REGIMM category */ @@ -1787,19 +2026,14 @@ mips32_next_pc (struct regcache *regcache, CORE_ADD= R pc) else pc +=3D 8; break; - case 6: /* BLEZ, BLEZL */ - if (regcache_raw_get_signed (regcache, itype_rs (inst)) <=3D 0) - pc +=3D mips32_relative_offset (inst) + 4; - else - pc +=3D 8; + case 6: /* BLEZ, BLEZL, BLEZALC, BGEZALC, BGEUC */ + lez_branch: + pc =3D mips32_blez_pc (gdbarch, regcache, inst, pc + 4, 0); break; case 7: default: - greater_branch: /* BGTZ, BGTZL */ - if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0) - pc +=3D mips32_relative_offset (inst) + 4; - else - pc +=3D 8; + greater_branch: /* BGTZ, BGTZL, BGTZALC, BLTZALC, BLTUC */ + pc =3D mips32_blez_pc (gdbarch, regcache, inst, pc + 4, 1); break; } /* switch */ } /* else */ @@ -2422,6 +2656,74 @@ micromips_instruction_is_compact_branch (unsigned sh= ort insn) } } =20 +/* Return non-zero if the MIPS instruction INSN is a compact branch + or jump. A value of 1 indicates an unconditional compact branch + and a value of 2 indicates a conditional compact branch. */ + +static int +mips32_instruction_is_compact_branch (struct gdbarch *gdbarch, ULONGEST in= sn) +{ + switch (itype_op (insn)) + { + /* BC */ + case 50: + /* BALC */ + case 58: + if (is_mipsr6_isa (gdbarch)) + return 1; + break; + /* BOVC, BEQZALC, BEQC */ + case 8: + /* BNVC, BNEZALC, BNEC */ + case 24: + if (is_mipsr6_isa (gdbarch)) + return 2; + break; + /* BEQZC, JIC */ + case 54: + /* BNEZC, JIALC */ + case 62: + if (is_mipsr6_isa (gdbarch)) + /* JIC, JIALC are unconditional */ + return (itype_rs (insn) =3D=3D 0) ? 1 : 2; + break; + /* BLEZC, BGEZC, BGEC */ + case 22: + /* BGTZC, BLTZC, BLTC */ + case 23: + /* BLEZALC, BGEZALC, BGEUC */ + case 6: + /* BGTZALC, BLTZALC, BLTUC */ + case 7: + if (is_mipsr6_isa (gdbarch) + && itype_rt (insn) !=3D 0) + return 2; + break; + /* BPOSGE32C */ + case 1: + if (is_mipsr6_isa (gdbarch) + && itype_rt (insn) =3D=3D 0x1d && itype_rs (insn) =3D=3D 0) + return 2; + } + return 0; +} + +/* Return non-zero if a standard MIPS instruction at ADDR has a branch + forbidden slot (i.e. it is a conditional compact branch instruction). = */ + +static int +mips32_insn_at_pc_has_forbidden_slot (struct gdbarch *gdbarch, CORE_ADDR a= ddr) +{ + ULONGEST insn; + int status; + + insn =3D mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status); + if (status) + return 0; + + return mips32_instruction_is_compact_branch (gdbarch, insn) =3D=3D 2; +} + struct mips_frame_cache { CORE_ADDR base; @@ -3463,7 +3765,8 @@ mips32_scan_prologue (struct gdbarch *gdbarch, reg =3D high_word & 0x1f; =20 if (high_word =3D=3D 0x27bd /* addiu $sp,$sp,-i */ - || high_word =3D=3D 0x23bd /* addi $sp,$sp,-i */ + || (high_word =3D=3D 0x23bd /* addi $sp,$sp,-i */ + && !is_mipsr6_isa (gdbarch)) || high_word =3D=3D 0x67bd) /* daddiu $sp,$sp,-i */ { if (offset < 0) /* Negative stack adjustment? */ @@ -3596,9 +3899,12 @@ mips32_scan_prologue (struct gdbarch *gdbarch, =20 non_prologue_insns +=3D this_non_prologue_insn; =20 + /* A jump or branch, or enough non-prologue insns seen? If so, then we must have reached the end of the prologue by now. */ - if (prev_delay_slot || non_prologue_insns > 1) + if (prev_delay_slot + || non_prologue_insns > 1 + || mips32_instruction_is_compact_branch (gdbarch, inst)) break; =20 prev_non_prologue_insn =3D this_non_prologue_insn; @@ -3902,6 +4208,59 @@ mips_addr_bits_remove (struct gdbarch *gdbarch, CORE= _ADDR addr) #define LLD_OPCODE 0x34 #define SC_OPCODE 0x38 #define SCD_OPCODE 0x3c +#define LLSC_R6_OPCODE 0x1f +#define LL_R6_FUNCT 0x36 +#define LLE_FUNCT 0x2e +#define LLD_R6_FUNCT 0x37 +#define SC_R6_FUNCT 0x26 +#define SCE_FUNCT 0x1e +#define SCD_R6_FUNCT 0x27 + +static int +is_ll_insn (struct gdbarch *gdbarch, ULONGEST insn) +{ + if (itype_op (insn) =3D=3D LL_OPCODE + || itype_op (insn) =3D=3D LLD_OPCODE) + return 1; + + if (rtype_op (insn) =3D=3D LLSC_R6_OPCODE + && rtype_funct (insn) =3D=3D LLE_FUNCT + && (insn & 0x40) =3D=3D 0) + return 1; + + /* Handle LL and LLP varieties. */ + if (is_mipsr6_isa (gdbarch) + && rtype_op (insn) =3D=3D LLSC_R6_OPCODE + && (rtype_funct (insn) =3D=3D LL_R6_FUNCT + || rtype_funct (insn) =3D=3D LLD_R6_FUNCT + || rtype_funct (insn) =3D=3D LLE_FUNCT)) + return 1; + + return 0; +} + +static int +is_sc_insn (struct gdbarch *gdbarch, ULONGEST insn) +{ + if (itype_op (insn) =3D=3D SC_OPCODE + || itype_op (insn) =3D=3D SCD_OPCODE) + return 1; + + if (rtype_op (insn) =3D=3D LLSC_R6_OPCODE + && rtype_funct (insn) =3D=3D SCE_FUNCT + && (insn & 0x40) =3D=3D 0) + return 1; + + /* Handle SC and SCP varieties. */ + if (is_mipsr6_isa (gdbarch) + && rtype_op (insn) =3D=3D LLSC_R6_OPCODE + && (rtype_funct (insn) =3D=3D SC_R6_FUNCT + || rtype_funct (insn) =3D=3D SCD_R6_FUNCT + || rtype_funct (insn) =3D=3D SCE_FUNCT)) + return 1; + + return 0; +} =20 static std::vector mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) @@ -3914,10 +4273,11 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdb= arch, CORE_ADDR pc) int index; int last_breakpoint =3D 0; /* Defaults to 0 (no breakpoints placed). */= =20 const int atomic_sequence_length =3D 16; /* Instruction sequence length.= */ + int is_mipsr6 =3D is_mipsr6_isa (gdbarch); =20 insn =3D mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); /* Assume all atomic sequences start with a ll/lld instruction. */ - if (itype_op (insn) !=3D LL_OPCODE && itype_op (insn) !=3D LLD_OPCODE) + if (!is_ll_insn (gdbarch, insn)) return {}; =20 /* Assume that no atomic sequence is longer than "atomic_sequence_length= "=20 @@ -3947,28 +4307,72 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdb= arch, CORE_ADDR pc) return {}; /* fallback to the standard single-step code. */ case 4: /* BEQ */ case 5: /* BNE */ - case 6: /* BLEZ */ - case 7: /* BGTZ */ case 20: /* BEQL */ case 21: /* BNEL */ - case 22: /* BLEZL */ - case 23: /* BGTTL */ + case 22: /* BLEZL (BLEZC, BGEZC, BGEC) */ + case 23: /* BGTZL (BGTZC, BLTZC, BLTC) */ is_branch =3D 1; break; + case 6: /* BLEZ (BLEZALC, BGEZALC, BGEUC) */ + case 7: /* BGTZ (BGTZALC, BLTZALC, BLTUC) */ + if (is_mipsr6) + { + /* BLEZALC, BGTZALC */ + if (itype_rs (insn) =3D=3D 0 && itype_rt (insn) !=3D 0) + return {}; /* fallback to the standard single-step code. */ + /* BGEZALC, BLTZALC */ + else if (itype_rs (insn) =3D=3D itype_rt (insn) + && itype_rt (insn) !=3D 0) + return {}; /* fallback to the standard single-step code. */ + } + is_branch =3D 1; + break; + case 8: /* BOVC, BEQZALC, BEQC */ + case 24: /* BNVC, BNEZALC, BNEC */ + if (is_mipsr6) + is_branch =3D 1; + break; + case 50: /* BC */ + case 58: /* BALC */ + if (is_mipsr6) + return {}; /* fallback to the standard single-step code. */ + break; + case 54: /* BEQZC, JIC */ + case 62: /* BNEZC, JIALC */ + if (is_mipsr6) + { + if (itype_rs (insn) =3D=3D 0) /* JIC, JIALC */ + return {}; /* fallback to the standard single-step code. */ + else + is_branch =3D 2; /* Marker for branches with a 21-bit offset */ + } + break; case 17: /* COP1 */ - is_branch =3D ((itype_rs (insn) =3D=3D 9 || itype_rs (insn) =3D=3D 10) - && (itype_rt (insn) & 0x2) =3D=3D 0); + is_branch =3D ((!is_mipsr6 + && (itype_rs (insn) =3D=3D 9 || itype_rs (insn) =3D=3D 10) + && (itype_rt (insn) & 0x2) =3D=3D 0) + /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ + || (itype_rs (insn) & 0x18) =3D=3D 0x18); + /* BZ.df: 010001 110xx */ if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ break; /* Fall through. */ case 18: /* COP2 */ case 19: /* COP3 */ - is_branch =3D (itype_rs (insn) =3D=3D 8); /* BCzF, BCzFL, BCzT, BCzTL *= / + /* BCzF, BCzFL, BCzT, BCzTL, BC*EQZ, BC*NEZ */ + is_branch =3D (itype_rs (insn) =3D=3D 8) + || (is_mipsr6 + && (itype_rs (insn) =3D=3D 9 + || itype_rs (insn) =3D=3D 13)); break; } if (is_branch) { - branch_bp =3D loc + mips32_relative_offset (insn) + 4; + /* Is this a special PC21_S2 branch? */ + if (is_branch =3D=3D 2) + branch_bp =3D loc + mips32_relative_offset21 (insn) + 4; + else + branch_bp =3D loc + mips32_relative_offset (insn) + 4; if (last_breakpoint >=3D 1) return {}; /* More than one branch found, fallback to the standard single-step code. */ @@ -3976,12 +4380,12 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdb= arch, CORE_ADDR pc) last_breakpoint++; } =20 - if (itype_op (insn) =3D=3D SC_OPCODE || itype_op (insn) =3D=3D SCD_O= PCODE) + if (is_sc_insn (gdbarch, insn)) break; } =20 /* Assume that the atomic sequence ends with a sc/scd instruction. */ - if (itype_op (insn) !=3D SC_OPCODE && itype_op (insn) !=3D SCD_OPCODE) + if (!is_sc_insn (gdbarch, insn)) return {}; =20 loc +=3D MIPS_INSN32_SIZE; @@ -4206,8 +4610,14 @@ mips_about_to_return (struct gdbarch *gdbarch, CORE_= ADDR pc) gdb_assert (mips_pc_is_mips (pc)); =20 insn =3D mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); - hint =3D 0x7c0; - return (insn & ~hint) =3D=3D 0x3e00008; /* jr(.hb) $ra */ + /* Mask the hint and the jalr/jr bit */ + hint =3D 0x7c1; + + if (is_mipsr6_isa (gdbarch) && insn =3D=3D 0xd81f0000) /* jrc $31 */ + return 1; + + /* jr(.hb) $ra and "jalr(.hb) $ra" */ + return ((insn & ~hint) =3D=3D 0x3e00008); } =20 =20 @@ -6711,7 +7121,9 @@ mips32_stack_frame_destroyed_p (struct gdbarch *gdbar= ch, CORE_ADDR pc) =20 if (high_word !=3D 0x27bd /* addiu $sp,$sp,offset */ && high_word !=3D 0x67bd /* daddiu $sp,$sp,offset */ - && inst !=3D 0x03e00008 /* jr $ra */ + && (inst & ~0x1) !=3D 0x03e00008 /* jr $31 or jalr $0, $31 */ + && (!is_mipsr6_isa (gdbarch) + || inst !=3D 0xd81f0000) /* jrc $31 */ && inst !=3D 0x00000000) /* nop */ return 0; } @@ -7092,22 +7504,31 @@ mips32_instruction_has_delay_slot (struct gdbarch *= gdbarch, ULONGEST inst) int op; int rs; int rt; + int is_mipsr6 =3D is_mipsr6_isa (gdbarch); =20 op =3D itype_op (inst); if ((inst & 0xe0000000) !=3D 0) { rs =3D itype_rs (inst); rt =3D itype_rt (inst); - return (is_octeon_bbit_op (op, gdbarch)=20 - || op >> 2 =3D=3D 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ - || op =3D=3D 29 /* JALX: bits 011101 */ + return (is_octeon_bbit_op (op, gdbarch) + || (op >> 1 =3D=3D 10) /* BEQL, BNEL: bits 01010x */ + || (op >> 1 =3D=3D 11 && rt =3D=3D 0) /* BLEZL, BGTZL: bits 01011x = */ + || (!is_mipsr6 && op =3D=3D 29) /* JALX: bits 011101 */ || (op =3D=3D 17 && (rs =3D=3D 8 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ - || (rs =3D=3D 9 && (rt & 0x2) =3D=3D 0) + || (!is_mipsr6 && rs =3D=3D 9 && (rt & 0x2) =3D=3D 0) /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ - || (rs =3D=3D 10 && (rt & 0x2) =3D=3D 0)))); + || (!is_mipsr6 && rs =3D=3D 10 && (rt & 0x2) =3D=3D 0))) /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ + || (is_mipsr6 + && ((op =3D=3D 17 + && (rs =3D=3D 9 /* BC1EQZ: 010001 01001 */ + || rs =3D=3D 13 /* BC1NEZ: 010001 01101 */ )) + || (op =3D=3D 18 + && (rs =3D=3D 9 /* BC2EQZ: 010010 01001 */ + || rs =3D=3D 13 /* BC2NEZ: 010010 01101 */ ))))); } else switch (op & 0x07) /* extract bits 28,27,26 */ @@ -7126,7 +7547,11 @@ mips32_instruction_has_delay_slot (struct gdbarch *g= dbarch, ULONGEST inst) || ((rt & 0x1e) =3D=3D 0x1c && rs =3D=3D 0)); /* BPOSGE32, BPOSGE64: bits 1110x */ break; /* end REGIMM */ - default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ + case 6: /* BLEZ */ + case 7: /* BGTZ */ + return (itype_rt (inst) =3D=3D 0); + break; + default: /* J, JAL, BEQ, BNE */ return 1; break; } @@ -7338,7 +7763,18 @@ mips_adjust_breakpoint_address (struct gdbarch *gdba= rch, CORE_ADDR bpaddr) =20 So, we'll use the second solution. To do this we need to know if the instruction we're trying to set the breakpoint on is in the - branch delay slot. */ + branch delay slot. + + A similar problem occurs for breakpoints on forbidden slots where + the trap will be reported for the branch with the BD bit set. + In this case it would be ideal to recover using solution 1 from + above as there is no problem with the branch being skipped + (since the forbidden slot only exists on not-taken branches). + However, the BD bit is not available in all scenarios currently + so instead we move the breakpoint on to the next instruction. + This means that it is not possible to stop on an instruction + that can be in a forbidden slot even if that instruction is + jumped to directly. */ =20 boundary =3D mips_segment_boundary (bpaddr); =20 @@ -7360,6 +7796,13 @@ mips_adjust_breakpoint_address (struct gdbarch *gdba= rch, CORE_ADDR bpaddr) prev_addr =3D bpaddr - 4; if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr)) bpaddr =3D prev_addr; + /* If the previous instruction has a forbidden slot, we have to + move the breakpoint to the following instruction to prevent + breakpoints in forbidden slots being reported as unknown + traps. */ + else if (mips32_insn_at_pc_has_forbidden_slot (gdbarch, prev_addr)) + + bpaddr +=3D 4; } else { @@ -7772,6 +8215,8 @@ mips_in_return_stub (struct gdbarch *gdbarch, CORE_AD= DR pc, const char *name) PC of the stub target. The stub just loads $t9 and jumps to it, so that $t9 has the correct value at function entry. */ =20 +/* TODO: Update for compact jump trampoline */ + static CORE_ADDR mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) { --=20 2.25.1