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* [PATCH 1/2] sim: h8300 Fixed different behavior in preinc/predec.
@ 2021-05-21 14:16 Yoshinori Sato
  2021-05-21 14:16 ` [PATCH 2/2] sim: h8300 add special case test Yoshinori Sato
                   ` (4 more replies)
  0 siblings, 5 replies; 13+ messages in thread
From: Yoshinori Sato @ 2021-05-21 14:16 UTC (permalink / raw)
  To: gdb-patches

Fixed some addressing modes not working properly on the h8300.
I have confirmed in the test case that the result is
the same as the actual CPU.

ChangeLog.
2021-05-21  Yoshinori Sato  <ysato@users.sourceforge.jp>

	* sim-main.h (h8_typecodes): Add operand type OP_REG_DEC, OP_REG_INC.
	* compile.c (decode): Rewrite oprand type for specific case.
	(fetch_1): Add handling OP_REG_DEC and OP_REG_INC.
	(step_once): Fix operand fetch order.
---
 sim/h8300/compile.c  | 52 ++++++++++++++++++++++++++++++++++++++++++--
 sim/h8300/sim-main.h |  4 +++-
 2 files changed, 53 insertions(+), 3 deletions(-)

diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c
index 365f8667c6a..885e347d3a6 100644
--- a/sim/h8300/compile.c
+++ b/sim/h8300/compile.c
@@ -1098,6 +1098,35 @@ decode (SIM_DESC sd, int addr, unsigned char *data, decoded_inst *dst)
 		      /* End of Processing for system calls.  */
 		    }
 
+		  /* Use same register is specified for source
+		     and destination.
+		     the value of source will be the value after
+		     address calculation. */
+		  if (OP_KIND(dst->opcode) != O_CMP &&
+		      OP_KIND(dst->src.type) == OP_REG &&
+		      (dst->src.reg & 7) == dst->dst.reg) {
+		    switch (OP_KIND(dst->dst.type))
+		      {
+		      case OP_POSTDEC:
+			dst->src.type = X(OP_REG_DEC,
+					  OP_SIZE(dst->dst.type));
+			break;
+		      case OP_POSTINC:
+			dst->src.type = X(OP_REG_INC,
+					  OP_SIZE(dst->dst.type));
+			break;
+		      case OP_PREINC:
+			if (OP_KIND(dst->opcode) == O_MOV)
+			  dst->src.type = X(OP_REG_INC,
+					    OP_SIZE(dst->dst.type));
+			break;
+		      case OP_PREDEC:
+			if (OP_KIND(dst->opcode) == O_MOV)
+			  dst->src.type = X(OP_REG_DEC,
+					    OP_SIZE(dst->dst.type));
+			break;
+		      }
+		  }
 		  dst->next_pc = addr + len / 2;
 		  return;
 		}
@@ -1368,6 +1397,25 @@ fetch_1 (SIM_DESC sd, ea_type *arg, int *val, int twice)
       *val = abs;
       break;
 
+    case X (OP_REG_DEC, SB):	/* Register direct, affected decrement byte. */
+      *val = GET_B_REG (rn) - 1;
+      break;
+    case X (OP_REG_DEC, SW):	/* Register direct, affected decrement word. */
+      *val = GET_W_REG (rn) - 2;
+      break;
+    case X (OP_REG_DEC, SL):	/* Register direct, affected decrement long. */
+      *val = GET_L_REG (rn) - 4;
+      break;
+    case X (OP_REG_INC, SB):	/* Register direct, affected increment byte. */
+      *val = GET_B_REG (rn) + 1;
+      break;
+    case X (OP_REG_INC, SW):	/* Register direct, affected increment word. */
+      *val = GET_W_REG (rn) + 2;
+      break;
+    case X (OP_REG_INC, SL):	/* Register direct, affected increment long. */
+      *val = GET_L_REG (rn) + 4;
+      break;
+
     case X (OP_MEM, SB):	/* Why isn't this implemented?  */
     default:
       sim_engine_halt (sd, cpu, NULL, NULL_CIA, sim_stopped, SIM_SIGSEGV);
@@ -1976,7 +2024,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
 
 	case O (O_AND, SB):		/* and.b */
 	  /* Fetch rd and ea.  */
-	  if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd)) 
+	  if (fetch2 (sd, &code->dst, &rd) || fetch (sd, &code->src, &ea))
 	    goto end;
 	  res = rd & ea;
 	  goto log8;
@@ -1997,7 +2045,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
 
 	case O (O_OR, SB):		/* or.b */
 	  /* Fetch rd and ea.  */
-	  if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd)) 
+	  if (fetch2 (sd, &code->dst, &rd) || fetch (sd, &code->src, &ea))
 	    goto end;
 	  res = rd | ea;
 	  goto log8;
diff --git a/sim/h8300/sim-main.h b/sim/h8300/sim-main.h
index b6169b3bc12..686d5337639 100644
--- a/sim/h8300/sim-main.h
+++ b/sim/h8300/sim-main.h
@@ -83,7 +83,9 @@ enum h8_typecodes {
   /* FIXME: memory indirect?  */
   OP_INDEXB,		/* Byte index mode */
   OP_INDEXW,		/* Word index mode */
-  OP_INDEXL		/* Long index mode */
+  OP_INDEXL,		/* Long index mode */
+  OP_REG_DEC,		/* Register direct. affect address decrement. */
+  OP_REG_INC,		/* Register direct. affect address increment. */
 };
 
 #include "sim-basics.h"
-- 
2.20.1


^ permalink raw reply	[flat|nested] 13+ messages in thread
end of thread, other threads:[~2021-05-26 20:23 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-21 14:16 [PATCH 1/2] sim: h8300 Fixed different behavior in preinc/predec Yoshinori Sato
2021-05-21 14:16 ` [PATCH 2/2] sim: h8300 add special case test Yoshinori Sato
2021-05-21 15:03 ` [PATCH RESEND " Yoshinori Sato
2021-05-21 22:41   ` Mike Frysinger
2021-05-21 22:41 ` [PATCH 1/2] sim: h8300 Fixed different behavior in preinc/predec Mike Frysinger
2021-05-23 13:42   ` Yoshinori Sato
2021-05-25 14:10 ` [PATCH v2 " Yoshinori Sato
2021-05-25 14:10   ` [PATCH v2 2/2] sim: h8300 add special case test Yoshinori Sato
2021-05-25 23:10     ` Mike Frysinger
2021-05-25 23:09   ` [PATCH v2 1/2] sim: h8300 Fixed different behavior in preinc/predec Mike Frysinger
2021-05-26 11:52 ` [PATCH v3 " Yoshinori Sato
2021-05-26 11:52   ` [PATCH v3 2/2] sim: h8300 add special case test Yoshinori Sato
2021-05-26 20:23   ` [PATCH v3 1/2] sim: h8300 Fixed different behavior in preinc/predec Mike Frysinger

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