From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp.gentoo.org (woodpecker.gentoo.org [IPv6:2001:470:ea4a:1:5054:ff:fec7:86e4]) by sourceware.org (Postfix) with ESMTP id 5D6813857C7A for ; Sun, 28 Nov 2021 08:44:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5D6813857C7A Received: by smtp.gentoo.org (Postfix, from userid 559) id EF036342F22; Sun, 28 Nov 2021 08:44:19 +0000 (UTC) From: Mike Frysinger To: gdb-patches@sourceware.org Subject: [PATCH 7/9] sim: riscv: switch to new target-newlib-syscall Date: Sun, 28 Nov 2021 03:43:56 -0500 Message-Id: <20211128084358.29302-7-vapier@gentoo.org> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211128084358.29302-1-vapier@gentoo.org> References: <20211128084358.29302-1-vapier@gentoo.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 28 Nov 2021 08:44:22 -0000 Use the new target-newlib-syscall module. This is needed to merge all the architectures into a single build, and riscv has a custom syscall table for its newlib/libgloss port. --- sim/riscv/Makefile.in | 3 --- sim/riscv/interp.c | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/sim/riscv/Makefile.in b/sim/riscv/Makefile.in index 17cb288eba3d..b967654d7875 100644 --- a/sim/riscv/Makefile.in +++ b/sim/riscv/Makefile.in @@ -15,9 +15,6 @@ # You should have received a copy of the GNU General Public License # along with this program. If not, see . -# This selects the newlib/libgloss syscall definitions. -NL_TARGET = -DNL_TARGET_riscv - ## COMMON_PRE_CONFIG_FRAG SIM_OBJS = \ diff --git a/sim/riscv/interp.c b/sim/riscv/interp.c index efa4b5669cb3..13fe6c7cae0d 100644 --- a/sim/riscv/interp.c +++ b/sim/riscv/interp.c @@ -24,6 +24,7 @@ #include "sim/callback.h" #include "sim-main.h" #include "sim-options.h" +#include "target-newlib-syscall.h" void sim_engine_run (SIM_DESC sd, @@ -69,6 +70,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback, STATE_MACHS (sd) = riscv_sim_machs; STATE_MODEL_NAME (sd) = WITH_TARGET_WORD_BITSIZE == 32 ? "RV32G" : "RV64G"; current_target_byte_order = BFD_ENDIAN_LITTLE; + callback->syscall_map = cb_riscv_syscall_map; /* The cpu data is kept in a separately allocated chunk of memory. */ if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK) -- 2.33.0