From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by sourceware.org (Postfix) with ESMTPS id 22A03385E44C for ; Fri, 14 Jan 2022 16:37:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 22A03385E44C Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20EAbLt0006957 for ; Fri, 14 Jan 2022 17:37:57 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3dk3vyk7kr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 14 Jan 2022 17:37:57 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 98E55100038 for ; Fri, 14 Jan 2022 17:37:56 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9281C2194E3 for ; Fri, 14 Jan 2022 17:37:56 +0100 (CET) Received: from gnx2104.gnb.st.com (10.75.127.51) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Fri, 14 Jan 2022 17:37:56 +0100 From: Christophe Lyon To: CC: , Christophe Lyon Subject: [PATCH 3/5] gdb/arm: Introduce arm_cache_init Date: Fri, 14 Jan 2022 17:35:30 +0100 Message-ID: <20220114163552.4107885-3-christophe.lyon@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220114163552.4107885-1-christophe.lyon@foss.st.com> References: <20220114163552.4107885-1-christophe.lyon@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.75.127.51] X-ClientProxiedBy: SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-14_06,2022-01-14_01,2021-12-02_01 X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 14 Jan 2022 16:38:00 -0000 This patch is a preparation for the rest of the series and adds two arm_cache_init helper functions. It updates every place that updates cache->saved_regs to call the helper instead. --- gdb/arm-tdep.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index b6a1deafad5..a345df959d1 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -290,6 +290,23 @@ struct arm_prologue_cache trad_frame_saved_reg *saved_regs; }; +static void +arm_cache_init (struct arm_prologue_cache *cache, struct gdbarch *gdbarch) +{ + cache->framesize = 0; + cache->framereg = 0; + cache->saved_regs = trad_frame_alloc_saved_regs (gdbarch); +} + +static void +arm_cache_init (struct arm_prologue_cache *cache, struct frame_info *frame) +{ + struct gdbarch *gdbarch = get_frame_arch (frame); + cache->prev_sp = get_frame_register_unsigned (frame, ARM_SP_REGNUM); + + arm_cache_init (cache, gdbarch); +} + namespace { /* Abstract class to read ARM instructions from memory. */ @@ -1922,7 +1939,7 @@ arm_make_prologue_cache (struct frame_info *this_frame) CORE_ADDR unwound_fp; cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); - cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); + arm_cache_init (cache, this_frame); arm_scan_prologue (this_frame, cache); @@ -2388,7 +2405,7 @@ arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry) struct arm_prologue_cache *cache; cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); - cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); + arm_cache_init (cache, this_frame); for (;;) { @@ -2782,7 +2799,7 @@ arm_make_epilogue_frame_cache (struct frame_info *this_frame) int reg; cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); - cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); + arm_cache_init (cache, this_frame); /* Still rely on the offset calculated from prologue. */ arm_scan_prologue (this_frame, cache); @@ -2943,7 +2960,7 @@ arm_make_stub_cache (struct frame_info *this_frame) struct arm_prologue_cache *cache; cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); - cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); + arm_cache_init (cache, this_frame); cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); @@ -3020,7 +3037,7 @@ arm_m_exception_cache (struct frame_info *this_frame) uint32_t secure_stack_used; cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache); - cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); + arm_cache_init (cache, this_frame); /* ARMv7-M Architecture Reference "B1.5.6 Exception entry behavior" describes which bits in LR that define which stack was used prior @@ -13572,7 +13589,7 @@ arm_analyze_prologue_test () test_arm_instruction_reader mem_reader (insns); arm_prologue_cache cache; - cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch); + arm_cache_init (&cache, gdbarch); arm_analyze_prologue (gdbarch, 0, sizeof (insns) - 1, &cache, mem_reader); } -- 2.25.1