From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.baldwin.cx (bigwig.baldwin.cx [IPv6:2607:f138:0:13::2]) by sourceware.org (Postfix) with ESMTPS id A1256385801E for ; Thu, 17 Mar 2022 18:37:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A1256385801E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=FreeBSD.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=FreeBSD.org Received: from ralph.com (ralph.baldwin.cx [66.234.199.215]) by mail.baldwin.cx (Postfix) with ESMTPSA id D68191A84C75; Thu, 17 Mar 2022 14:37:31 -0400 (EDT) From: John Baldwin To: gdb-patches@sourceware.org Cc: Willgerodt, Felix Subject: [RFC PATCH v2 1/5] x86: Add an x86_xsave_layout structure to handle variable XSAVE layouts. Date: Thu, 17 Mar 2022 11:35:59 -0700 Message-Id: <20220317183603.34789-2-jhb@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220317183603.34789-1-jhb@FreeBSD.org> References: <20220317183603.34789-1-jhb@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.6.4 (mail.baldwin.cx [0.0.0.0]); Thu, 17 Mar 2022 14:37:32 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.103.1 at mail.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Mar 2022 18:37:34 -0000 The standard layout of the XSAVE extended state area consists of three regions. The first 512 bytes (legacy region) match the layout of the FXSAVE instruction including floating point registers, MMX registers, and SSE registers. The next 64 bytes (XSAVE header) contains a header with a fixed layout. The final region (extended region) contains zero or more optional state components. Examples of these include the upper 128 bits of YMM registers for AVX. These optional state components generally have an architecturally-fixed size, but they are not assigned architectural offsets in the extended region. Instead, processors provide additional CPUID leafs describing the size and offset of each component in the "standard" layout for a given CPU. (There is also a "compact" format which uses an alternate layout, but existing OS's currently export the "standard" layout when exporting XSAVE data via ptrace() and core dumps.) To date, GDB has assumed the layout used on current Intel processors for state components in the extended region and hardcoded those offsets in the tables in i387-tdep.c and i387-fp.cc. However, this fails on recent AMD processors which use a different layout. Specifically, AMD Ryzen 9 processors at least do not leave space for the MPX register set in between the AVX and AVX512 register sets. It is not known if other AMD processors are effected, but seems probable. To rectify this, add an x86_xsave_layout structure which contains the total size of the XSAVE extended state area as well as the offset of each known optional state component. This structure is stored in i386_gdbarch_tdep and is fetched from the current target in i386_gdbarch_init as a TARGET_OBJECT_X86_XSAVE_LAYOUT object. Subsequent commits will modify XSAVE parsing to use x86_xsave_layout. --- gdb/i386-tdep.c | 36 +++++++++++++++++++++++++++++++++++- gdb/i386-tdep.h | 30 ++++++++++++++++++++++++++++++ gdb/target.h | 2 ++ 3 files changed, 67 insertions(+), 1 deletion(-) diff --git a/gdb/i386-tdep.c b/gdb/i386-tdep.c index b98f4757499..0fe7431cef1 100644 --- a/gdb/i386-tdep.c +++ b/gdb/i386-tdep.c @@ -8446,6 +8446,21 @@ i386_type_align (struct gdbarch *gdbarch, struct type *type) } +/* Fetch the XSAVE layout for the current target. */ + +static struct x86_xsave_layout +i386_fetch_xsave_layout () +{ + struct x86_xsave_layout layout; + LONGEST len = target_read (current_inferior ()->top_target (), + TARGET_OBJECT_X86_XSAVE_LAYOUT, nullptr, + (gdb_byte *) &layout, 0, sizeof (layout)); + if (len != sizeof (layout)) + return {}; + + return layout; +} + /* Note: This is called for both i386 and amd64. */ static struct gdbarch * @@ -8453,13 +8468,30 @@ i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) { struct gdbarch *gdbarch; const struct target_desc *tdesc; + struct x86_xsave_layout xsave_layout; int mm0_regnum; int ymm0_regnum; int bnd0_regnum; int num_bnd_cooked; + xsave_layout = i386_fetch_xsave_layout (); + /* If there is already a candidate, use it. */ - arches = gdbarch_list_lookup_by_info (arches, &info); + for (arches = gdbarch_list_lookup_by_info (arches, &info); + arches != NULL; + arches = gdbarch_list_lookup_by_info (arches->next, &info)) + { + /* Check that the XSAVE layout of ARCHES matches the layout for + the current target. */ + i386_gdbarch_tdep *other_tdep + = (i386_gdbarch_tdep *) gdbarch_tdep (arches->gdbarch); + + if (other_tdep->xsave_layout != xsave_layout) + continue; + + break; + } + if (arches != NULL) return arches->gdbarch; @@ -8712,6 +8744,8 @@ i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) gdbarch_free (gdbarch); return NULL; } + if (tdep->xcr0 != 0) + tdep->xsave_layout = xsave_layout; num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0); diff --git a/gdb/i386-tdep.h b/gdb/i386-tdep.h index eb58dd68e73..0034660c9f7 100644 --- a/gdb/i386-tdep.h +++ b/gdb/i386-tdep.h @@ -56,6 +56,34 @@ enum struct_return reg_struct_return /* Return "short" structures in registers. */ }; +/* Size and offsets of register states in the XSAVE area extended + region. Offsets are set to 0 to indicate the absence of the + associated registers. */ + +struct x86_xsave_layout +{ + int sizeof_xsave = 0; + int avx_offset = 0; + int bndregs_offset = 0; + int bndcfg_offset = 0; + int avx512_k_offset = 0; + int avx512_zmm_h_offset = 0; + int avx512_zmm_offset = 0; + int pkru_offset = 0; + + bool operator!= (const x86_xsave_layout &other) + { + return sizeof_xsave != other.sizeof_xsave + || avx_offset != other.avx_offset + || bndregs_offset != other.bndregs_offset + || bndcfg_offset != other.bndcfg_offset + || avx512_k_offset != other.avx512_k_offset + || avx512_zmm_h_offset != other.avx512_zmm_h_offset + || avx512_zmm_offset != other.avx512_zmm_offset + || pkru_offset != other.pkru_offset; + } +}; + /* i386 architecture specific information. */ struct i386_gdbarch_tdep : gdbarch_tdep { @@ -145,6 +173,8 @@ struct i386_gdbarch_tdep : gdbarch_tdep /* Offset of XCR0 in XSAVE extended state. */ int xsave_xcr0_offset = 0; + x86_xsave_layout xsave_layout; + /* Register names. */ const char * const *register_names = nullptr; diff --git a/gdb/target.h b/gdb/target.h index 4cc79df05b4..4298ae2ccf8 100644 --- a/gdb/target.h +++ b/gdb/target.h @@ -204,6 +204,8 @@ enum target_object TARGET_OBJECT_FREEBSD_VMMAP, /* FreeBSD process strings. */ TARGET_OBJECT_FREEBSD_PS_STRINGS, + /* x86 XSAVE area layout. */ + TARGET_OBJECT_X86_XSAVE_LAYOUT, /* Possible future objects: TARGET_OBJECT_FILE, ... */ }; -- 2.34.1