From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.baldwin.cx (bigwig.baldwin.cx [IPv6:2607:f138:0:13::2]) by sourceware.org (Postfix) with ESMTPS id D13A53888C46; Wed, 23 Mar 2022 21:00:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D13A53888C46 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=FreeBSD.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=FreeBSD.org Received: from ralph.com (ralph.baldwin.cx [66.234.199.215]) by mail.baldwin.cx (Postfix) with ESMTPSA id 292681A84E63; Wed, 23 Mar 2022 17:00:57 -0400 (EDT) From: John Baldwin To: binutils@sourceware.org, gdb-patches@sourceware.org Subject: [PATCH 05/12] Read the tpidruro register from NT_ARM_TLS core dump notes on FreeBSD/arm. Date: Wed, 23 Mar 2022 14:00:44 -0700 Message-Id: <20220323210048.25525-6-jhb@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220323210048.25525-1-jhb@FreeBSD.org> References: <20220323210048.25525-1-jhb@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.6.4 (mail.baldwin.cx [0.0.0.0]); Wed, 23 Mar 2022 17:00:57 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.103.1 at mail.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Mar 2022 21:00:59 -0000 --- gdb/arm-fbsd-nat.c | 2 +- gdb/arm-fbsd-tdep.c | 28 ++++++++++++++++++++++------ gdb/arm-fbsd-tdep.h | 6 +++++- 3 files changed, 28 insertions(+), 8 deletions(-) diff --git a/gdb/arm-fbsd-nat.c b/gdb/arm-fbsd-nat.c index 3106d73cc3a..c32924de735 100644 --- a/gdb/arm-fbsd-nat.c +++ b/gdb/arm-fbsd-nat.c @@ -72,7 +72,7 @@ arm_fbsd_nat_target::read_description () { const struct target_desc *desc; - desc = arm_fbsd_read_description_auxv (this); + desc = arm_fbsd_read_description_auxv (this, false); if (desc == NULL) desc = this->beneath ()->read_description (); return desc; diff --git a/gdb/arm-fbsd-tdep.c b/gdb/arm-fbsd-tdep.c index 06745a36186..e11b17664eb 100644 --- a/gdb/arm-fbsd-tdep.c +++ b/gdb/arm-fbsd-tdep.c @@ -44,6 +44,12 @@ static const struct regcache_map_entry arm_fbsd_gregmap[] = { 0 } }; +static const struct regcache_map_entry arm_fbsd_tlsregmap[] = + { + { 1, ARM_TPIDRURO_REGNUM, 4 }, + { 0 } + }; + static const struct regcache_map_entry arm_fbsd_vfpregmap[] = { { 32, ARM_D0_REGNUM, 8 }, /* d0 ... d31 */ @@ -144,6 +150,12 @@ const struct regset arm_fbsd_gregset = regcache_supply_regset, regcache_collect_regset }; +const struct regset arm_fbsd_tlsregset = + { + arm_fbsd_tlsregmap, + regcache_supply_regset, regcache_collect_regset + }; + const struct regset arm_fbsd_vfpregset = { arm_fbsd_vfpregmap, @@ -162,6 +174,8 @@ arm_fbsd_iterate_over_regset_sections (struct gdbarch *gdbarch, cb (".reg", ARM_FBSD_SIZEOF_GREGSET, ARM_FBSD_SIZEOF_GREGSET, &arm_fbsd_gregset, NULL, cb_data); + cb (".reg-aarch-tls", ARM_FBSD_SIZEOF_TLSREGSET, ARM_FBSD_SIZEOF_TLSREGSET, + &arm_fbsd_tlsregset, NULL, cb_data); /* While FreeBSD/arm cores do contain a NT_FPREGSET / ".reg2" register set, it is not populated with register values by the @@ -175,12 +189,12 @@ arm_fbsd_iterate_over_regset_sections (struct gdbarch *gdbarch, vector. */ const struct target_desc * -arm_fbsd_read_description_auxv (struct target_ops *target) +arm_fbsd_read_description_auxv (struct target_ops *target, bool tls) { CORE_ADDR arm_hwcap = 0; if (target_auxv_search (target, AT_FREEBSD_HWCAP, &arm_hwcap) != 1) - return nullptr; + return arm_read_description (ARM_FP_TYPE_NONE, tls); if (arm_hwcap & HWCAP_VFP) { @@ -188,12 +202,12 @@ arm_fbsd_read_description_auxv (struct target_ops *target) return aarch32_read_description (); else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPD32)) == (HWCAP_VFPv3 | HWCAP_VFPD32)) - return arm_read_description (ARM_FP_TYPE_VFPV3, false); + return arm_read_description (ARM_FP_TYPE_VFPV3, tls); else - return arm_read_description (ARM_FP_TYPE_VFPV2, false); + return arm_read_description (ARM_FP_TYPE_VFPV2, tls); } - return nullptr; + return arm_read_description (ARM_FP_TYPE_NONE, tls); } /* Implement the "core_read_description" gdbarch method. */ @@ -203,7 +217,9 @@ arm_fbsd_core_read_description (struct gdbarch *gdbarch, struct target_ops *target, bfd *abfd) { - return arm_fbsd_read_description_auxv (target); + asection *tls = bfd_get_section_by_name (abfd, ".reg-aarch-tls"); + + return arm_fbsd_read_description_auxv (target, tls != nullptr); } /* Implement the 'init_osabi' method of struct gdb_osabi_handler. */ diff --git a/gdb/arm-fbsd-tdep.h b/gdb/arm-fbsd-tdep.h index 633dafad75d..00b55cf5bd0 100644 --- a/gdb/arm-fbsd-tdep.h +++ b/gdb/arm-fbsd-tdep.h @@ -26,11 +26,15 @@ PC, and CPSR registers. */ #define ARM_FBSD_SIZEOF_GREGSET (17 * 4) +/* The TLS regset consists of a single register. */ +#define ARM_FBSD_SIZEOF_TLSREGSET (4) + /* The VFP regset consists of 32 D registers plus FPSCR, and the whole structure is padded to 64-bit alignment. */ #define ARM_FBSD_SIZEOF_VFPREGSET (33 * 8) extern const struct regset arm_fbsd_gregset; +extern const struct regset arm_fbsd_tlsregset; extern const struct regset arm_fbsd_vfpregset; /* Flags passed in AT_HWCAP. */ @@ -40,6 +44,6 @@ extern const struct regset arm_fbsd_vfpregset; #define HWCAP_VFPD32 0x00080000 extern const struct target_desc * -arm_fbsd_read_description_auxv (struct target_ops *target); +arm_fbsd_read_description_auxv (struct target_ops *target, bool tls); #endif /* ARM_FBSD_TDEP_H */ -- 2.34.1