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From: Christophe Lyon <christophe.lyon@arm.com>
To: <gdb-patches@sourceware.org>
Cc: <torbjorn.svensson@st.com>, <yvan.roux@foss.st.com>,
	Christophe Lyon <christophe.lyon@foss.st.com>,
	Christophe Lyon <christophe.lyon@arm.com>
Subject: [PATCH v4 1/5] gdb/arm: Fix prologue analysis to support vpush
Date: Fri, 1 Apr 2022 11:18:10 +0200	[thread overview]
Message-ID: <20220401091814.2782327-2-christophe.lyon@arm.com> (raw)
In-Reply-To: <20220401091814.2782327-1-christophe.lyon@arm.com>

From: Christophe Lyon <christophe.lyon@foss.st.com>

While working on adding support for Non-secure/Secure modes unwinding,
I noticed that the prologue analysis lacked support for vpush, which
is used for instance in the CMSE stub routine.

This patch updates thumb_analyze_prologue accordingly, adding support
for vpush of D-registers.

Signed-off-by: Christophe Lyon <christophe.lyon@foss.st.com>
Signed-off-by: Christophe Lyon <christophe.lyon@arm.com>
---
 gdb/arm-tdep.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index d36856e1f3b..9e623057e4a 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -896,6 +896,35 @@ thumb_analyze_prologue (struct gdbarch *gdbarch,
 		regs[bits (insn, 0, 3)] = addr;
 	    }
 
+	  /* vstmdb Rn{!}, { D-registers } (aka vpush).  */
+	  else if ((insn & 0xff20) == 0xed20
+		   && (inst2 & 0x0f00) == 0x0b00
+		   && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
+	    {
+	      /* Address SP points to.  */
+	      pv_t addr = regs[bits (insn, 0, 3)];
+
+	      /* Number of registers saved.  */
+	      unsigned int number = bits (inst2, 0, 7) >> 1;
+
+	      /* First register to save.  */
+	      int vd = bits (inst2, 12, 15) | (bits (insn, 6, 6) << 4);
+
+	      if (stack.store_would_trash (addr))
+		break;
+
+	      /* Calculate offsets of saved registers.  */
+	      for (; number > 0; number--)
+		{
+		  addr = pv_add_constant (addr, -8);
+		  stack.store (addr, 8, pv_register (ARM_D0_REGNUM
+						     + vd + number, 0));
+		}
+
+	      /* Writeback SP to account for the saved registers.  */
+	      regs[bits (insn, 0, 3)] = addr;
+	    }
+
 	  else if ((insn & 0xff50) == 0xe940	/* strd Rt, Rt2,
 						   [Rn, #+/-imm]{!} */
 		   && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM))
-- 
2.17.1


  reply	other threads:[~2022-04-01  9:19 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-01  9:18 [PATCH v4 0/5] arm: Add support for multiple stacks on Cortex-M Christophe Lyon
2022-04-01  9:18 ` Christophe Lyon [this message]
2022-04-01  9:18 ` [PATCH v4 2/5] gdb/arm: Define MSP and PSP registers for M-Profile Christophe Lyon
2022-04-01  9:18 ` [PATCH v4 3/5] gdb/arm: Introduce arm_cache_init Christophe Lyon
2022-04-01  9:18 ` [PATCH v4 4/5] gdb/arm: Add support for multiple stack pointers on Cortex-M Christophe Lyon
2022-04-01  9:18 ` [PATCH v4 5/5] gdb/arm: Extend arm_m_addr_is_magic to support FNC_RETURN, add unwind-ns-to-s command Christophe Lyon
2022-04-01  9:33 ` [PATCH v4 0/5] arm: Add support for multiple stacks on Cortex-M Christophe Lyon
  -- strict thread matches above, loose matches on Subject: below --
2022-04-01  9:16 Christophe Lyon
2022-04-01  9:16 ` [PATCH v4 1/5] gdb/arm: Fix prologue analysis to support vpush Christophe Lyon

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