From: Christophe Lyon <christophe.lyon@arm.com>
To: <gdb-patches@sourceware.org>
Cc: <torbjorn.svensson@st.com>, <yvan.roux@foss.st.com>,
Christophe Lyon <christophe.lyon@foss.st.com>,
Christophe Lyon <christophe.lyon@arm.com>
Subject: [PATCH v4 3/5] gdb/arm: Introduce arm_cache_init
Date: Fri, 1 Apr 2022 11:18:12 +0200 [thread overview]
Message-ID: <20220401091814.2782327-4-christophe.lyon@arm.com> (raw)
In-Reply-To: <20220401091814.2782327-1-christophe.lyon@arm.com>
From: Christophe Lyon <christophe.lyon@foss.st.com>
This patch is a preparation for the rest of the series and adds two
arm_cache_init helper functions. It updates every place that updates
cache->saved_regs to call the helper instead.
Signed-off-by: Torbjörn Svensson <torbjorn.svensson@st.com>
Signed-off-by: Christophe Lyon <christophe.lyon@foss.st.com>
Signed-off-by: Christophe Lyon <christophe.lyon@arm.com>
---
gdb/arm-tdep.c | 32 ++++++++++++++++++++++++++------
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 5faab6b6da6..0e442e64b36 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -290,6 +290,25 @@ struct arm_prologue_cache
trad_frame_saved_reg *saved_regs;
};
+/* Initialize CACHE fields for which zero is not adequate (CACHE is
+ expected to have been ZALLOC'ed before calling this function). */
+
+static void
+arm_cache_init (struct arm_prologue_cache *cache, struct gdbarch *gdbarch)
+{
+ cache->saved_regs = trad_frame_alloc_saved_regs (gdbarch);
+}
+
+/* Similar to the previous function, but extracts GDBARCH from FRAME. */
+
+static void
+arm_cache_init (struct arm_prologue_cache *cache, struct frame_info *frame)
+{
+ struct gdbarch *gdbarch = get_frame_arch (frame);
+
+ arm_cache_init (cache, gdbarch);
+}
+
namespace {
/* Abstract class to read ARM instructions from memory. */
@@ -1930,7 +1949,7 @@ arm_make_prologue_cache (struct frame_info *this_frame)
CORE_ADDR unwound_fp;
cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
- cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
+ arm_cache_init (cache, this_frame);
arm_scan_prologue (this_frame, cache);
@@ -2396,7 +2415,7 @@ arm_exidx_fill_cache (struct frame_info *this_frame, gdb_byte *entry)
struct arm_prologue_cache *cache;
cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
- cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
+ arm_cache_init (cache, this_frame);
for (;;)
{
@@ -2790,7 +2809,7 @@ arm_make_epilogue_frame_cache (struct frame_info *this_frame)
int reg;
cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
- cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
+ arm_cache_init (cache, this_frame);
/* Still rely on the offset calculated from prologue. */
arm_scan_prologue (this_frame, cache);
@@ -2951,7 +2970,7 @@ arm_make_stub_cache (struct frame_info *this_frame)
struct arm_prologue_cache *cache;
cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
- cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
+ arm_cache_init (cache, this_frame);
cache->prev_sp = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
@@ -3029,7 +3048,7 @@ arm_m_exception_cache (struct frame_info *this_frame)
uint32_t secure_stack_used;
cache = FRAME_OBSTACK_ZALLOC (struct arm_prologue_cache);
- cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
+ arm_cache_init (cache, this_frame);
/* ARMv7-M Architecture Reference "B1.5.6 Exception entry behavior"
describes which bits in LR that define which stack was used prior
@@ -13621,7 +13640,8 @@ arm_analyze_prologue_test ()
test_arm_instruction_reader mem_reader (insns);
arm_prologue_cache cache;
- cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch);
+ memset (&cache, 0, sizeof (arm_prologue_cache));
+ arm_cache_init (&cache, gdbarch);
arm_analyze_prologue (gdbarch, 0, sizeof (insns) - 1, &cache, mem_reader);
}
--
2.17.1
next prev parent reply other threads:[~2022-04-01 9:18 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-01 9:18 [PATCH v4 0/5] arm: Add support for multiple stacks on Cortex-M Christophe Lyon
2022-04-01 9:18 ` [PATCH v4 1/5] gdb/arm: Fix prologue analysis to support vpush Christophe Lyon
2022-04-01 9:18 ` [PATCH v4 2/5] gdb/arm: Define MSP and PSP registers for M-Profile Christophe Lyon
2022-04-01 9:18 ` Christophe Lyon [this message]
2022-04-01 9:18 ` [PATCH v4 4/5] gdb/arm: Add support for multiple stack pointers on Cortex-M Christophe Lyon
2022-04-01 9:18 ` [PATCH v4 5/5] gdb/arm: Extend arm_m_addr_is_magic to support FNC_RETURN, add unwind-ns-to-s command Christophe Lyon
2022-04-01 9:33 ` [PATCH v4 0/5] arm: Add support for multiple stacks on Cortex-M Christophe Lyon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220401091814.2782327-4-christophe.lyon@arm.com \
--to=christophe.lyon@arm.com \
--cc=christophe.lyon@foss.st.com \
--cc=gdb-patches@sourceware.org \
--cc=torbjorn.svensson@st.com \
--cc=yvan.roux@foss.st.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).