From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.baldwin.cx (bigwig.baldwin.cx [66.216.25.90]) by sourceware.org (Postfix) with ESMTPS id 7FFCB3857C46 for ; Tue, 12 Apr 2022 23:48:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7FFCB3857C46 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=FreeBSD.org Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=FreeBSD.org Received: from ralph.com (ralph.baldwin.cx [66.234.199.215]) by mail.baldwin.cx (Postfix) with ESMTPSA id E6D631A84E35 for ; Tue, 12 Apr 2022 19:48:14 -0400 (EDT) From: John Baldwin To: gdb-patches@sourceware.org Subject: [PATCH v2 12/14] Read the tpidr register from NT_ARM_TLS core dump notes on Linux Aarch64. Date: Tue, 12 Apr 2022 16:46:45 -0700 Message-Id: <20220412234647.84595-13-jhb@FreeBSD.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220412234647.84595-1-jhb@FreeBSD.org> References: <20220412234647.84595-1-jhb@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.6.4 (mail.baldwin.cx [0.0.0.0]); Tue, 12 Apr 2022 19:48:15 -0400 (EDT) X-Virus-Scanned: clamav-milter 0.103.1 at mail.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_SOFTFAIL, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Apr 2022 23:48:16 -0000 --- gdb/aarch64-linux-tdep.c | 20 +++++++++++++++++++- gdb/aarch64-linux-tdep.h | 4 ++++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c index 8cfb64d9f4a..e29b29523bb 100644 --- a/gdb/aarch64-linux-tdep.c +++ b/gdb/aarch64-linux-tdep.c @@ -479,6 +479,12 @@ static const struct regcache_map_entry aarch64_linux_fpregmap[] = { 0 } }; +static const struct regcache_map_entry aarch64_linux_tls_regmap[] = + { + { 1, AARCH64_TPIDR_REGNUM, 8 }, + { 0 } + }; + /* Register set definitions. */ const struct regset aarch64_linux_gregset = @@ -493,6 +499,12 @@ const struct regset aarch64_linux_fpregset = regcache_supply_regset, regcache_collect_regset }; +const struct regset aarch64_linux_tls_regset = + { + aarch64_linux_tls_regmap, + regcache_supply_regset, regcache_collect_regset + }; + /* The fields in an SVE header at the start of a SVE regset. */ #define SVE_HEADER_SIZE_LENGTH 4 @@ -749,6 +761,11 @@ aarch64_linux_iterate_over_regset_sections (struct gdbarch *gdbarch, AARCH64_LINUX_SIZEOF_MTE_REGSET, &aarch64_linux_mte_regset, "MTE registers", cb_data); } + + if (tdep->has_tls ()) + cb (".reg-aarch-tls", AARCH64_LINUX_SIZEOF_TLSREGSET, + AARCH64_LINUX_SIZEOF_TLSREGSET, &aarch64_linux_tls_regset, + "TLS register", cb_data); } /* Implement the "core_read_description" gdbarch method. */ @@ -757,13 +774,14 @@ static const struct target_desc * aarch64_linux_core_read_description (struct gdbarch *gdbarch, struct target_ops *target, bfd *abfd) { + asection *tls = bfd_get_section_by_name (abfd, ".reg-aarch-tls"); CORE_ADDR hwcap = linux_get_hwcap (target); CORE_ADDR hwcap2 = linux_get_hwcap2 (target); bool pauth_p = hwcap & AARCH64_HWCAP_PACA; bool mte_p = hwcap2 & HWCAP2_MTE; return aarch64_read_description (aarch64_linux_core_read_vq (gdbarch, abfd), - pauth_p, mte_p, false); + pauth_p, mte_p, tls != nullptr); } /* Implementation of `gdbarch_stap_is_single_operand', as defined in diff --git a/gdb/aarch64-linux-tdep.h b/gdb/aarch64-linux-tdep.h index 8ae33efc605..6f5a671cb6e 100644 --- a/gdb/aarch64-linux-tdep.h +++ b/gdb/aarch64-linux-tdep.h @@ -39,8 +39,12 @@ /* The MTE regset consists of a 64-bit register. */ #define AARCH64_LINUX_SIZEOF_MTE_REGSET (8) +/* The TLS regset consists of a single register. */ +#define AARCH64_LINUX_SIZEOF_TLSREGSET (X_REGISTER_SIZE) + extern const struct regset aarch64_linux_gregset; extern const struct regset aarch64_linux_fpregset; +extern const struct regset aarch64_linux_tls_regset; /* Matches HWCAP_PACA in kernel header arch/arm64/include/uapi/asm/hwcap.h. */ #define AARCH64_HWCAP_PACA (1 << 30) -- 2.34.1