From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id 03C9F3952522 for ; Fri, 6 May 2022 12:13:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 03C9F3952522 X-IronPort-AV: E=McAfee;i="6400,9594,10338"; a="250450231" X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="250450231" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2022 05:13:01 -0700 X-IronPort-AV: E=Sophos;i="5.91,203,1647327600"; d="scan'208";a="812365862" Received: from mulvlfelix.iul.intel.com (HELO localhost) ([172.28.48.92]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2022 05:13:00 -0700 From: Felix Willgerodt To: gdb-patches@sourceware.org Subject: [PATCH 4/4] gdb: Clear tilecfg.start_row for any PC modification. Date: Fri, 6 May 2022 14:12:26 +0200 Message-Id: <20220506121226.137608-5-felix.willgerodt@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506121226.137608-1-felix.willgerodt@intel.com> References: <20220506121226.137608-1-felix.willgerodt@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SCC_10_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 May 2022 12:13:05 -0000 AMX tile instructions are restartable, e.g. on faults. Tilecfg.start_row is used to restart the interrupted instructions at the right row. On inferior calls, jumps or any other PC modification, start_row needs to be reset. It binds to the current instruction and not to the one we would start executing next in these cases. --- gdb/amd64-linux-tdep.c | 24 ++++ gdb/testsuite/gdb.arch/amd64-amx-startrow.c | 122 ++++++++++++++++++ gdb/testsuite/gdb.arch/amd64-amx-startrow.exp | 91 +++++++++++++ 3 files changed, 237 insertions(+) create mode 100644 gdb/testsuite/gdb.arch/amd64-amx-startrow.c create mode 100755 gdb/testsuite/gdb.arch/amd64-amx-startrow.exp diff --git a/gdb/amd64-linux-tdep.c b/gdb/amd64-linux-tdep.c index cda90de54c6..65cce7f36ed 100644 --- a/gdb/amd64-linux-tdep.c +++ b/gdb/amd64-linux-tdep.c @@ -314,6 +314,30 @@ amd64_linux_write_pc (struct regcache *regcache, CORE_ADDR pc) within GDB. In all other cases the system call will not be restarted. */ regcache_cooked_write_unsigned (regcache, AMD64_LINUX_ORIG_RAX_REGNUM, -1); + + /* If we have interrupted a restart-able AMX instruction we should clear + start_row. Any instructions we will now run should start at row 0. */ + i386_gdbarch_tdep *tdep + = (i386_gdbarch_tdep *) gdbarch_tdep (regcache->arch ()); + if (tdep != nullptr && tdep->tilecfg_raw_regnum != -1) + { + gdb_byte tilecfg_buf[register_size (regcache->arch (), + tdep->tilecfg_raw_regnum)]; + + if (regcache->raw_read (tdep->tilecfg_raw_regnum, tilecfg_buf) + != REG_VALID) + { + warning (_ ("Could not reset $tilecfg.start_row.")); + return; + } + + /* start_row is the second byte. */ + if (tilecfg_buf[1] != 0) + { + tilecfg_buf[1] = 0; + regcache->raw_write (AMD64_AMX_TILECFG_RAW_REGNUM, tilecfg_buf); + } + } } /* Record all registers but IP register for process-record. */ diff --git a/gdb/testsuite/gdb.arch/amd64-amx-startrow.c b/gdb/testsuite/gdb.arch/amd64-amx-startrow.c new file mode 100644 index 00000000000..00650ac5683 --- /dev/null +++ b/gdb/testsuite/gdb.arch/amd64-amx-startrow.c @@ -0,0 +1,122 @@ +/* Test program for AMX startrow. + + Copyright 2022 Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define XFEATURE_XTILEDATA 18 +#define ARCH_REQ_XCOMP_PERM 0x1023 + +/* To test infcalls. */ +int +square (int a, int b) +{ + int tmp; + tmp = a * b; /* BP2. */ + return tmp; +} + +int +main (int argc, char **argv) +{ + /* Ask the OS to configure AMX in xsave. */ + if (syscall (SYS_arch_prctl, ARCH_REQ_XCOMP_PERM, XFEATURE_XTILEDATA) != 0) + return -1; + + /* Configure tiles. */ + struct tileconfig_t + { + uint8_t palette_id; + uint8_t startRow; + uint8_t reserved[14]; + uint16_t cols[16]; + uint8_t rows[16]; + }; + + const int tmm0 = 0; + + struct tileconfig_t tc = { 1 }; + + tc.rows[tmm0] = 16; + tc.cols[tmm0] = 64; + + _tile_loadconfig (&tc); + + const uint32_t memA1[16][16] + = { { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, + { 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 }, + { 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47 }, + { 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }, + { 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79 }, + { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95 }, + { 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, + 110, 111 }, + { 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, + 125, 126, 127 }, + { 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, + 141, 142, 143 }, + { 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, + 157, 158, 159 }, + { 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, + 173, 174, 175 }, + { 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, + 189, 190, 191 }, + { 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, + 205, 206, 207 }, + { 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, + 221, 222, 223 }, + { 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, + 237, 238, 239 }, + { 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, + 253, 254, 255 } }; + + /* Load tile that is stored over a page boundary. */ + const long page_size = sysconf (_SC_PAGESIZE); + if (page_size == -1) + return -1; + + void *p; + int ret = posix_memalign (&p, page_size, 2 * page_size); + if (ret != 0) + return -1; + + void *p2 = p + page_size; + + memmove (p2 - 512, memA1, sizeof (memA1)); + + /* Protect the second page to produce a fault. */ + if (mprotect (p2, page_size, PROT_NONE) == -1) + return -1; + + _tile_loadd (tmm0, p2 - 512, 64); /* BP1. */ + + square (2, 2); /* Jump. */ + free (p); + return 0; +} diff --git a/gdb/testsuite/gdb.arch/amd64-amx-startrow.exp b/gdb/testsuite/gdb.arch/amd64-amx-startrow.exp new file mode 100755 index 00000000000..201d4aaf767 --- /dev/null +++ b/gdb/testsuite/gdb.arch/amd64-amx-startrow.exp @@ -0,0 +1,91 @@ +# Copyright 2022 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +# This file tests clearing of tilecfg.startrow in case it isn't empty. +# If there is a fault, tileload and store instructions can be interrupted. +# In that case startrow will point to the row on which they should be +# continued. In that case, inferior calls and jump commands should clear it. +# This is tested by placing a tile over two memory pages, creating a page +# fault. Watchpoints that have hit will be delivered before the page fault. + +if { [skip_amx_tests] } { + unsupported "Target does not support AMX." + return -1 +} + +standard_testfile + +if { [prepare_for_testing "failed to prepare" ${testfile} ${srcfile} debug] } { + return -1 +} + +proc test_startrow {test} { + global gdb_prompt hex decimal srcfile + + if { ![runto_main] } { + untested "could not run to main" + return -1 + } + + set line1 [gdb_get_line_number "BP1"] + set line2 [gdb_get_line_number "BP2"] + set line_jump [gdb_get_line_number "Jump"] + gdb_breakpoint $line1 + gdb_breakpoint $line2 + + gdb_continue_to_breakpoint "line1" ".*$srcfile:$line1.*" + + # Set a watchpoint on the first page, which is un-protected. + set watch_addr 0 + gdb_test_multiple "p/x p2 - 8" "get watch_addr" { + -re -wrap "= ($hex)" { + set watch_addr $expect_out(1,string) + pass $gdb_test_name + } + } + + # If we didn't get a watch_addr, it makes no sense to continue. + if { $watch_addr == 0 } { + return -1 + } + + gdb_test "rwatch *(int*) $watch_addr" \ + "atchpoint $decimal: \\*\\(int\\*\\) $watch_addr" + + gdb_test "continue" \ + "Continuing.*atchpoint $decimal: \\*\\(int\\*\\) $watch_addr.*" + + gdb_test "p \$tilecfg.start_row" "= \[1-9\]+" "print non-zero start_row" + + if { $test == "jump" } { + # Test jump. + gdb_test "jump $line_jump" "Breakpoint $decimal, .*$srcfile:$line2.*" + gdb_test "p \$tilecfg.start_row" "= 0" + } else { + # Test infcall. + gdb_test "p square (2, 2)" "Breakpoint $decimal, .*$srcfile:$line2.*" + gdb_test "p \$tilecfg.start_row" "= 0" + } +} + +with_test_prefix "infcall" { + test_startrow "" +} + +clean_restart $binfile + +with_test_prefix "jump" { + test_startrow "jump" +} -- 2.34.1 Intel Deutschland GmbH Registered Address: Am Campeon 10, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Christin Eisenschmid, Sharon Heck, Tiffany Doon Silva Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928