From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by sourceware.org (Postfix) with ESMTPS id 87C2D3840C15 for ; Mon, 16 May 2022 14:00:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 87C2D3840C15 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 24GC7wpl017719 for ; Mon, 16 May 2022 16:00:24 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3g21j8khfn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 16 May 2022 16:00:24 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 19822100034 for ; Mon, 16 May 2022 16:00:24 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 12BAD2291DD for ; Mon, 16 May 2022 16:00:24 +0200 (CEST) Received: from gnbcxd0114.gnb.st.com (10.75.127.45) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Mon, 16 May 2022 16:00:23 +0200 Date: Mon, 16 May 2022 16:00:22 +0200 From: Yvan Roux To: CC: Torbjorn Svensson Subject: [PATCH 3/3] gdb/arm: Track msp and psp Message-ID: <20220516140022.GD27993@gnbcxd0114.gnb.st.com> References: <20220516135454.GA27993@gnbcxd0114.gnb.st.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220516135454.GA27993@gnbcxd0114.gnb.st.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-16_13,2022-05-16_02,2022-02-23_01 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 May 2022 14:00:31 -0000 For Arm Cortex-M33 with security extensions, there are 4 different stacks pointers (msp_s, msp_ns, psp_s, psp_ns). To be compatible with earlier Cortex-M derivates, the msp and psp register are aliases for one of the 4 real stack pointer registers. These are the combinations that exist: sp -> msp -> msp_s sp -> msp -> msp_ns sp -> psp -> psp_s sp -> psp -> psp_ns This means that when the GDB client is to show the value of "msp", the value should always be equal to either "msp_s" or "msp_ns". Same goes for "psp". Signed-off-by: Torbjörn SVENSSON Signed-off-by: Yvan Roux --- gdb/arm-tdep.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 4aa277f5bc8..b9c35bcdae6 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -288,6 +288,8 @@ struct arm_prologue_cache /* Active stack pointer. */ int active_sp_regnum; + int active_msp_regnum; + int active_psp_regnum; /* The frame base for this frame is just prev_sp - frame size. FRAMESIZE is the distance from the frame pointer to the @@ -345,11 +347,23 @@ arm_cache_init (struct arm_prologue_cache *cache, struct frame_info *frame) if (tdep->have_sec_ext) { + CORE_ADDR msp_val = get_frame_register_unsigned (frame, tdep->m_profile_msp_regnum); + CORE_ADDR psp_val = get_frame_register_unsigned (frame, tdep->m_profile_psp_regnum); + arm_cache_init_sp (tdep->m_profile_msp_s_regnum, &cache->msp_s, cache, frame); arm_cache_init_sp (tdep->m_profile_psp_s_regnum, &cache->psp_s, cache, frame); arm_cache_init_sp (tdep->m_profile_msp_ns_regnum, &cache->msp_ns, cache, frame); arm_cache_init_sp (tdep->m_profile_psp_ns_regnum, &cache->psp_ns, cache, frame); + if (msp_val == cache->msp_s) + cache->active_msp_regnum = tdep->m_profile_msp_s_regnum; + else if (msp_val == cache->msp_ns) + cache->active_msp_regnum = tdep->m_profile_msp_ns_regnum; + if (psp_val == cache->psp_s) + cache->active_psp_regnum = tdep->m_profile_psp_s_regnum; + else if (psp_val == cache->psp_ns) + cache->active_psp_regnum = tdep->m_profile_psp_ns_regnum; + /* Use MSP_S as default stack pointer. */ if (cache->active_sp_regnum == ARM_SP_REGNUM) cache->active_sp_regnum = tdep->m_profile_msp_s_regnum; @@ -384,6 +398,10 @@ arm_cache_get_sp_register (struct arm_prologue_cache *cache, return cache->psp_s; if (regnum == tdep->m_profile_psp_ns_regnum) return cache->psp_ns; + if (regnum == tdep->m_profile_msp_regnum) + return arm_cache_get_sp_register (cache, tdep, cache->active_msp_regnum); + if (regnum == tdep->m_profile_psp_regnum) + return arm_cache_get_sp_register (cache, tdep, cache->active_psp_regnum); } else if (tdep->is_m) { -- 2.17.1