From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from lndn.lancelotsix.com (vps-42846194.vps.ovh.net [IPv6:2001:41d0:801:2000::2400]) by sourceware.org (Postfix) with ESMTPS id 0EBB5383F408 for ; Mon, 16 May 2022 14:25:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0EBB5383F408 Received: from ubuntu.lan (unknown [IPv6:2a02:390:9086::635]) by lndn.lancelotsix.com (Postfix) with ESMTPSA id E175A86E9D; Mon, 16 May 2022 14:25:18 +0000 (UTC) Date: Mon, 16 May 2022 14:25:13 +0000 From: Lancelot SIX To: Yvan Roux Cc: gdb-patches@sourceware.org, Torbjorn Svensson Subject: Re: [PATCH 3/3] gdb/arm: Track msp and psp Message-ID: <20220516142513.lkn25aummmh2fxnt@ubuntu.lan> References: <20220516135454.GA27993@gnbcxd0114.gnb.st.com> <20220516140022.GD27993@gnbcxd0114.gnb.st.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220516140022.GD27993@gnbcxd0114.gnb.st.com> X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.5.11 (lndn.lancelotsix.com [0.0.0.0]); Mon, 16 May 2022 14:25:19 +0000 (UTC) X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 May 2022 14:25:22 -0000 Hi, I have no knowledge about Arm Cortex-M33 so I cannot comment on the actual changes. I however have a purely code-style related remark down below. On Mon, May 16, 2022 at 04:00:22PM +0200, Yvan Roux via Gdb-patches wrote: > For Arm Cortex-M33 with security extensions, there are 4 different > stacks pointers (msp_s, msp_ns, psp_s, psp_ns). To be compatible > with earlier Cortex-M derivates, the msp and psp register are > aliases for one of the 4 real stack pointer registers. > > These are the combinations that exist: > sp -> msp -> msp_s > sp -> msp -> msp_ns > sp -> psp -> psp_s > sp -> psp -> psp_ns > > This means that when the GDB client is to show the value of "msp", > the value should always be equal to either "msp_s" or "msp_ns". > Same goes for "psp". > > Signed-off-by: Torbjörn SVENSSON > Signed-off-by: Yvan Roux > --- > gdb/arm-tdep.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c > index 4aa277f5bc8..b9c35bcdae6 100644 > --- a/gdb/arm-tdep.c > +++ b/gdb/arm-tdep.c > @@ -288,6 +288,8 @@ struct arm_prologue_cache > > /* Active stack pointer. */ > int active_sp_regnum; > + int active_msp_regnum; > + int active_psp_regnum; > > /* The frame base for this frame is just prev_sp - frame size. > FRAMESIZE is the distance from the frame pointer to the > @@ -345,11 +347,23 @@ arm_cache_init (struct arm_prologue_cache *cache, struct frame_info *frame) > > if (tdep->have_sec_ext) > { > + CORE_ADDR msp_val = get_frame_register_unsigned (frame, tdep->m_profile_msp_regnum); > + CORE_ADDR psp_val = get_frame_register_unsigned (frame, tdep->m_profile_psp_regnum); > + > arm_cache_init_sp (tdep->m_profile_msp_s_regnum, &cache->msp_s, cache, frame); > arm_cache_init_sp (tdep->m_profile_psp_s_regnum, &cache->psp_s, cache, frame); > arm_cache_init_sp (tdep->m_profile_msp_ns_regnum, &cache->msp_ns, cache, frame); > arm_cache_init_sp (tdep->m_profile_psp_ns_regnum, &cache->psp_ns, cache, frame); > > + if (msp_val == cache->msp_s) > + cache->active_msp_regnum = tdep->m_profile_msp_s_regnum; > + else if (msp_val == cache->msp_ns) > + cache->active_msp_regnum = tdep->m_profile_msp_ns_regnum; > + if (psp_val == cache->psp_s) > + cache->active_psp_regnum = tdep->m_profile_psp_s_regnum; > + else if (psp_val == cache->psp_ns) > + cache->active_psp_regnum = tdep->m_profile_psp_ns_regnum; > + In the above section, you use 8 spaces for indentation instead on a tab char (in the 4 lines starting with "cache->"). Best, Lancelot. > /* Use MSP_S as default stack pointer. */ > if (cache->active_sp_regnum == ARM_SP_REGNUM) > cache->active_sp_regnum = tdep->m_profile_msp_s_regnum; > @@ -384,6 +398,10 @@ arm_cache_get_sp_register (struct arm_prologue_cache *cache, > return cache->psp_s; > if (regnum == tdep->m_profile_psp_ns_regnum) > return cache->psp_ns; > + if (regnum == tdep->m_profile_msp_regnum) > + return arm_cache_get_sp_register (cache, tdep, cache->active_msp_regnum); > + if (regnum == tdep->m_profile_psp_regnum) > + return arm_cache_get_sp_register (cache, tdep, cache->active_psp_regnum); > } > else if (tdep->is_m) > { > -- > 2.17.1 >