[PATCH 12/14] ODR warnings for "struct insn_decode_record_t"

[Tom Tromey <tromey@adacore.com>]

"struct insn_decode_record_t" is defined in multiple .c files, causing
ODR warnings.  This patch renames the types, and removes the use of
"typedef" here -- this is a C-ism that's no longer needed.

Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=22395
---
 gdb/aarch64-tdep.c | 28 +++++++-------
 gdb/arm-tdep.c     | 95 +++++++++++++++++++++++-----------------------
 2 files changed, 62 insertions(+), 61 deletions(-)

diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 9d06ebfe27c..141dc712898 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -3768,7 +3768,7 @@ enum aarch64_record_result
   AARCH64_RECORD_UNKNOWN
 };
 
-typedef struct insn_decode_record_t
+struct aarch64_insn_decode_record
 {
   struct gdbarch *gdbarch;
   struct regcache *regcache;
@@ -3778,12 +3778,12 @@ typedef struct insn_decode_record_t
   uint32_t reg_rec_count;              /* Count of register records.  */
   uint32_t *aarch64_regs;              /* Registers to be recorded.  */
   struct aarch64_mem_r *aarch64_mems;  /* Memory locations to be recorded.  */
-} insn_decode_record;
+};
 
 /* Record handler for data processing - register instructions.  */
 
 static unsigned int
-aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
+aarch64_record_data_proc_reg (aarch64_insn_decode_record *aarch64_insn_r)
 {
   uint8_t reg_rd, insn_bits24_27, insn_bits21_23;
   uint32_t record_buf[4];
@@ -3859,7 +3859,7 @@ aarch64_record_data_proc_reg (insn_decode_record *aarch64_insn_r)
 /* Record handler for data processing - immediate instructions.  */
 
 static unsigned int
-aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
+aarch64_record_data_proc_imm (aarch64_insn_decode_record *aarch64_insn_r)
 {
   uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags;
   uint32_t record_buf[4];
@@ -3904,7 +3904,7 @@ aarch64_record_data_proc_imm (insn_decode_record *aarch64_insn_r)
 /* Record handler for branch, exception generation and system instructions.  */
 
 static unsigned int
-aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
+aarch64_record_branch_except_sys (aarch64_insn_decode_record *aarch64_insn_r)
 {
 
   aarch64_gdbarch_tdep *tdep
@@ -3986,7 +3986,7 @@ aarch64_record_branch_except_sys (insn_decode_record *aarch64_insn_r)
 /* Record handler for advanced SIMD load and store instructions.  */
 
 static unsigned int
-aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
+aarch64_record_asimd_load_store (aarch64_insn_decode_record *aarch64_insn_r)
 {
   CORE_ADDR address;
   uint64_t addr_offset = 0;
@@ -4152,7 +4152,7 @@ aarch64_record_asimd_load_store (insn_decode_record *aarch64_insn_r)
 /* Record handler for load and store instructions.  */
 
 static unsigned int
-aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
+aarch64_record_load_store (aarch64_insn_decode_record *aarch64_insn_r)
 {
   uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11;
   uint8_t insn_bit23, insn_bit21;
@@ -4440,7 +4440,7 @@ aarch64_record_load_store (insn_decode_record *aarch64_insn_r)
 /* Record handler for data processing SIMD and floating point instructions.  */
 
 static unsigned int
-aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
+aarch64_record_data_proc_simd_fp (aarch64_insn_decode_record *aarch64_insn_r)
 {
   uint8_t insn_bit21, opcode, rmode, reg_rd;
   uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15;
@@ -4593,7 +4593,7 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r)
 /* Decodes insns type and invokes its record handler.  */
 
 static unsigned int
-aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
+aarch64_record_decode_insn_handler (aarch64_insn_decode_record *aarch64_insn_r)
 {
   uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28;
 
@@ -4628,7 +4628,7 @@ aarch64_record_decode_insn_handler (insn_decode_record *aarch64_insn_r)
 /* Cleans up local record registers and memory allocations.  */
 
 static void
-deallocate_reg_mem (insn_decode_record *record)
+deallocate_reg_mem (aarch64_insn_decode_record *record)
 {
   xfree (record->aarch64_regs);
   xfree (record->aarch64_mems);
@@ -4648,9 +4648,9 @@ aarch64_process_record_test (void)
   struct gdbarch *gdbarch = gdbarch_find_by_info (info);
   SELF_CHECK (gdbarch != NULL);
 
-  insn_decode_record aarch64_record;
+  aarch64_insn_decode_record aarch64_record;
 
-  memset (&aarch64_record, 0, sizeof (insn_decode_record));
+  memset (&aarch64_record, 0, sizeof (aarch64_insn_decode_record));
   aarch64_record.regcache = NULL;
   aarch64_record.this_addr = 0;
   aarch64_record.gdbarch = gdbarch;
@@ -4680,10 +4680,10 @@ aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
   uint8_t insn_size = 4;
   uint32_t ret = 0;
   gdb_byte buf[insn_size];
-  insn_decode_record aarch64_record;
+  aarch64_insn_decode_record aarch64_record;
 
   memset (&buf[0], 0, insn_size);
-  memset (&aarch64_record, 0, sizeof (insn_decode_record));
+  memset (&aarch64_record, 0, sizeof (aarch64_insn_decode_record));
   target_read_memory (insn_addr, &buf[0], insn_size);
   aarch64_record.aarch64_insn
     = (uint32_t) extract_unsigned_integer (&buf[0],
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 07836cfa1d5..ed556f9c62b 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -10671,7 +10671,7 @@ struct arm_mem_r
    contains list of to-be-modified registers and
    memory blocks (on return from decode_insn()).  */
 
-typedef struct insn_decode_record_t
+struct arm_insn_decode_record
 {
   struct gdbarch *gdbarch;
   struct regcache *regcache;
@@ -10684,7 +10684,7 @@ typedef struct insn_decode_record_t
   uint32_t reg_rec_count;       /* No of reg records.  */
   uint32_t *arm_regs;           /* Registers to be saved for this record.  */
   struct arm_mem_r *arm_mems;   /* Memory to be saved for this record.  */
-} insn_decode_record;
+};
 
 
 /* Checks ARM SBZ and SBO mandatory fields.  */
@@ -10732,7 +10732,7 @@ enum record_type_t
 
 
 static int
-arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf, 
+arm_record_strx (arm_insn_decode_record *arm_insn_r, uint32_t *record_buf, 
 		 uint32_t *record_buf_mem, arm_record_strx_t str_type)
 {
 
@@ -10900,7 +10900,7 @@ arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf,
 /* Handling ARM extension space insns.  */
 
 static int
-arm_record_extension_space (insn_decode_record *arm_insn_r)
+arm_record_extension_space (arm_insn_decode_record *arm_insn_r)
 {
   int ret = 0;  /* Return value: -1:record failure ;  0:success  */
   uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
@@ -11163,7 +11163,7 @@ arm_record_extension_space (insn_decode_record *arm_insn_r)
 /* Handling opcode 000 insns.  */
 
 static int
-arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r)
+arm_record_data_proc_misc_ld_str (arm_insn_decode_record *arm_insn_r)
 {
   struct regcache *reg_cache = arm_insn_r->regcache;
   uint32_t record_buf[8], record_buf_mem[8];
@@ -11456,7 +11456,7 @@ arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r)
 /* Handling opcode 001 insns.  */
 
 static int
-arm_record_data_proc_imm (insn_decode_record *arm_insn_r)
+arm_record_data_proc_imm (arm_insn_decode_record *arm_insn_r)
 {
   uint32_t record_buf[8], record_buf_mem[8];
 
@@ -11500,7 +11500,7 @@ arm_record_data_proc_imm (insn_decode_record *arm_insn_r)
 }
 
 static int
-arm_record_media (insn_decode_record *arm_insn_r)
+arm_record_media (arm_insn_decode_record *arm_insn_r)
 {
   uint32_t record_buf[8];
 
@@ -11584,7 +11584,7 @@ arm_record_media (insn_decode_record *arm_insn_r)
 /* Handle ARM mode instructions with opcode 010.  */
 
 static int
-arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r)
+arm_record_ld_st_imm_offset (arm_insn_decode_record *arm_insn_r)
 {
   struct regcache *reg_cache = arm_insn_r->regcache;
 
@@ -11675,7 +11675,7 @@ arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r)
 /* Handling opcode 011 insns.  */
 
 static int
-arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r)
+arm_record_ld_st_reg_offset (arm_insn_decode_record *arm_insn_r)
 {
   struct regcache *reg_cache = arm_insn_r->regcache;
 
@@ -11941,7 +11941,7 @@ arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r)
 /* Handle ARM mode instructions with opcode 100.  */
 
 static int
-arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
+arm_record_ld_st_multiple (arm_insn_decode_record *arm_insn_r)
 {
   struct regcache *reg_cache = arm_insn_r->regcache;
   uint32_t register_count = 0, register_bits;
@@ -12041,7 +12041,7 @@ arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
 /* Handling opcode 101 insns.  */
 
 static int
-arm_record_b_bl (insn_decode_record *arm_insn_r)
+arm_record_b_bl (arm_insn_decode_record *arm_insn_r)
 {
   uint32_t record_buf[8];
 
@@ -12061,7 +12061,7 @@ arm_record_b_bl (insn_decode_record *arm_insn_r)
 }
 
 static int
-arm_record_unsupported_insn (insn_decode_record *arm_insn_r)
+arm_record_unsupported_insn (arm_insn_decode_record *arm_insn_r)
 {
   gdb_printf (gdb_stderr,
 	      _("Process record does not support instruction "
@@ -12074,7 +12074,7 @@ arm_record_unsupported_insn (insn_decode_record *arm_insn_r)
 /* Record handler for vector data transfer instructions.  */
 
 static int
-arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
+arm_record_vdata_transfer_insn (arm_insn_decode_record *arm_insn_r)
 {
   uint32_t bits_a, bit_c, bit_l, reg_t, reg_v;
   uint32_t record_buf[4];
@@ -12160,7 +12160,7 @@ arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r)
 /* Record handler for extension register load/store instructions.  */
 
 static int
-arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
+arm_record_exreg_ld_st_insn (arm_insn_decode_record *arm_insn_r)
 {
   uint32_t opcode, single_reg;
   uint8_t op_vldm_vstm;
@@ -12355,7 +12355,7 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
 /* Record handler for arm/thumb mode VFP data processing instructions.  */
 
 static int
-arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r)
+arm_record_vfp_data_proc_insn (arm_insn_decode_record *arm_insn_r)
 {
   uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd;
   uint32_t record_buf[4];
@@ -12567,7 +12567,7 @@ arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r)
 /* Handling opcode 110 insns.  */
 
 static int
-arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r)
+arm_record_asimd_vfp_coproc (arm_insn_decode_record *arm_insn_r)
 {
   uint32_t op1, op1_ebit, coproc;
 
@@ -12621,7 +12621,7 @@ arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r)
 /* Handling opcode 111 insns.  */
 
 static int
-arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
+arm_record_coproc_data_proc (arm_insn_decode_record *arm_insn_r)
 {
   uint32_t op, op1_ebit, coproc, bits_24_25;
   arm_gdbarch_tdep *tdep
@@ -12752,7 +12752,7 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
 /* Handling opcode 000 insns.  */
 
 static int
-thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r)
+thumb_record_shift_add_sub (arm_insn_decode_record *thumb_insn_r)
 {
   uint32_t record_buf[8];
   uint32_t reg_src1 = 0;
@@ -12772,7 +12772,7 @@ thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r)
 /* Handling opcode 001 insns.  */
 
 static int
-thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r)
+thumb_record_add_sub_cmp_mov (arm_insn_decode_record *thumb_insn_r)
 {
   uint32_t record_buf[8];
   uint32_t reg_src1 = 0;
@@ -12791,7 +12791,7 @@ thumb_record_add_sub_cmp_mov (insn_decode_record *thumb_insn_r)
 /* Handling opcode 010 insns.  */
 
 static int
-thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
+thumb_record_ld_st_reg_offset (arm_insn_decode_record *thumb_insn_r)
 {
   struct regcache *reg_cache =  thumb_insn_r->regcache;
   uint32_t record_buf[8], record_buf_mem[8];
@@ -12883,7 +12883,7 @@ thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r)
 /* Handling opcode 001 insns.  */
 
 static int
-thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r)
+thumb_record_ld_st_imm_offset (arm_insn_decode_record *thumb_insn_r)
 {
   struct regcache *reg_cache = thumb_insn_r->regcache;
   uint32_t record_buf[8], record_buf_mem[8];
@@ -12923,7 +12923,7 @@ thumb_record_ld_st_imm_offset (insn_decode_record *thumb_insn_r)
 /* Handling opcode 100 insns.  */
 
 static int
-thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r)
+thumb_record_ld_st_stack (arm_insn_decode_record *thumb_insn_r)
 {
   struct regcache *reg_cache = thumb_insn_r->regcache;
   uint32_t record_buf[8], record_buf_mem[8];
@@ -12979,7 +12979,7 @@ thumb_record_ld_st_stack (insn_decode_record *thumb_insn_r)
 /* Handling opcode 101 insns.  */
 
 static int
-thumb_record_misc (insn_decode_record *thumb_insn_r)
+thumb_record_misc (arm_insn_decode_record *thumb_insn_r)
 {
   struct regcache *reg_cache = thumb_insn_r->regcache;
 
@@ -13110,7 +13110,7 @@ thumb_record_misc (insn_decode_record *thumb_insn_r)
 /* Handling opcode 110 insns.  */
 
 static int
-thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r)
+thumb_record_ldm_stm_swi (arm_insn_decode_record *thumb_insn_r)
 {
   arm_gdbarch_tdep *tdep
     = (arm_gdbarch_tdep *) gdbarch_tdep  (thumb_insn_r->gdbarch);
@@ -13195,7 +13195,7 @@ thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r)
 /* Handling opcode 111 insns.  */
 
 static int
-thumb_record_branch (insn_decode_record *thumb_insn_r)
+thumb_record_branch (arm_insn_decode_record *thumb_insn_r)
 {
   uint32_t record_buf[8];
   uint32_t bits_h = 0;
@@ -13227,7 +13227,7 @@ thumb_record_branch (insn_decode_record *thumb_insn_r)
 /* Handler for thumb2 load/store multiple instructions.  */
 
 static int
-thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r)
+thumb2_record_ld_st_multiple (arm_insn_decode_record *thumb2_insn_r)
 {
   struct regcache *reg_cache = thumb2_insn_r->regcache;
 
@@ -13322,7 +13322,7 @@ thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r)
    instructions.  */
 
 static int
-thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r)
+thumb2_record_ld_st_dual_ex_tbb (arm_insn_decode_record *thumb2_insn_r)
 {
   struct regcache *reg_cache = thumb2_insn_r->regcache;
 
@@ -13439,7 +13439,7 @@ thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r)
    instructions.  */
 
 static int
-thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r)
+thumb2_record_data_proc_sreg_mimm (arm_insn_decode_record *thumb2_insn_r)
 {
   uint32_t reg_rd, op;
   uint32_t record_buf[8];
@@ -13468,7 +13468,7 @@ thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r)
    registers.  */
 
 static int
-thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r)
+thumb2_record_ps_dest_generic (arm_insn_decode_record *thumb2_insn_r)
 {
   uint32_t reg_rd;
   uint32_t record_buf[8];
@@ -13487,7 +13487,7 @@ thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r)
 /* Handler for thumb2 branch and miscellaneous control instructions.  */
 
 static int
-thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r)
+thumb2_record_branch_misc_cntrl (arm_insn_decode_record *thumb2_insn_r)
 {
   uint32_t op, op1, op2;
   uint32_t record_buf[8];
@@ -13527,7 +13527,7 @@ thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r)
 /* Handler for thumb2 store single data item instructions.  */
 
 static int
-thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r)
+thumb2_record_str_single_data (arm_insn_decode_record *thumb2_insn_r)
 {
   struct regcache *reg_cache = thumb2_insn_r->regcache;
 
@@ -13617,7 +13617,7 @@ thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r)
 /* Handler for thumb2 load memory hints instructions.  */
 
 static int
-thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r)
+thumb2_record_ld_mem_hints (arm_insn_decode_record *thumb2_insn_r)
 {
   uint32_t record_buf[8];
   uint32_t reg_rt, reg_rn;
@@ -13643,7 +13643,7 @@ thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r)
 /* Handler for thumb2 load word instructions.  */
 
 static int
-thumb2_record_ld_word (insn_decode_record *thumb2_insn_r)
+thumb2_record_ld_word (arm_insn_decode_record *thumb2_insn_r)
 {
   uint32_t record_buf[8];
 
@@ -13660,7 +13660,7 @@ thumb2_record_ld_word (insn_decode_record *thumb2_insn_r)
    divide instructions.  */
 
 static int
-thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r)
+thumb2_record_lmul_lmla_div (arm_insn_decode_record *thumb2_insn_r)
 {
   uint32_t opcode1 = 0, opcode2 = 0;
   uint32_t record_buf[8];
@@ -13696,7 +13696,7 @@ thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r)
 /* Record handler for thumb32 coprocessor instructions.  */
 
 static int
-thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r)
+thumb2_record_coproc_insn (arm_insn_decode_record *thumb2_insn_r)
 {
   if (bit (thumb2_insn_r->arm_insn, 25))
     return arm_record_coproc_data_proc (thumb2_insn_r);
@@ -13707,7 +13707,7 @@ thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r)
 /* Record handler for advance SIMD structure load/store instructions.  */
 
 static int
-thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r)
+thumb2_record_asimd_struct_ld_st (arm_insn_decode_record *thumb2_insn_r)
 {
   struct regcache *reg_cache = thumb2_insn_r->regcache;
   uint32_t l_bit, a_bit, b_bits;
@@ -13895,7 +13895,7 @@ thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r)
 /* Decodes thumb2 instruction type and invokes its record handler.  */
 
 static unsigned int
-thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r)
+thumb2_record_decode_insn_handler (arm_insn_decode_record *thumb2_insn_r)
 {
   uint32_t op, op1, op2;
 
@@ -14029,7 +14029,7 @@ and positive val on failure.  */
 
 static int
 extract_arm_insn (abstract_memory_reader& reader,
-		  insn_decode_record *insn_record, uint32_t insn_size)
+		  arm_insn_decode_record *insn_record, uint32_t insn_size)
 {
   gdb_byte buf[insn_size];
 
@@ -14043,13 +14043,14 @@ extract_arm_insn (abstract_memory_reader& reader,
   return 0;
 }
 
-typedef int (*sti_arm_hdl_fp_t) (insn_decode_record*);
+typedef int (*sti_arm_hdl_fp_t) (arm_insn_decode_record*);
 
 /* Decode arm/thumb insn depending on condition cods and opcodes; and
    dispatch it.  */
 
 static int
-decode_insn (abstract_memory_reader &reader, insn_decode_record *arm_record,
+decode_insn (abstract_memory_reader &reader,
+	     arm_insn_decode_record *arm_record,
 	     record_type_t record_type, uint32_t insn_size)
 {
 
@@ -14200,9 +14201,9 @@ arm_record_test (void)
 
   /* 16-bit Thumb instructions.  */
   {
-    insn_decode_record arm_record;
+    arm_insn_decode_record arm_record;
 
-    memset (&arm_record, 0, sizeof (insn_decode_record));
+    memset (&arm_record, 0, sizeof (arm_insn_decode_record));
     arm_record.gdbarch = gdbarch;
 
     static const uint16_t insns[] = {
@@ -14234,9 +14235,9 @@ arm_record_test (void)
 
   /* 32-bit Thumb-2 instructions.  */
   {
-    insn_decode_record arm_record;
+    arm_insn_decode_record arm_record;
 
-    memset (&arm_record, 0, sizeof (insn_decode_record));
+    memset (&arm_record, 0, sizeof (arm_insn_decode_record));
     arm_record.gdbarch = gdbarch;
 
     static const uint16_t insns[] = {
@@ -14315,7 +14316,7 @@ arm_analyze_prologue_test ()
 /* Cleans up local record registers and memory allocations.  */
 
 static void 
-deallocate_reg_mem (insn_decode_record *record)
+deallocate_reg_mem (arm_insn_decode_record *record)
 {
   xfree (record->arm_regs);
   xfree (record->arm_mems);    
@@ -14337,9 +14338,9 @@ arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
 
   ULONGEST u_regval = 0;
 
-  insn_decode_record arm_record;
+  arm_insn_decode_record arm_record;
 
-  memset (&arm_record, 0, sizeof (insn_decode_record));
+  memset (&arm_record, 0, sizeof (arm_insn_decode_record));
   arm_record.regcache = regcache;
   arm_record.this_addr = insn_addr;
   arm_record.gdbarch = gdbarch;
-- 
2.34.1