From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by sourceware.org (Postfix) with ESMTPS id 2573C3857BB1 for ; Tue, 31 May 2022 13:23:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2573C3857BB1 Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 24VAXqUe007483; Tue, 31 May 2022 15:23:44 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3gbc50huus-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 31 May 2022 15:23:44 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 476A610002A; Tue, 31 May 2022 15:23:43 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 19E9B22A6D5; Tue, 31 May 2022 15:23:43 +0200 (CEST) Received: from gnbcxd0114.gnb.st.com (10.75.127.47) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2308.20; Tue, 31 May 2022 15:23:42 +0200 Date: Tue, 31 May 2022 15:23:40 +0200 From: Yvan Roux To: Luis Machado , CC: Torbjorn SVENSSON Subject: Re: [PATCH] gdb/arm: Cleanup: use hex for offsets Message-ID: <20220531132340.GA13232@gnbcxd0114.gnb.st.com> References: <20220525151240.GA11828@gnbcxd0114.gnb.st.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-05-31_04,2022-05-30_03,2022-02-23_01 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 May 2022 13:23:49 -0000 On Thu, May 26, 2022 at 08:29:38AM +0100, Luis Machado wrote: > On 5/25/22 16:12, Yvan Roux wrote: > > Hi, > > > > Changed offset from decimal to hex to match architecture reference > > manual terminology and keep coherency with the rest of the code. > > > > Signed-off-by: Torbj�rn SVENSSON > > Signed-off-by: Yvan Roux > > --- > > gdb/arm-tdep.c | 16 ++++++++-------- > > 1 file changed, 8 insertions(+), 8 deletions(-) > > > > diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c > > index 49664093f00..21cd80c5fcc 100644 > > --- a/gdb/arm-tdep.c > > +++ b/gdb/arm-tdep.c > > @@ -3438,13 +3438,13 @@ arm_m_exception_cache (struct frame_info *this_frame) > > "B1.5.6 Exception entry behavior" in > > "ARMv7-M Architecture Reference Manual". */ > > cache->saved_regs[0].set_addr (unwound_sp + sp_r0_offset); > > - cache->saved_regs[1].set_addr (unwound_sp + sp_r0_offset + 4); > > - cache->saved_regs[2].set_addr (unwound_sp + sp_r0_offset + 8); > > - cache->saved_regs[3].set_addr (unwound_sp + sp_r0_offset + 12); > > - cache->saved_regs[ARM_IP_REGNUM].set_addr (unwound_sp + sp_r0_offset + 16); > > - cache->saved_regs[ARM_LR_REGNUM].set_addr (unwound_sp + sp_r0_offset + 20); > > - cache->saved_regs[ARM_PC_REGNUM].set_addr (unwound_sp + sp_r0_offset + 24); > > - cache->saved_regs[ARM_PS_REGNUM].set_addr (unwound_sp + sp_r0_offset + 28); > > + cache->saved_regs[1].set_addr (unwound_sp + sp_r0_offset + 0x04); > > + cache->saved_regs[2].set_addr (unwound_sp + sp_r0_offset + 0x08); > > + cache->saved_regs[3].set_addr (unwound_sp + sp_r0_offset + 0x0C); > > + cache->saved_regs[ARM_IP_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x10); > > + cache->saved_regs[ARM_LR_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x14); > > + cache->saved_regs[ARM_PC_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x18); > > + cache->saved_regs[ARM_PS_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x1C); > > /* Check EXC_RETURN bit FTYPE if extended stack frame (FPU regs stored) > > type used. */ > > @@ -3499,7 +3499,7 @@ arm_m_exception_cache (struct frame_info *this_frame) > > /* If bit 9 of the saved xPSR is set, then there is a four-byte > > aligner between the top of the 32-byte stack frame and the > > previous context's stack pointer. */ > > - if (safe_read_memory_integer (unwound_sp + sp_r0_offset + 28, 4, byte_order, &xpsr) > > + if (safe_read_memory_integer (unwound_sp + sp_r0_offset + 0x1C, 4, byte_order, &xpsr) > > && (xpsr & (1 << 9)) != 0) > > arm_cache_set_active_sp_value (cache, tdep, > > arm_cache_get_prev_sp_value (cache, tdep) + 4); > > Thanks. This is OK with the long lines fixed. The last one is going over the limit of 80 cols. Thanks for the review Luis, here is the updated version of the patch. Would you mind applying it, I don't have the commit rigths. Cheers Yvan Changed offset from decimal to hex to match architecture reference manual terminology and keep coherency with the rest of the code. Signed-off-by: Torbjörn SVENSSON Signed-off-by: Yvan Roux --- gdb/arm-tdep.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 49664093f00..5ea66898747 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -3438,13 +3438,13 @@ arm_m_exception_cache (struct frame_info *this_frame) "B1.5.6 Exception entry behavior" in "ARMv7-M Architecture Reference Manual". */ cache->saved_regs[0].set_addr (unwound_sp + sp_r0_offset); - cache->saved_regs[1].set_addr (unwound_sp + sp_r0_offset + 4); - cache->saved_regs[2].set_addr (unwound_sp + sp_r0_offset + 8); - cache->saved_regs[3].set_addr (unwound_sp + sp_r0_offset + 12); - cache->saved_regs[ARM_IP_REGNUM].set_addr (unwound_sp + sp_r0_offset + 16); - cache->saved_regs[ARM_LR_REGNUM].set_addr (unwound_sp + sp_r0_offset + 20); - cache->saved_regs[ARM_PC_REGNUM].set_addr (unwound_sp + sp_r0_offset + 24); - cache->saved_regs[ARM_PS_REGNUM].set_addr (unwound_sp + sp_r0_offset + 28); + cache->saved_regs[1].set_addr (unwound_sp + sp_r0_offset + 0x04); + cache->saved_regs[2].set_addr (unwound_sp + sp_r0_offset + 0x08); + cache->saved_regs[3].set_addr (unwound_sp + sp_r0_offset + 0x0C); + cache->saved_regs[ARM_IP_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x10); + cache->saved_regs[ARM_LR_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x14); + cache->saved_regs[ARM_PC_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x18); + cache->saved_regs[ARM_PS_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x1C); /* Check EXC_RETURN bit FTYPE if extended stack frame (FPU regs stored) type used. */ @@ -3499,7 +3499,8 @@ arm_m_exception_cache (struct frame_info *this_frame) /* If bit 9 of the saved xPSR is set, then there is a four-byte aligner between the top of the 32-byte stack frame and the previous context's stack pointer. */ - if (safe_read_memory_integer (unwound_sp + sp_r0_offset + 28, 4, byte_order, &xpsr) + if (safe_read_memory_integer (unwound_sp + sp_r0_offset + 0x1C, 4, + byte_order, &xpsr) && (xpsr & (1 << 9)) != 0) arm_cache_set_active_sp_value (cache, tdep, arm_cache_get_prev_sp_value (cache, tdep) + 4); -- 2.17.1