From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by sourceware.org (Postfix) with ESMTPS id EF454396DC2D for ; Thu, 2 Jun 2022 14:29:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org EF454396DC2D Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2528k97J032342; Thu, 2 Jun 2022 16:29:51 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3get03huq6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 02 Jun 2022 16:29:50 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6CCDB100034; Thu, 2 Jun 2022 16:29:50 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 6095822D174; Thu, 2 Jun 2022 16:29:50 +0200 (CEST) Received: from gnbcxd0114.gnb.st.com (10.75.127.51) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2308.20; Thu, 2 Jun 2022 16:29:49 +0200 Date: Thu, 2 Jun 2022 16:29:48 +0200 From: Yvan Roux To: CC: Christophe Lyon , Torbjorn SVENSSON , Luis Machado Subject: Re: [PATCH] gdb/arm: Document and fix exception stack offsets Message-ID: <20220602142948.GC23363@gnbcxd0114.gnb.st.com> References: <20220602092316.GB20273@gnbcxd0114.gnb.st.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) X-Originating-IP: [10.75.127.51] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-02_03,2022-06-02_01,2022-02-23_01 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Jun 2022 14:29:55 -0000 On Thu, Jun 02, 2022 at 12:09:47PM +0200, Christophe Lyon wrote: > > > On 6/2/22 11:23, Yvan Roux via Gdb-patches wrote: > > Hi, > > > > Add a description of exception entry context stacking and fix next > > frame offset (at 0xA8 relative to R0 location) as well as FPU > > registers ones (starting at 0x68 relative to R0). > > Thanks, adding the picture will really help maintenance! > So IIUC, the existing code is broken when there is no Secure->Non-Secure > transition additional context saved? Thanks, yes that's it, the current offsets assume that the additional contexts are present. > > > > > Signed-off-by: Torbj�rn SVENSSON > > Signed-off-by: Yvan Roux > > --- > > gdb/arm-tdep.c | 62 ++++++++++++++++++++++++++++++++++++++++++++++---- > > 1 file changed, 58 insertions(+), 4 deletions(-) > > > > diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c > > index 50ec41a66b1..759dfd76ef6 100644 > > --- a/gdb/arm-tdep.c > > +++ b/gdb/arm-tdep.c > > @@ -3417,6 +3417,57 @@ arm_m_exception_cache (struct frame_info *this_frame) > > /* Fetch the SP to use for this frame. */ > > unwound_sp = arm_cache_get_prev_sp_value (cache, tdep); > > + /* Exception entry context stacking as described into ARMv8-M (section B3.19) > > + and ARMv7-M (sections B1.5.6 and B1.5.7) Architecture Reference Manuals. > > + > > + SP Offsets > > + Without With > > + Callee Regs Callee Regs > > Could make the description here (Without Callee Regs) a more obvious match > of the one below (Additional State Ctx When transitioning from Secure to > Non-secure)? OK > > + > > + +-------------------+ > > + 0xA8 | | 0xD0 > > + +===================+ --+ <-- Original SP > > + 0xA4 | S31 | 0xCC | > > + +-------------------+ | > > + ... | Additional FP Ctx > Here and elsewhere, I suggest Ctx -> Context OK > > + +-------------------+ | > > + 0x68 | S16 | 0x90 | > > + +===================+ --+ > > + 0x64 | Reserved | 0x8C | > > + +-------------------+ | > > + 0x60 | FPSCR | 0x88 | > > + +-------------------+ | > > + 0x5C | S15 | 0x84 | FP Ctx > > + +-------------------+ | > > + ... | > > + +-------------------+ | > > + 0x20 | S0 | 0x48 | > > + +===================+ --+ > > + 0x1C | xPSR | 0x44 | > > + +-------------------+ | > > + 0x18 | Return address | 0x40 | > > + +-------------------+ | > > + 0x14 | LR(R14) | 0x3C | > > + +-------------------+ | > > + 0x10 | R12 | 0x38 | State Ctx > > + +-------------------+ | > > + 0x0C | R3 | 0x34 | > > + +-------------------+ | > > + ... | > > + +-------------------+ | > > + 0x00 | R0 | 0x28 | > > + +===================+ --+ > > + | R11 | 0x24 | > > + +-------------------+ | > > + ... | > > + +-------------------+ | Additional State Ctx > > + | R4 | 0x08 | When transitioning from > > + +-------------------+ | Secure to Non-secure > > + | Reserved | 0x04 | > > + +-------------------+ | > > + | Magic signature | 0x00 | > > + +===================+ --+ <-- New SP */ > > + > > /* With the Security extension, the hardware saves R4..R11 too. */ > > if (exc_return && tdep->have_sec_ext && secure_stack_used > > && (!default_callee_register_stacking || exception_domain_is_secure)) > > @@ -3475,25 +3526,28 @@ arm_m_exception_cache (struct frame_info *this_frame) > > if (tdep->have_sec_ext && !default_callee_register_stacking) > > { > > /* Handle floating-point callee saved registers. */ > > - fpu_regs_stack_offset = 0x90; > > + fpu_regs_stack_offset = unwound_sp + sp_r0_offset + 0x68; > > for (i = 8; i < 16; i++) > > { > > cache->saved_regs[ARM_D0_REGNUM + i].set_addr (fpu_regs_stack_offset); > > fpu_regs_stack_offset += 8; > > } > > - arm_cache_set_active_sp_value (cache, tdep, unwound_sp + sp_r0_offset + 0xD0); > > + arm_cache_set_active_sp_value (cache, tdep, > > + unwound_sp + sp_r0_offset + 0xA8); > > } > > else > > { > > /* Offset 0x64 is reserved. */ > > - arm_cache_set_active_sp_value (cache, tdep, unwound_sp + sp_r0_offset + 0x68); > > + arm_cache_set_active_sp_value (cache, tdep, > > + unwound_sp + sp_r0_offset + 0x68); > > } > > } > > else > > { > > /* Standard stack frame type used. */ > > - arm_cache_set_active_sp_value (cache, tdep, unwound_sp + sp_r0_offset + 0x20); > > + arm_cache_set_active_sp_value (cache, tdep, > > + unwound_sp + sp_r0_offset + 0x20); > > } > > /* If bit 9 of the saved xPSR is set, then there is a four-byte > > > Thanks, > > Christophe Here is the updated version: --- gdb/arm-tdep.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 61 insertions(+), 4 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 50ec41a66b1..6998fbd24e9 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -3417,6 +3417,60 @@ arm_m_exception_cache (struct frame_info *this_frame) /* Fetch the SP to use for this frame. */ unwound_sp = arm_cache_get_prev_sp_value (cache, tdep); + /* Exception entry context stacking are described in ARMv8-M (section B3.19) + and ARMv7-M (sections B1.5.6 and B1.5.7) Architecture Reference Manuals. + + The following figure shows the structure of the stack frame when Security + and Floating-point extensions are present. + + SP Offsets + Without With + Callee Regs Callee Regs + (Secure -> Non-Secure) + +-------------------+ + 0xA8 | | 0xD0 + +===================+ --+ <-- Original SP + 0xA4 | S31 | 0xCC | + +-------------------+ | + ... | Additional FP Context + +-------------------+ | + 0x68 | S16 | 0x90 | + +===================+ --+ + 0x64 | Reserved | 0x8C | + +-------------------+ | + 0x60 | FPSCR | 0x88 | + +-------------------+ | + 0x5C | S15 | 0x84 | FP Context + +-------------------+ | + ... | + +-------------------+ | + 0x20 | S0 | 0x48 | + +===================+ --+ + 0x1C | xPSR | 0x44 | + +-------------------+ | + 0x18 | Return address | 0x40 | + +-------------------+ | + 0x14 | LR(R14) | 0x3C | + +-------------------+ | + 0x10 | R12 | 0x38 | State Context + +-------------------+ | + 0x0C | R3 | 0x34 | + +-------------------+ | + ... | + +-------------------+ | + 0x00 | R0 | 0x28 | + +===================+ --+ + | R11 | 0x24 | + +-------------------+ | + ... | + +-------------------+ | Additional State Context + | R4 | 0x08 | When transitioning from + +-------------------+ | Secure to Non-secure + | Reserved | 0x04 | + +-------------------+ | + | Magic signature | 0x00 | + +===================+ --+ <-- New SP */ + /* With the Security extension, the hardware saves R4..R11 too. */ if (exc_return && tdep->have_sec_ext && secure_stack_used && (!default_callee_register_stacking || exception_domain_is_secure)) @@ -3475,25 +3529,28 @@ arm_m_exception_cache (struct frame_info *this_frame) if (tdep->have_sec_ext && !default_callee_register_stacking) { /* Handle floating-point callee saved registers. */ - fpu_regs_stack_offset = 0x90; + fpu_regs_stack_offset = unwound_sp + sp_r0_offset + 0x68; for (i = 8; i < 16; i++) { cache->saved_regs[ARM_D0_REGNUM + i].set_addr (fpu_regs_stack_offset); fpu_regs_stack_offset += 8; } - arm_cache_set_active_sp_value (cache, tdep, unwound_sp + sp_r0_offset + 0xD0); + arm_cache_set_active_sp_value (cache, tdep, + unwound_sp + sp_r0_offset + 0xA8); } else { /* Offset 0x64 is reserved. */ - arm_cache_set_active_sp_value (cache, tdep, unwound_sp + sp_r0_offset + 0x68); + arm_cache_set_active_sp_value (cache, tdep, + unwound_sp + sp_r0_offset + 0x68); } } else { /* Standard stack frame type used. */ - arm_cache_set_active_sp_value (cache, tdep, unwound_sp + sp_r0_offset + 0x20); + arm_cache_set_active_sp_value (cache, tdep, + unwound_sp + sp_r0_offset + 0x20); } /* If bit 9 of the saved xPSR is set, then there is a four-byte -- 2.17.1