From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by sourceware.org (Postfix) with ESMTPS id 1E5283852754 for ; Tue, 14 Jun 2022 14:47:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1E5283852754 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 25EBjSrX008404; Tue, 14 Jun 2022 16:47:53 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3gp2uha4q7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 14 Jun 2022 16:47:53 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E34D910002A; Tue, 14 Jun 2022 16:47:52 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C0A3E229A6C; Tue, 14 Jun 2022 16:47:52 +0200 (CEST) Received: from gnbcxd0114.gnb.st.com (10.129.178.234) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Tue, 14 Jun 2022 16:47:52 +0200 Date: Tue, 14 Jun 2022 16:47:51 +0200 From: Yvan Roux To: CC: Luis Machado , Torbjorn SVENSSON Subject: [PATCH] gdb/arm: Only stack S16..S31 when FPU registers are secure Message-ID: <20220614144751.GA12000@gnbcxd0114.gnb.st.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Disposition: inline Content-Transfer-Encoding: 8bit User-Agent: Mutt/1.9.4 (2018-02-28) X-Originating-IP: [10.129.178.234] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-14_05,2022-06-13_01,2022-02-23_01 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 14 Jun 2022 14:47:58 -0000 Hi, The FPCCR.TS bit is used to identify if FPU registers are considered non-secure or secure. If they are secure, then callee saved registers (S16 to S31) are stacked on exception entry or otherwise skipped. Signed-off-by: Torbjörn SVENSSON Signed-off-by: Yvan Roux --- gdb/arch/arm.h | 6 ++++++ gdb/arm-tdep.c | 9 ++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/gdb/arch/arm.h b/gdb/arch/arm.h index 4ad329f6f1f..de1b472fe71 100644 --- a/gdb/arch/arm.h +++ b/gdb/arch/arm.h @@ -136,6 +136,12 @@ enum arm_m_profile_type { #define XPSR_T 0x01000000 +/* System control registers addresses. */ + +/* M-profile Floating-Point Context Control Register address, defined in ARMv7-M + (Section B3.2.2) and ARMv8-M (Section D1.2.99) reference manuals. */ +#define FPCCR 0xE000EF34 + /* Size of registers. */ #define ARM_INT_REGISTER_SIZE 4 diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 456649afdaa..abc812817aa 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -3519,6 +3519,13 @@ arm_m_exception_cache (struct frame_info *this_frame) { int i; int fpu_regs_stack_offset; + ULONGEST fpccr; + bool fpccr_ts; + + /* Read FPCCR register */ + gdb_assert (safe_read_memory_unsigned_integer (FPCCR, 4, byte_order, + &fpccr)); + fpccr_ts = fpccr & (1 << 26); /* This code does not take into account the lazy stacking, see "Lazy context save of FP state", in B1.5.7, also ARM AN298, supported @@ -3538,7 +3545,7 @@ arm_m_exception_cache (struct frame_info *this_frame) cache->saved_regs[ARM_FPSCR_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x60); fpu_regs_stack_offset += 4; - if (tdep->have_sec_ext && !default_callee_register_stacking) + if (tdep->have_sec_ext && !default_callee_register_stacking && fpccr_ts) { /* Handle floating-point callee saved registers. */ fpu_regs_stack_offset = unwound_sp + sp_r0_offset + 0x68; -- 2.17.1