From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by sourceware.org (Postfix) with ESMTPS id 4E71F3852765 for ; Tue, 14 Jun 2022 15:01:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4E71F3852765 Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 25EE3AVO029267; Tue, 14 Jun 2022 17:01:39 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3gmgfmn05r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 14 Jun 2022 17:01:39 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B572D10002A; Tue, 14 Jun 2022 17:01:38 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id AB319229A91; Tue, 14 Jun 2022 17:01:38 +0200 (CEST) Received: from gnbcxd0114.gnb.st.com (10.129.178.234) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Tue, 14 Jun 2022 17:01:38 +0200 Date: Tue, 14 Jun 2022 17:01:37 +0200 From: Yvan Roux To: CC: Torbjorn SVENSSON , Luis Machado Subject: [PATCH 3/3] gdb/arm: Make sp alias for one of the other stack pointers Message-ID: <20220614150137.GE12000@gnbcxd0114.gnb.st.com> References: <20220614145606.GB12000@gnbcxd0114.gnb.st.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220614145606.GB12000@gnbcxd0114.gnb.st.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-Originating-IP: [10.129.178.234] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-14_05,2022-06-13_01,2022-02-23_01 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 14 Jun 2022 15:01:43 -0000 For Cortex-M targets, the sp register is never detached from msp or psp, it always has the same value as one of them. Let GDB treat ARM_SP_REGNUM as an alias similar to what is done in hardware. Signed-off-by: Torbjörn SVENSSON Signed-off-by: Yvan Roux --- gdb/arm-tdep.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index e497dd1b3b8..694fe8a8859 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -385,9 +385,6 @@ static CORE_ADDR arm_cache_get_sp_register (struct arm_prologue_cache *cache, arm_gdbarch_tdep *tdep, int regnum) { - if (regnum == ARM_SP_REGNUM) - return cache->sp; - if (tdep->have_sec_ext) { if (regnum == tdep->m_profile_msp_s_regnum) @@ -402,6 +399,8 @@ arm_cache_get_sp_register (struct arm_prologue_cache *cache, return arm_cache_get_sp_register (cache, tdep, cache->active_msp_regnum); if (regnum == tdep->m_profile_psp_regnum) return arm_cache_get_sp_register (cache, tdep, cache->active_psp_regnum); + if (regnum == ARM_SP_REGNUM) + return arm_cache_get_sp_register (cache, tdep, cache->active_sp_regnum); } else if (tdep->is_m) { @@ -409,7 +408,11 @@ arm_cache_get_sp_register (struct arm_prologue_cache *cache, return cache->msp_s; if (regnum == tdep->m_profile_psp_regnum) return cache->psp_s; + if (regnum == ARM_SP_REGNUM) + return arm_cache_get_sp_register (cache, tdep, cache->active_sp_regnum); } + else if (regnum == ARM_SP_REGNUM) + return cache->sp; gdb_assert_not_reached ("Invalid SP selection"); } @@ -430,12 +433,6 @@ static void arm_cache_set_active_sp_value (struct arm_prologue_cache *cache, arm_gdbarch_tdep *tdep, CORE_ADDR val) { - if (cache->active_sp_regnum == ARM_SP_REGNUM) - { - cache->sp = val; - return; - } - if (tdep->have_sec_ext) { if (cache->active_sp_regnum == tdep->m_profile_msp_s_regnum) @@ -458,6 +455,11 @@ arm_cache_set_active_sp_value (struct arm_prologue_cache *cache, return; } + else if (cache->active_sp_regnum == ARM_SP_REGNUM) + { + cache->sp = val; + return; + } gdb_assert_not_reached ("Invalid SP selection"); } -- 2.17.1