From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by sourceware.org (Postfix) with ESMTPS id 6D06C3858D32 for ; Thu, 7 Jul 2022 09:21:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6D06C3858D32 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2677prRt025721; Thu, 7 Jul 2022 11:21:18 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3h58bp7p6y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Jul 2022 11:21:18 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3881810002A; Thu, 7 Jul 2022 11:21:18 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 34385212FDD; Thu, 7 Jul 2022 11:21:18 +0200 (CEST) Received: from gnbcxd0114.gnb.st.com (10.75.127.46) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2308.20; Thu, 7 Jul 2022 11:21:17 +0200 Date: Thu, 7 Jul 2022 11:21:16 +0200 From: Yvan Roux To: , Luis Machado CC: Torbjorn SVENSSON Subject: [PATCH V2 2/2] gdb/arm: Sync sp with other *sp registers Message-ID: <20220707092116.GD5239@gnbcxd0114.gnb.st.com> References: <20220707091722.GB5239@gnbcxd0114.gnb.st.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220707091722.GB5239@gnbcxd0114.gnb.st.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-07-07_06,2022-06-28_01,2022-06-22_01 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jul 2022 09:21:23 -0000 For Arm Cortex-M33 with security extensions, there are 4 different stack pointers (msp_s, msp_ns, psp_s, psp_ns), without security extensions and for other Cortex-M targets, there are 2 different stack pointers (msp and psp). With this path, sp will always be in sync with one of the real stack pointers on Arm targets that contains more than one stack pointer. Signed-off-by: Torbjörn SVENSSON Signed-off-by: Yvan Roux --- gdb/arm-tdep.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 89c2779bbb5..c28543229de 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -3812,6 +3812,85 @@ arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, return frame_unwind_got_constant (this_frame, regnum, cpsr); default: + /* Handle the alternative SP on Cortex-M. */ + if (arm_is_alternative_sp_register (tdep, regnum)) + { + bool override_with_sp_value = false; + CORE_ADDR val; + + if (tdep->have_sec_ext) + { + CORE_ADDR sp + = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); + CORE_ADDR msp_s + = get_frame_register_unsigned (this_frame, + tdep->m_profile_msp_s_regnum); + CORE_ADDR msp_ns + = get_frame_register_unsigned (this_frame, + tdep->m_profile_msp_ns_regnum); + CORE_ADDR psp_s + = get_frame_register_unsigned (this_frame, + tdep->m_profile_psp_s_regnum); + CORE_ADDR psp_ns + = get_frame_register_unsigned (this_frame, + tdep->m_profile_psp_ns_regnum); + + if (regnum == tdep->m_profile_msp_regnum + && (msp_s == sp || msp_ns == sp)) + /* Use value of SP for MSP register. */ + override_with_sp_value = true; + else if (regnum == tdep->m_profile_msp_s_regnum && msp_s == sp) + /* Use value of SP for MSP_S register. */ + override_with_sp_value = true; + else if (regnum == tdep->m_profile_msp_ns_regnum && msp_ns == sp) + /* Use value of SP for MSP_NS register. */ + override_with_sp_value = true; + else if (regnum == tdep->m_profile_psp_regnum + && (psp_s == sp || psp_ns == sp)) + /* Use value of SP for PSP register. */ + override_with_sp_value = true; + else if (regnum == tdep->m_profile_psp_s_regnum && psp_s == sp) + /* Use value of SP for PSP_S register. */ + override_with_sp_value = true; + else if (regnum == tdep->m_profile_psp_ns_regnum && psp_ns == sp) + /* Use value of SP for PSP_NS register. */ + override_with_sp_value = true; + } + else if (tdep->is_m) + { + CORE_ADDR sp + = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); + CORE_ADDR msp + = get_frame_register_unsigned (this_frame, + tdep->m_profile_msp_regnum); + CORE_ADDR psp + = get_frame_register_unsigned (this_frame, + tdep->m_profile_psp_regnum); + + if (regnum == tdep->m_profile_msp_regnum && sp == msp) + /* Use value of SP for MSP register. */ + override_with_sp_value = true; + else if (regnum == tdep->m_profile_psp_regnum && sp == psp) + /* Use value of SP for PSP register. */ + override_with_sp_value = true; + } + + if (override_with_sp_value) + { + /* Use value of SP from previous frame. */ + struct frame_info *prev_frame = get_prev_frame(this_frame); + if (prev_frame) + val = get_frame_register_unsigned (prev_frame, ARM_SP_REGNUM); + else + val = get_frame_base(this_frame); + } + else + /* Use value for the register from previous frame. */ + val = get_frame_register_unsigned (this_frame, regnum); + + return frame_unwind_got_constant(this_frame, regnum, val); + } + internal_error (__FILE__, __LINE__, _("Unexpected register %d"), regnum); } @@ -4931,6 +5010,8 @@ arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, struct dwarf2_frame_state_reg *reg, struct frame_info *this_frame) { + arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); + if (is_pacbti_pseudo (gdbarch, regnum)) { /* Initialize RA_AUTH_CODE to zero. */ @@ -4950,6 +5031,14 @@ arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, case ARM_SP_REGNUM: reg->how = DWARF2_FRAME_REG_CFA; break; + default: + /* Handle the alternative SP on Cortex-M. */ + if (arm_is_alternative_sp_register (tdep, regnum)) + { + reg->how = DWARF2_FRAME_REG_FN; + reg->loc.fn = arm_dwarf2_prev_register; + } + break; } } -- 2.17.1