* [PATCH] RISC-V: fix FRM register display mask value
@ 2022-07-11 17:57 Hugues de Lassus
2022-08-03 18:45 ` [PING] " Hugues de Lassus
0 siblings, 1 reply; 6+ messages in thread
From: Hugues de Lassus @ 2022-07-11 17:57 UTC (permalink / raw)
To: gdb-patches; +Cc: Hugues de Lassus
The FRM register is 3-bit long, but the top-most bit was masked off for
display, resulting in incorrectly displayed values and format strings
when FRM >= 4.
Tested on riscv64-unknown-linux-gnu target, with FPU support.
---
gdb/riscv-tdep.c | 2 +-
gdb/testsuite/gdb.base/float.exp | 4 +++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 69f2123dcdb..a3afab3b998 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -1185,7 +1185,7 @@ riscv_print_one_register_info (struct gdbarch *gdbarch,
"dynamic rounding mode",
};
int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
- ? (d >> 5) : d) & 0x3;
+ ? (d >> 5) : d) & 0x7;
gdb_printf (file, "%sFRM:%i [%s]",
(regnum == RISCV_CSR_FCSR_REGNUM
diff --git a/gdb/testsuite/gdb.base/float.exp b/gdb/testsuite/gdb.base/float.exp
index 62e8346928b..10c0692a976 100644
--- a/gdb/testsuite/gdb.base/float.exp
+++ b/gdb/testsuite/gdb.base/float.exp
@@ -112,14 +112,16 @@ if { [is_aarch64_target] } then {
gdb_test "info float" "f0.*f1.*f31.*d0.*d30.*" "info float"
} elseif [istarget "riscv*-*-*"] then {
# RISC-V may or may not have an FPU
+ send_gdb "set \$frm = 7\n"
gdb_test_multiple "info float" "info float" {
- -re "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*$gdb_prompt $" {
+ -re "ft0.*ft1.*ft11.*fflags.*frm.*0x7.*FRM:7.*fcsr.*$gdb_prompt $" {
pass "info float (with FPU)"
}
-re "No floating.point info available for this processor.*$gdb_prompt $" {
pass "info float (without FPU)"
}
}
+ send_gdb "set \$frm = 0\n"
} else {
gdb_test "info float" "No floating.point info available for this processor." "info float (unknown target)"
}
--
2.35.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PING] [PATCH] RISC-V: fix FRM register display mask value
2022-07-11 17:57 [PATCH] RISC-V: fix FRM register display mask value Hugues de Lassus
@ 2022-08-03 18:45 ` Hugues de Lassus
2022-09-21 19:34 ` [PING^2] " Hugues de Lassus
0 siblings, 1 reply; 6+ messages in thread
From: Hugues de Lassus @ 2022-08-03 18:45 UTC (permalink / raw)
To: gdb-patches; +Cc: Hugues de Lassus
Ping.
On Mon, Jul 11, 2022 at 10:58 AM Hugues de Lassus <
hugues.delassus@sifive.com> wrote:
> The FRM register is 3-bit long, but the top-most bit was masked off for
> display, resulting in incorrectly displayed values and format strings
> when FRM >= 4.
>
> Tested on riscv64-unknown-linux-gnu target, with FPU support.
> ---
> gdb/riscv-tdep.c | 2 +-
> gdb/testsuite/gdb.base/float.exp | 4 +++-
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
> index 69f2123dcdb..a3afab3b998 100644
> --- a/gdb/riscv-tdep.c
> +++ b/gdb/riscv-tdep.c
> @@ -1185,7 +1185,7 @@ riscv_print_one_register_info (struct gdbarch
> *gdbarch,
> "dynamic rounding mode",
> };
> int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
> - ? (d >> 5) : d) & 0x3;
> + ? (d >> 5) : d) & 0x7;
>
> gdb_printf (file, "%sFRM:%i [%s]",
> (regnum == RISCV_CSR_FCSR_REGNUM
> diff --git a/gdb/testsuite/gdb.base/float.exp
> b/gdb/testsuite/gdb.base/float.exp
> index 62e8346928b..10c0692a976 100644
> --- a/gdb/testsuite/gdb.base/float.exp
> +++ b/gdb/testsuite/gdb.base/float.exp
> @@ -112,14 +112,16 @@ if { [is_aarch64_target] } then {
> gdb_test "info float" "f0.*f1.*f31.*d0.*d30.*" "info float"
> } elseif [istarget "riscv*-*-*"] then {
> # RISC-V may or may not have an FPU
> + send_gdb "set \$frm = 7\n"
> gdb_test_multiple "info float" "info float" {
> - -re "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*$gdb_prompt $" {
> + -re "ft0.*ft1.*ft11.*fflags.*frm.*0x7.*FRM:7.*fcsr.*$gdb_prompt $"
> {
> pass "info float (with FPU)"
> }
> -re "No floating.point info available for this
> processor.*$gdb_prompt $" {
> pass "info float (without FPU)"
> }
> }
> + send_gdb "set \$frm = 0\n"
> } else {
> gdb_test "info float" "No floating.point info available for this
> processor." "info float (unknown target)"
> }
> --
> 2.35.1
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PING^2] [PATCH] RISC-V: fix FRM register display mask value
2022-08-03 18:45 ` [PING] " Hugues de Lassus
@ 2022-09-21 19:34 ` Hugues de Lassus
2022-09-21 19:34 ` Hugues de Lassus
2022-09-21 19:52 ` Hugues de Lassus
0 siblings, 2 replies; 6+ messages in thread
From: Hugues de Lassus @ 2022-09-21 19:34 UTC (permalink / raw)
To: gdb-patches
On Wed, Aug 3, 2022 at 11:45 AM Hugues de Lassus <hugues.delassus@sifive.com>
wrote:
> Ping.
>
> On Mon, Jul 11, 2022 at 10:58 AM Hugues de Lassus <
> hugues.delassus@sifive.com> wrote:
>
>> The FRM register is 3-bit long, but the top-most bit was masked off for
>> display, resulting in incorrectly displayed values and format strings
>> when FRM >= 4.
>>
>> Tested on riscv64-unknown-linux-gnu target, with FPU support.
>> ---
>> gdb/riscv-tdep.c | 2 +-
>> gdb/testsuite/gdb.base/float.exp | 4 +++-
>> 2 files changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
>> index 69f2123dcdb..a3afab3b998 100644
>> --- a/gdb/riscv-tdep.c
>> +++ b/gdb/riscv-tdep.c
>> @@ -1185,7 +1185,7 @@ riscv_print_one_register_info (struct gdbarch
>> *gdbarch,
>> "dynamic rounding mode",
>> };
>> int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
>> - ? (d >> 5) : d) & 0x3;
>> + ? (d >> 5) : d) & 0x7;
>>
>> gdb_printf (file, "%sFRM:%i [%s]",
>> (regnum == RISCV_CSR_FCSR_REGNUM
>> diff --git a/gdb/testsuite/gdb.base/float.exp
>> b/gdb/testsuite/gdb.base/float.exp
>> index 62e8346928b..10c0692a976 100644
>> --- a/gdb/testsuite/gdb.base/float.exp
>> +++ b/gdb/testsuite/gdb.base/float.exp
>> @@ -112,14 +112,16 @@ if { [is_aarch64_target] } then {
>> gdb_test "info float" "f0.*f1.*f31.*d0.*d30.*" "info float"
>> } elseif [istarget "riscv*-*-*"] then {
>> # RISC-V may or may not have an FPU
>> + send_gdb "set \$frm = 7\n"
>> gdb_test_multiple "info float" "info float" {
>> - -re "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*$gdb_prompt $" {
>> + -re "ft0.*ft1.*ft11.*fflags.*frm.*0x7.*FRM:7.*fcsr.*$gdb_prompt
>> $" {
>> pass "info float (with FPU)"
>> }
>> -re "No floating.point info available for this
>> processor.*$gdb_prompt $" {
>> pass "info float (without FPU)"
>> }
>> }
>> + send_gdb "set \$frm = 0\n"
>> } else {
>> gdb_test "info float" "No floating.point info available for this
>> processor." "info float (unknown target)"
>> }
>> --
>> 2.35.1
>>
>>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PING^2] [PATCH] RISC-V: fix FRM register display mask value
2022-09-21 19:34 ` [PING^2] " Hugues de Lassus
@ 2022-09-21 19:34 ` Hugues de Lassus
2022-09-21 19:52 ` Hugues de Lassus
1 sibling, 0 replies; 6+ messages in thread
From: Hugues de Lassus @ 2022-09-21 19:34 UTC (permalink / raw)
To: gdb-patches
[-- Attachment #1: Type: text/plain, Size: 2265 bytes --]
On Wed, Aug 3, 2022 at 11:45 AM Hugues de Lassus <hugues.delassus@sifive.com>
wrote:
> Ping.
>
> On Mon, Jul 11, 2022 at 10:58 AM Hugues de Lassus <
> hugues.delassus@sifive.com> wrote:
>
>> The FRM register is 3-bit long, but the top-most bit was masked off for
>> display, resulting in incorrectly displayed values and format strings
>> when FRM >= 4.
>>
>> Tested on riscv64-unknown-linux-gnu target, with FPU support.
>> ---
>> gdb/riscv-tdep.c | 2 +-
>> gdb/testsuite/gdb.base/float.exp | 4 +++-
>> 2 files changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
>> index 69f2123dcdb..a3afab3b998 100644
>> --- a/gdb/riscv-tdep.c
>> +++ b/gdb/riscv-tdep.c
>> @@ -1185,7 +1185,7 @@ riscv_print_one_register_info (struct gdbarch
>> *gdbarch,
>> "dynamic rounding mode",
>> };
>> int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
>> - ? (d >> 5) : d) & 0x3;
>> + ? (d >> 5) : d) & 0x7;
>>
>> gdb_printf (file, "%sFRM:%i [%s]",
>> (regnum == RISCV_CSR_FCSR_REGNUM
>> diff --git a/gdb/testsuite/gdb.base/float.exp
>> b/gdb/testsuite/gdb.base/float.exp
>> index 62e8346928b..10c0692a976 100644
>> --- a/gdb/testsuite/gdb.base/float.exp
>> +++ b/gdb/testsuite/gdb.base/float.exp
>> @@ -112,14 +112,16 @@ if { [is_aarch64_target] } then {
>> gdb_test "info float" "f0.*f1.*f31.*d0.*d30.*" "info float"
>> } elseif [istarget "riscv*-*-*"] then {
>> # RISC-V may or may not have an FPU
>> + send_gdb "set \$frm = 7\n"
>> gdb_test_multiple "info float" "info float" {
>> - -re "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*$gdb_prompt $" {
>> + -re "ft0.*ft1.*ft11.*fflags.*frm.*0x7.*FRM:7.*fcsr.*$gdb_prompt
>> $" {
>> pass "info float (with FPU)"
>> }
>> -re "No floating.point info available for this
>> processor.*$gdb_prompt $" {
>> pass "info float (without FPU)"
>> }
>> }
>> + send_gdb "set \$frm = 0\n"
>> } else {
>> gdb_test "info float" "No floating.point info available for this
>> processor." "info float (unknown target)"
>> }
>> --
>> 2.35.1
>>
>>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PING^2] [PATCH] RISC-V: fix FRM register display mask value
2022-09-21 19:34 ` [PING^2] " Hugues de Lassus
2022-09-21 19:34 ` Hugues de Lassus
@ 2022-09-21 19:52 ` Hugues de Lassus
2022-09-21 19:52 ` Hugues de Lassus
1 sibling, 1 reply; 6+ messages in thread
From: Hugues de Lassus @ 2022-09-21 19:52 UTC (permalink / raw)
To: gdb-patches
I see this issue has been fixed by Andrew, thanks! Please disregard my ping.
Best regards,
Hugues
On Wed, Sep 21, 2022 at 12:34 PM Hugues de Lassus <
hugues.delassus@sifive.com> wrote:
> On Wed, Aug 3, 2022 at 11:45 AM Hugues de Lassus <
> hugues.delassus@sifive.com> wrote:
>
>> Ping.
>>
>> On Mon, Jul 11, 2022 at 10:58 AM Hugues de Lassus <
>> hugues.delassus@sifive.com> wrote:
>>
>>> The FRM register is 3-bit long, but the top-most bit was masked off for
>>> display, resulting in incorrectly displayed values and format strings
>>> when FRM >= 4.
>>>
>>> Tested on riscv64-unknown-linux-gnu target, with FPU support.
>>> ---
>>> gdb/riscv-tdep.c | 2 +-
>>> gdb/testsuite/gdb.base/float.exp | 4 +++-
>>> 2 files changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
>>> index 69f2123dcdb..a3afab3b998 100644
>>> --- a/gdb/riscv-tdep.c
>>> +++ b/gdb/riscv-tdep.c
>>> @@ -1185,7 +1185,7 @@ riscv_print_one_register_info (struct gdbarch
>>> *gdbarch,
>>> "dynamic rounding mode",
>>> };
>>> int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
>>> - ? (d >> 5) : d) & 0x3;
>>> + ? (d >> 5) : d) & 0x7;
>>>
>>> gdb_printf (file, "%sFRM:%i [%s]",
>>> (regnum == RISCV_CSR_FCSR_REGNUM
>>> diff --git a/gdb/testsuite/gdb.base/float.exp
>>> b/gdb/testsuite/gdb.base/float.exp
>>> index 62e8346928b..10c0692a976 100644
>>> --- a/gdb/testsuite/gdb.base/float.exp
>>> +++ b/gdb/testsuite/gdb.base/float.exp
>>> @@ -112,14 +112,16 @@ if { [is_aarch64_target] } then {
>>> gdb_test "info float" "f0.*f1.*f31.*d0.*d30.*" "info float"
>>> } elseif [istarget "riscv*-*-*"] then {
>>> # RISC-V may or may not have an FPU
>>> + send_gdb "set \$frm = 7\n"
>>> gdb_test_multiple "info float" "info float" {
>>> - -re "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*$gdb_prompt $" {
>>> + -re "ft0.*ft1.*ft11.*fflags.*frm.*0x7.*FRM:7.*fcsr.*$gdb_prompt
>>> $" {
>>> pass "info float (with FPU)"
>>> }
>>> -re "No floating.point info available for this
>>> processor.*$gdb_prompt $" {
>>> pass "info float (without FPU)"
>>> }
>>> }
>>> + send_gdb "set \$frm = 0\n"
>>> } else {
>>> gdb_test "info float" "No floating.point info available for this
>>> processor." "info float (unknown target)"
>>> }
>>> --
>>> 2.35.1
>>>
>>>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PING^2] [PATCH] RISC-V: fix FRM register display mask value
2022-09-21 19:52 ` Hugues de Lassus
@ 2022-09-21 19:52 ` Hugues de Lassus
0 siblings, 0 replies; 6+ messages in thread
From: Hugues de Lassus @ 2022-09-21 19:52 UTC (permalink / raw)
To: gdb-patches
[-- Attachment #1: Type: text/plain, Size: 2517 bytes --]
I see this issue has been fixed by Andrew, thanks! Please disregard my ping.
Best regards,
Hugues
On Wed, Sep 21, 2022 at 12:34 PM Hugues de Lassus <
hugues.delassus@sifive.com> wrote:
> On Wed, Aug 3, 2022 at 11:45 AM Hugues de Lassus <
> hugues.delassus@sifive.com> wrote:
>
>> Ping.
>>
>> On Mon, Jul 11, 2022 at 10:58 AM Hugues de Lassus <
>> hugues.delassus@sifive.com> wrote:
>>
>>> The FRM register is 3-bit long, but the top-most bit was masked off for
>>> display, resulting in incorrectly displayed values and format strings
>>> when FRM >= 4.
>>>
>>> Tested on riscv64-unknown-linux-gnu target, with FPU support.
>>> ---
>>> gdb/riscv-tdep.c | 2 +-
>>> gdb/testsuite/gdb.base/float.exp | 4 +++-
>>> 2 files changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
>>> index 69f2123dcdb..a3afab3b998 100644
>>> --- a/gdb/riscv-tdep.c
>>> +++ b/gdb/riscv-tdep.c
>>> @@ -1185,7 +1185,7 @@ riscv_print_one_register_info (struct gdbarch
>>> *gdbarch,
>>> "dynamic rounding mode",
>>> };
>>> int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
>>> - ? (d >> 5) : d) & 0x3;
>>> + ? (d >> 5) : d) & 0x7;
>>>
>>> gdb_printf (file, "%sFRM:%i [%s]",
>>> (regnum == RISCV_CSR_FCSR_REGNUM
>>> diff --git a/gdb/testsuite/gdb.base/float.exp
>>> b/gdb/testsuite/gdb.base/float.exp
>>> index 62e8346928b..10c0692a976 100644
>>> --- a/gdb/testsuite/gdb.base/float.exp
>>> +++ b/gdb/testsuite/gdb.base/float.exp
>>> @@ -112,14 +112,16 @@ if { [is_aarch64_target] } then {
>>> gdb_test "info float" "f0.*f1.*f31.*d0.*d30.*" "info float"
>>> } elseif [istarget "riscv*-*-*"] then {
>>> # RISC-V may or may not have an FPU
>>> + send_gdb "set \$frm = 7\n"
>>> gdb_test_multiple "info float" "info float" {
>>> - -re "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*$gdb_prompt $" {
>>> + -re "ft0.*ft1.*ft11.*fflags.*frm.*0x7.*FRM:7.*fcsr.*$gdb_prompt
>>> $" {
>>> pass "info float (with FPU)"
>>> }
>>> -re "No floating.point info available for this
>>> processor.*$gdb_prompt $" {
>>> pass "info float (without FPU)"
>>> }
>>> }
>>> + send_gdb "set \$frm = 0\n"
>>> } else {
>>> gdb_test "info float" "No floating.point info available for this
>>> processor." "info float (unknown target)"
>>> }
>>> --
>>> 2.35.1
>>>
>>>
^ permalink raw reply [flat|nested] 6+ messages in thread
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Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2022-07-11 17:57 [PATCH] RISC-V: fix FRM register display mask value Hugues de Lassus
2022-08-03 18:45 ` [PING] " Hugues de Lassus
2022-09-21 19:34 ` [PING^2] " Hugues de Lassus
2022-09-21 19:34 ` Hugues de Lassus
2022-09-21 19:52 ` Hugues de Lassus
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