From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from transporter.internal.sifive.com (unknown [64.62.193.209]) by sourceware.org (Postfix) with ESMTPS id E9FF63858D1E for ; Mon, 11 Jul 2022 17:58:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E9FF63858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: from gamma21.internal.sifive.com (gamma21.internal.sifive.com [10.14.18.66]) by transporter.internal.sifive.com (Postfix) with ESMTP id F21BE201EE; Mon, 11 Jul 2022 10:58:01 -0700 (PDT) Received: by gamma21.internal.sifive.com (Postfix, from userid 1651) id ECA546030D; Mon, 11 Jul 2022 10:58:01 -0700 (PDT) From: Hugues de Lassus To: gdb-patches@sourceware.org Cc: Hugues de Lassus Subject: [PATCH] RISC-V: fix FRM register display mask value Date: Mon, 11 Jul 2022 10:57:46 -0700 Message-Id: <20220711175746.76137-1-hugues.delassus@sifive.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Jul 2022 17:58:04 -0000 The FRM register is 3-bit long, but the top-most bit was masked off for display, resulting in incorrectly displayed values and format strings when FRM >= 4. Tested on riscv64-unknown-linux-gnu target, with FPU support. --- gdb/riscv-tdep.c | 2 +- gdb/testsuite/gdb.base/float.exp | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 69f2123dcdb..a3afab3b998 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -1185,7 +1185,7 @@ riscv_print_one_register_info (struct gdbarch *gdbarch, "dynamic rounding mode", }; int frm = ((regnum == RISCV_CSR_FCSR_REGNUM) - ? (d >> 5) : d) & 0x3; + ? (d >> 5) : d) & 0x7; gdb_printf (file, "%sFRM:%i [%s]", (regnum == RISCV_CSR_FCSR_REGNUM diff --git a/gdb/testsuite/gdb.base/float.exp b/gdb/testsuite/gdb.base/float.exp index 62e8346928b..10c0692a976 100644 --- a/gdb/testsuite/gdb.base/float.exp +++ b/gdb/testsuite/gdb.base/float.exp @@ -112,14 +112,16 @@ if { [is_aarch64_target] } then { gdb_test "info float" "f0.*f1.*f31.*d0.*d30.*" "info float" } elseif [istarget "riscv*-*-*"] then { # RISC-V may or may not have an FPU + send_gdb "set \$frm = 7\n" gdb_test_multiple "info float" "info float" { - -re "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*$gdb_prompt $" { + -re "ft0.*ft1.*ft11.*fflags.*frm.*0x7.*FRM:7.*fcsr.*$gdb_prompt $" { pass "info float (with FPU)" } -re "No floating.point info available for this processor.*$gdb_prompt $" { pass "info float (without FPU)" } } + send_gdb "set \$frm = 0\n" } else { gdb_test "info float" "No floating.point info available for this processor." "info float (unknown target)" } -- 2.35.1