From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by sourceware.org (Postfix) with ESMTPS id C6D1F3858405 for ; Fri, 22 Jul 2022 21:02:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C6D1F3858405 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 26MEPh6t015132 for ; Fri, 22 Jul 2022 23:02:38 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3hf805f95u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 22 Jul 2022 23:02:38 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 77DE5100034 for ; Fri, 22 Jul 2022 23:02:38 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 7375E20972E for ; Fri, 22 Jul 2022 23:02:38 +0200 (CEST) Received: from jkgcxl0002.jkg.st.com (10.75.127.46) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2308.20; Fri, 22 Jul 2022 23:02:36 +0200 From: =?UTF-8?q?Torbj=C3=B6rn=20SVENSSON?= To: CC: =?UTF-8?q?Torbj=C3=B6rn=20SVENSSON?= , Yvan Roux Subject: [PATCH v3 1/2] gdb/arm: Use if-else if instead of switch Date: Fri, 22 Jul 2022 22:59:33 +0200 Message-ID: <20220722205930.2461429-2-torbjorn.svensson@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <1dde8763-9da8-1590-ac3f-06f0555bc14a@arm.com> References: <1dde8763-9da8-1590-ac3f-06f0555bc14a@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-07-22_06,2022-07-21_02,2022-06-22_01 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jul 2022 21:02:41 -0000 As the register number for the alternative Arm SP register are not contstant, it's not possible to use switch statement to define the rules. In order to not have a mix, replace the few existing switch-statement with regular if-else if statments. This patch is a preparation for the next one in the series. Signed-off-by: Torbjörn SVENSSON --- gdb/arm-tdep.c | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index d3b4fce98a3..7d0944f9e3f 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -3785,9 +3785,8 @@ arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, CORE_ADDR lr; ULONGEST cpsr; - switch (regnum) + if (regnum == ARM_PC_REGNUM) { - case ARM_PC_REGNUM: /* The PC is normally copied from the return column, which describes saves of LR. However, that version may have an extra bit set to indicate Thumb state. The bit is not @@ -3807,18 +3806,18 @@ arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); return frame_unwind_got_constant (this_frame, regnum, arm_addr_bits_remove (gdbarch, lr)); - - case ARM_PS_REGNUM: + } + else if (regnum == ARM_PS_REGNUM) + { /* Reconstruct the T bit; see arm_prologue_prev_register for details. */ cpsr = get_frame_register_unsigned (this_frame, regnum); lr = frame_unwind_register_unsigned (this_frame, ARM_LR_REGNUM); cpsr = reconstruct_t_bit (gdbarch, lr, cpsr); return frame_unwind_got_constant (this_frame, regnum, cpsr); - - default: - internal_error (__FILE__, __LINE__, - _("Unexpected register %d"), regnum); } + + internal_error (__FILE__, __LINE__, + _("Unexpected register %d"), regnum); } /* Implement the stack_frame_destroyed_p gdbarch method. */ @@ -4944,17 +4943,13 @@ arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, return; } - switch (regnum) + if (regnum == ARM_PC_REGNUM || regnum == ARM_PS_REGNUM) { - case ARM_PC_REGNUM: - case ARM_PS_REGNUM: reg->how = DWARF2_FRAME_REG_FN; reg->loc.fn = arm_dwarf2_prev_register; - break; - case ARM_SP_REGNUM: - reg->how = DWARF2_FRAME_REG_CFA; - break; } + else if (regnum == ARM_SP_REGNUM) + reg->how = DWARF2_FRAME_REG_CFA; } /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand -- 2.25.1