From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by sourceware.org (Postfix) with ESMTPS id D9A223858405 for ; Fri, 22 Jul 2022 21:03:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D9A223858405 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 26MEF3Qg015055 for ; Fri, 22 Jul 2022 23:03:20 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3hf805f97d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 22 Jul 2022 23:03:19 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 33AB110002A for ; Fri, 22 Jul 2022 23:03:19 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3022F20972F for ; Fri, 22 Jul 2022 23:03:19 +0200 (CEST) Received: from jkgcxl0002.jkg.st.com (10.75.127.46) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2308.20; Fri, 22 Jul 2022 23:03:16 +0200 From: =?UTF-8?q?Torbj=C3=B6rn=20SVENSSON?= To: CC: Yvan Roux , =?UTF-8?q?Torbj=C3=B6rn=20SVENSSON?= Subject: [PATCH v3 2/2] gdb/arm: Sync sp with other *sp registers Date: Fri, 22 Jul 2022 22:59:35 +0200 Message-ID: <20220722205930.2461429-3-torbjorn.svensson@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <1dde8763-9da8-1590-ac3f-06f0555bc14a@arm.com> References: <1dde8763-9da8-1590-ac3f-06f0555bc14a@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-07-22_06,2022-07-21_02,2022-06-22_01 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Jul 2022 21:03:22 -0000 From: Yvan Roux For Arm Cortex-M33 with security extensions, there are 4 different stack pointers (msp_s, msp_ns, psp_s, psp_ns), without security extensions and for other Cortex-M targets, there are 2 different stack pointers (msp and psp). With this patch, sp will always be in sync with one of the real stack pointers on Arm targets that contain more than one stack pointer. Signed-off-by: Torbjörn SVENSSON Signed-off-by: Yvan Roux --- gdb/arm-tdep.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 7d0944f9e3f..eaec2fd6b14 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -3815,6 +3815,78 @@ arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache, cpsr = reconstruct_t_bit (gdbarch, lr, cpsr); return frame_unwind_got_constant (this_frame, regnum, cpsr); } + else if (arm_is_alternative_sp_register (tdep, regnum)) + { + /* Handle the alternative SP registers on Cortex-M. */ + bool override_with_sp_value = false; + CORE_ADDR val; + + if (tdep->have_sec_ext) + { + CORE_ADDR sp + = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); + CORE_ADDR msp_s + = get_frame_register_unsigned (this_frame, + tdep->m_profile_msp_s_regnum); + CORE_ADDR msp_ns + = get_frame_register_unsigned (this_frame, + tdep->m_profile_msp_ns_regnum); + CORE_ADDR psp_s + = get_frame_register_unsigned (this_frame, + tdep->m_profile_psp_s_regnum); + CORE_ADDR psp_ns + = get_frame_register_unsigned (this_frame, + tdep->m_profile_psp_ns_regnum); + + bool is_msp = regnum == tdep->m_profile_msp_regnum + && (msp_s == sp || msp_ns == sp); + bool is_msp_s = regnum == tdep->m_profile_msp_s_regnum + && msp_s == sp; + bool is_msp_ns = regnum == tdep->m_profile_msp_ns_regnum + && msp_ns == sp; + bool is_psp = regnum == tdep->m_profile_psp_regnum + && (psp_s == sp || psp_ns == sp); + bool is_psp_s = regnum == tdep->m_profile_psp_s_regnum + && psp_s == sp; + bool is_psp_ns = regnum == tdep->m_profile_psp_ns_regnum + && psp_ns == sp; + + override_with_sp_value = is_msp || is_msp_s || is_msp_ns + || is_psp || is_psp_s || is_psp_ns; + + } + else if (tdep->is_m) + { + CORE_ADDR sp + = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); + CORE_ADDR msp + = get_frame_register_unsigned (this_frame, + tdep->m_profile_msp_regnum); + CORE_ADDR psp + = get_frame_register_unsigned (this_frame, + tdep->m_profile_psp_regnum); + + bool is_msp = regnum == tdep->m_profile_msp_regnum && sp == msp; + bool is_psp = regnum == tdep->m_profile_psp_regnum && sp == psp; + + override_with_sp_value = is_msp || is_psp; + } + + if (override_with_sp_value) + { + /* Use value of SP from previous frame. */ + struct frame_info *prev_frame = get_prev_frame (this_frame); + if (prev_frame) + val = get_frame_register_unsigned (prev_frame, ARM_SP_REGNUM); + else + val = get_frame_base (this_frame); + } + else + /* Use value for the register from previous frame. */ + val = get_frame_register_unsigned (this_frame, regnum); + + return frame_unwind_got_constant (this_frame, regnum, val); + } internal_error (__FILE__, __LINE__, _("Unexpected register %d"), regnum); @@ -4934,6 +5006,8 @@ arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, struct dwarf2_frame_state_reg *reg, struct frame_info *this_frame) { + arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch); + if (is_pacbti_pseudo (gdbarch, regnum)) { /* Initialize RA_AUTH_CODE to zero. */ @@ -4950,6 +5024,12 @@ arm_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, } else if (regnum == ARM_SP_REGNUM) reg->how = DWARF2_FRAME_REG_CFA; + else if (arm_is_alternative_sp_register (tdep, regnum)) + { + /* Handle the alternative SP registers on Cortex-M. */ + reg->how = DWARF2_FRAME_REG_FN; + reg->loc.fn = arm_dwarf2_prev_register; + } } /* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand -- 2.25.1