From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from forward100p.mail.yandex.net (forward100p.mail.yandex.net [IPv6:2a02:6b8:0:1472:2741:0:8b7:100]) by sourceware.org (Postfix) with ESMTPS id 6C6D338582BF for ; Mon, 8 Aug 2022 13:02:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6C6D338582BF Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=syntacore.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=syntacore.com Received: from sas1-1f4a002bb12a.qloud-c.yandex.net (sas1-1f4a002bb12a.qloud-c.yandex.net [IPv6:2a02:6b8:c14:3908:0:640:1f4a:2b]) by forward100p.mail.yandex.net (Yandex) with ESMTP id 871684F0A60A for ; Mon, 8 Aug 2022 16:02:07 +0300 (MSK) Received: by sas1-1f4a002bb12a.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id NY4TSU7xCq-26haf3dH; Mon, 08 Aug 2022 16:02:06 +0300 (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (Client certificate not present) X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=syntacore.com; s=mail; t=1659963727; bh=4mk5GF1cqnlcgGCg9V7QaIu/PMtQkTGXm7EzhqUZO2s=; h=Message-Id:Date:Cc:Subject:To:From; b=usthki+PR85TdL184kGIvLg9KOv0rp/kLZ2cOtB1MIGW39exj/AaUHTHObL31/Chb XIlWnH+3SUCEXSWWFEsHqIp4eTqTEl/prmQSwzh7XOqFpP03uZD07r3bO7QM0e99G4 qgN7LMUuMntlTY2u00AdjfopHvf4EWGchiVD/jy4= Authentication-Results: sas1-1f4a002bb12a.qloud-c.yandex.net; dkim=pass header.i=@syntacore.com From: Mark Goncharov To: gdb-patches@sourceware.org Cc: mga-sc Subject: [PATCH] [gdb/riscv] Fix test for riscv: zero register. Date: Mon, 8 Aug 2022 16:01:47 +0300 Message-Id: <20220808130147.2715849-1-mark.goncharov@syntacore.com> X-Mailer: git-send-email 2.37.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 08 Aug 2022 13:02:15 -0000 From: mga-sc x0 register in riscv must have permanent value. We already have test for that: gdb/testsuite/riscv-reg-aliases.exp. This patch fixes 4 test drops. --- gdb/riscv-tdep.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 2d41be96b20..20b613075d5 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -933,6 +933,12 @@ riscv_register_name (struct gdbarch *gdbarch, int regnum) return name; } +static int +riscv_cannot_store_register (struct gdbarch *gdbarch, int regnum) +{ + return regnum == RISCV_ZERO_REGNUM; +} + /* Construct a type for 64-bit FP registers. */ static struct type * @@ -3822,6 +3828,9 @@ riscv_gdbarch_init (struct gdbarch_info info, registers, no matter what the target description called them. */ set_gdbarch_register_name (gdbarch, riscv_register_name); + /* Zero register must have permanent value. */ + set_gdbarch_cannot_store_register (gdbarch, riscv_cannot_store_register); + /* Override the register group callback setup by the target description mechanism. This allows us to force registers into the groups we want, ignoring what the target tells us. */ -- 2.37.1