On Wed, Aug 3, 2022 at 11:45 AM Hugues de Lassus wrote: > Ping. > > On Mon, Jul 11, 2022 at 10:58 AM Hugues de Lassus < > hugues.delassus@sifive.com> wrote: > >> The FRM register is 3-bit long, but the top-most bit was masked off for >> display, resulting in incorrectly displayed values and format strings >> when FRM >= 4. >> >> Tested on riscv64-unknown-linux-gnu target, with FPU support. >> --- >> gdb/riscv-tdep.c | 2 +- >> gdb/testsuite/gdb.base/float.exp | 4 +++- >> 2 files changed, 4 insertions(+), 2 deletions(-) >> >> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c >> index 69f2123dcdb..a3afab3b998 100644 >> --- a/gdb/riscv-tdep.c >> +++ b/gdb/riscv-tdep.c >> @@ -1185,7 +1185,7 @@ riscv_print_one_register_info (struct gdbarch >> *gdbarch, >> "dynamic rounding mode", >> }; >> int frm = ((regnum == RISCV_CSR_FCSR_REGNUM) >> - ? (d >> 5) : d) & 0x3; >> + ? (d >> 5) : d) & 0x7; >> >> gdb_printf (file, "%sFRM:%i [%s]", >> (regnum == RISCV_CSR_FCSR_REGNUM >> diff --git a/gdb/testsuite/gdb.base/float.exp >> b/gdb/testsuite/gdb.base/float.exp >> index 62e8346928b..10c0692a976 100644 >> --- a/gdb/testsuite/gdb.base/float.exp >> +++ b/gdb/testsuite/gdb.base/float.exp >> @@ -112,14 +112,16 @@ if { [is_aarch64_target] } then { >> gdb_test "info float" "f0.*f1.*f31.*d0.*d30.*" "info float" >> } elseif [istarget "riscv*-*-*"] then { >> # RISC-V may or may not have an FPU >> + send_gdb "set \$frm = 7\n" >> gdb_test_multiple "info float" "info float" { >> - -re "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*$gdb_prompt $" { >> + -re "ft0.*ft1.*ft11.*fflags.*frm.*0x7.*FRM:7.*fcsr.*$gdb_prompt >> $" { >> pass "info float (with FPU)" >> } >> -re "No floating.point info available for this >> processor.*$gdb_prompt $" { >> pass "info float (without FPU)" >> } >> } >> + send_gdb "set \$frm = 0\n" >> } else { >> gdb_test "info float" "No floating.point info available for this >> processor." "info float (unknown target)" >> } >> -- >> 2.35.1 >> >>