From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by sourceware.org (Postfix) with ESMTPS id 024323858CDB for ; Wed, 21 Sep 2022 19:34:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 024323858CDB Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-ed1-x536.google.com with SMTP id e18so10289600edj.3 for ; Wed, 21 Sep 2022 12:34:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :from:to:cc:subject:date; bh=TDZ8Z/ypYvjsSUs3OHGLO/nE6rOaDzNB8UNmsno+d2A=; b=UCwFz4hwt7EkmFVxh+GPvQ/q1HYEmB01dl5BpVs/kYK7OZMuwVjcxi6JjikRFzYMvz 3rsX4dp5F6gbbGYpMW/6d69EqmJgZqzUn5a5LpxOGvCBqgtAm7rhtEua6oIUlyDutzth MUCnuAUNfC+JDfnRNIfC+incat7tespGh4lyTT2JgVTm9PwDGS36b9ZKa3bilk1gLMGa oDSQpUB/wTKr1y8SO+v4++hJA3jCmyPs/F8nRNggK90h6+Ofv5wECEdmgWPtaHikj8fV d1yJ7LTjdHOuZ1af1igFOuAmlYlBskivBBLIx1TRPwkDTughdPyHscpkxDjvQ+NCOEas bMvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :x-gm-message-state:from:to:cc:subject:date; bh=TDZ8Z/ypYvjsSUs3OHGLO/nE6rOaDzNB8UNmsno+d2A=; b=exA1f6ImIU9bU+WBl5Bf1KeeOU+L/mpHMI7wT/c+FEG88hNGVHg+jKgpAFhl6EJBjy UPeY7i+QBMjtNBnn2hnCN/AAcqeycWLmRnLI0Ityj4L783gvHDoSec160s2RHUUtG/Xn kRCOSNJ1191LF6MZkq4G48jPgsSE9gUt1UTJhmJncwT1mquSjT5JlZqmLTBDLWO4d6SZ 00W/oYYJIuiN3+GxrcomoZFvocfMvUaotKPJKYWj8F9+uNn8e5MKdCPCiJkYLo3gjnPa zGUxUzb9qQuzPoXPfAY3J9S1TAoYxjqUd6qRNvZbXSSxD4T8BH6yP9kedmK8L8APfK8x EjXg== X-Gm-Message-State: ACrzQf1B0PRMLxFOs8RCYxQ8EbuSuY1fnncbljKVFvnVRFO0KYvqfWzB aK+TYeueUodjUWDkr9fJpmyMSMtjsoqtG8UitR0Bdz7XUMQ= X-Google-Smtp-Source: AMsMyM7dfVdz1ZYFHQQVeMORKjoCc8kJn3hQkfkLD5kKuVvLWC5Y+B+SMoFb+unf1l+NZYPcskSR3zaM8Uf6Tn8ZOnc= X-Received: by 2002:a05:6402:51cc:b0:454:c988:48f0 with SMTP id r12-20020a05640251cc00b00454c98848f0mr4684884edd.74.1663788897654; Wed, 21 Sep 2022 12:34:57 -0700 (PDT) MIME-Version: 1.0 References: <20220711175746.76137-1-hugues.delassus@sifive.com> In-Reply-To: From: Hugues de Lassus Date: Wed, 21 Sep 2022 12:34:46 -0700 Message-ID: Subject: [PING^2] [PATCH] RISC-V: fix FRM register display mask value To: gdb-patches@sourceware.org Content-Type: multipart/alternative; boundary="00000000000039ec3d05e9350aaf" X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Message-ID: <20220921193446.-j-QThWPO9giCsxGr2enk2t3g_CAZX4-okRnKteTY6g@z> --00000000000039ec3d05e9350aaf Content-Type: text/plain; charset="UTF-8" On Wed, Aug 3, 2022 at 11:45 AM Hugues de Lassus wrote: > Ping. > > On Mon, Jul 11, 2022 at 10:58 AM Hugues de Lassus < > hugues.delassus@sifive.com> wrote: > >> The FRM register is 3-bit long, but the top-most bit was masked off for >> display, resulting in incorrectly displayed values and format strings >> when FRM >= 4. >> >> Tested on riscv64-unknown-linux-gnu target, with FPU support. >> --- >> gdb/riscv-tdep.c | 2 +- >> gdb/testsuite/gdb.base/float.exp | 4 +++- >> 2 files changed, 4 insertions(+), 2 deletions(-) >> >> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c >> index 69f2123dcdb..a3afab3b998 100644 >> --- a/gdb/riscv-tdep.c >> +++ b/gdb/riscv-tdep.c >> @@ -1185,7 +1185,7 @@ riscv_print_one_register_info (struct gdbarch >> *gdbarch, >> "dynamic rounding mode", >> }; >> int frm = ((regnum == RISCV_CSR_FCSR_REGNUM) >> - ? (d >> 5) : d) & 0x3; >> + ? (d >> 5) : d) & 0x7; >> >> gdb_printf (file, "%sFRM:%i [%s]", >> (regnum == RISCV_CSR_FCSR_REGNUM >> diff --git a/gdb/testsuite/gdb.base/float.exp >> b/gdb/testsuite/gdb.base/float.exp >> index 62e8346928b..10c0692a976 100644 >> --- a/gdb/testsuite/gdb.base/float.exp >> +++ b/gdb/testsuite/gdb.base/float.exp >> @@ -112,14 +112,16 @@ if { [is_aarch64_target] } then { >> gdb_test "info float" "f0.*f1.*f31.*d0.*d30.*" "info float" >> } elseif [istarget "riscv*-*-*"] then { >> # RISC-V may or may not have an FPU >> + send_gdb "set \$frm = 7\n" >> gdb_test_multiple "info float" "info float" { >> - -re "ft0.*ft1.*ft11.*fflags.*frm.*fcsr.*$gdb_prompt $" { >> + -re "ft0.*ft1.*ft11.*fflags.*frm.*0x7.*FRM:7.*fcsr.*$gdb_prompt >> $" { >> pass "info float (with FPU)" >> } >> -re "No floating.point info available for this >> processor.*$gdb_prompt $" { >> pass "info float (without FPU)" >> } >> } >> + send_gdb "set \$frm = 0\n" >> } else { >> gdb_test "info float" "No floating.point info available for this >> processor." "info float (unknown target)" >> } >> -- >> 2.35.1 >> >> --00000000000039ec3d05e9350aaf--