From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by sourceware.org (Postfix) with ESMTPS id EB4143858D37 for ; Wed, 5 Oct 2022 08:49:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org EB4143858D37 Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2957tLKM004423; Wed, 5 Oct 2022 10:49:08 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3jxaym6324-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Oct 2022 10:49:07 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4047F100034; Wed, 5 Oct 2022 10:49:03 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 2BBD9216ECA; Wed, 5 Oct 2022 10:49:03 +0200 (CEST) Received: from jkgcxl0002.jkg.st.com (10.75.127.45) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2375.31; Wed, 5 Oct 2022 10:49:01 +0200 From: =?UTF-8?q?Torbj=C3=B6rn=20SVENSSON?= To: CC: , , , , =?UTF-8?q?Torbj=C3=B6rn=20SVENSSON?= , Yvan ROUX Subject: [PATCH v5] gdb/arm: Handle lazy FPU state preservation Date: Wed, 5 Oct 2022 10:48:30 +0200 Message-ID: <20221005084829.265088-1-torbjorn.svensson@foss.st.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG2NODE3.st.com (10.75.127.6) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-04_09,2022-09-29_03,2022-06-22_01 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 05 Oct 2022 08:49:15 -0000 Read LSPEN, ASPEN and LSPACT bits from FPCCR and use them together with FPCAR to identify if lazy FPU state preservation is active for the current frame. See "Lazy context save of FP state", in B1.5.7, also ARM AN298, supported by Cortex-M4F architecture for details on lazy FPU register stacking. The same conditions are valid for other Cortex-M cores with FPU. This patch has been verified on a STM32F4-Discovery board by: a) writing a non-zero value (lets use 0x1122334455667788 as an example) to all the D-registers in the main function b) configured the SysTick to fire c) in the SysTick_Handler, write some other value (lets use 0x0022446688aaccee as an example) to one of the D-registers (D0 as an example) and then do "SVC #0" d) in the SVC_Handler, write some other value (lets use 0x0099aabbccddeeff) to one of the D-registers (D0 as an example) In GDB, suspend the execution in the SVC_Handler function and compare the value of the D-registers for the SVC_handler frame and the SysTick_Handler frame. With the patch, the value of the modified D-register (D0) should be the new value (0x009..eff) on the SVC_Handler frame, and the intermediate value (0x002..cee) for the SysTick_Handler frame. Now compare the D-register value for the SysTick_Handler frame and the main frame. The main frame should have the initial value (0x112..788). Signed-off-by: Torbjörn SVENSSON Signed-off-by: Yvan ROUX --- gdb/arch/arm.h | 7 ++++++- gdb/arm-tdep.c | 56 +++++++++++++++++++++++++++++++++++--------------- 2 files changed, 46 insertions(+), 17 deletions(-) diff --git a/gdb/arch/arm.h b/gdb/arch/arm.h index 36757493406..d384b952144 100644 --- a/gdb/arch/arm.h +++ b/gdb/arch/arm.h @@ -115,7 +115,12 @@ enum system_register_address : CORE_ADDR /* M-profile Floating-Point Context Control Register address, defined in ARMv7-M (Section B3.2.2) and ARMv8-M (Section D1.2.99) reference manuals. */ - FPCCR = 0xe000ef34 + FPCCR = 0xe000ef34, + + /* M-profile Floating-Point Context Address Register address, defined in + ARMv7-M (Section B3.2.2) and ARMv8-M (Section D1.2.98) reference + manuals. */ + FPCAR = 0xe000ef38 }; /* Instruction condition field values. */ diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 2810232fcb8..d357066653b 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -3588,27 +3588,48 @@ arm_m_exception_cache (struct frame_info *this_frame) if (extended_frame_used) { ULONGEST fpccr; + ULONGEST fpcar; /* Read FPCCR register. */ gdb_assert (safe_read_memory_unsigned_integer (FPCCR, ARM_INT_REGISTER_SIZE, byte_order, &fpccr)); - bool fpccr_ts = bit (fpccr, 26); - /* This code does not take into account the lazy stacking, see "Lazy - context save of FP state", in B1.5.7, also ARM AN298, supported - by Cortex-M4F architecture. - To fully handle this the FPCCR register (Floating-point Context - Control Register) needs to be read out and the bits ASPEN and - LSPEN could be checked to setup correct lazy stacked FP registers. - This register is located at address 0xE000EF34. */ + /* Read FPCAR register. */ + if (!safe_read_memory_unsigned_integer (FPCAR, ARM_INT_REGISTER_SIZE, + byte_order, &fpcar)) + { + warning (_("Could not fetch FPCAR content. Further unwinding of " + "FP register values will be unreliable.")); + fpcar = 0; + } + + bool fpccr_aspen = bit (fpccr, 31); + bool fpccr_lspen = bit (fpccr, 30); + bool fpccr_ts = bit (fpccr, 26); + bool fpccr_lspact = bit (fpccr, 0); + + /* The LSPEN and ASPEN bits indicate if the lazy state preservation + for FP registers is enabled or disabled. The LSPACT bit indicate, + together with FPCAR, if the lazy state preservation feature is + active for the current frame or for another frame. + See "Lazy context save of FP state", in B1.5.7, also ARM AN298, + supported by Cortex-M4F architecture for details. */ + bool fpcar_points_to_this_frame = ((unwound_sp + sp_r0_offset + 0x20) + == (fpcar & ~0x7)); + bool read_fp_regs_from_stack = (!(fpccr_aspen && fpccr_lspen + && fpccr_lspact + && fpcar_points_to_this_frame)); /* Extended stack frame type used. */ - CORE_ADDR addr = unwound_sp + sp_r0_offset + 0x20; - for (int i = 0; i < 8; i++) + if (read_fp_regs_from_stack) { - cache->saved_regs[ARM_D0_REGNUM + i].set_addr (addr); - addr += 8; + CORE_ADDR addr = unwound_sp + sp_r0_offset + 0x20; + for (int i = 0; i < 8; i++) + { + cache->saved_regs[ARM_D0_REGNUM + i].set_addr (addr); + addr += 8; + } } cache->saved_regs[ARM_FPSCR_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x60); @@ -3617,11 +3638,14 @@ arm_m_exception_cache (struct frame_info *this_frame) && fpccr_ts) { /* Handle floating-point callee saved registers. */ - addr = unwound_sp + sp_r0_offset + 0x68; - for (int i = 8; i < 16; i++) + if (read_fp_regs_from_stack) { - cache->saved_regs[ARM_D0_REGNUM + i].set_addr (addr); - addr += 8; + CORE_ADDR addr = unwound_sp + sp_r0_offset + 0x68; + for (int i = 8; i < 16; i++) + { + cache->saved_regs[ARM_D0_REGNUM + i].set_addr (addr); + addr += 8; + } } arm_cache_set_active_sp_value (cache, tdep, -- 2.25.1